JPH09307820A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the solid-state image pickup device in which number of pins for a drive IC and number of wires are not increased even when kinds of pulses required to drive a solid-state image pickup element are increased, which has ease of provision for a solid-state image pickup element of a different type and whose size is made small. SOLUTION: The solid-state image pickup device is provided with a solid- state image pickup element 6 and a drive IC 4, and the drive IC 4 provides an output of serial data Dsi. The solid-state image pickup device is also provided with a serial parallel conversion circuit 7 converting the serial data Dsi into parallel data V1-4, CH1 and CH2 and a pulse generating circuit 8 to generate pulses ΦV1-4 based on the parallel data V1-4, CH1 and CH2. Preferably the logic level of the serial data Dsi and a transfer clock CLK is changed only for a horizontal blanking period of a television signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device including a solid-state image pickup element and an IC for driving the same, and more particularly, to improvement of a drive circuit for the solid-state image pickup element.

[0002]

2. Description of the Related Art A camera using a solid-state image pickup device is widely used in both industrial and consumer fields, and it is desired to reduce the cost and size of the solid-state image pickup device. On the other hand, the solid-state image pickup element used in the solid-state image pickup device has been improved in performance and function, and the types of pulses required for driving have been increased accordingly.

FIG. 5 shows a block diagram of a conventional solid-state image pickup device. This solid-state imaging device includes a solid-state imaging device (hereinafter referred to as “area CCD”) 1, a driving IC (hereinafter referred to as “TG”) 2, a circuit for synthesizing a pulse for driving a vertical CCD (hereinafter referred to as “V driver”). It is composed of 3). Here, an area CCD composed of a vertical CCD composed of four-phase gates and a horizontal CCD composed of two-phase gates
Will be described as an example.

The timing chart of FIG. 6 shows pulses V1 to C4 which are output from TG2 and input to V driver 3.
H1 and CH2, and pulse voltages ΦV1 to 4 output from the V driver 3 and applied to the area CCD 1 are shown. Here, V1 to 4, CH1 and CH2 change between 0V and 5V corresponding to binary values, and ΦV1 and Φ
V3 varies between -7V, 0V, and 15V corresponding to the ternary value, and φV2 and φV4 vary between -7V and 0V corresponding to the binary value.

Six types of pulses V1 to 4, CH1 and CH2 supplied from the TG2 to the V driver 3 are voltage-converted in the V driver 3 and combined to output ΦV1 to 4 from the V driver 3. For example, V1 is voltage-converted into an amplitude of -7V to 0V after logically inverting the amplitude of 0V to 5V, and CH1 is voltage-converted into an amplitude of 0V to 15V after logically inverting the amplitude of 0V to 5V. , And are combined into ΦV1. Similarly, V3 and CH2 are combined through logic inversion and voltage conversion to become ΦV3. V2
And V4, the amplitude of 0V to 5V is logically inverted, and then the voltage is converted to the amplitude of -7V to 0V to become ΦV2 and ΦV4, respectively.

ΦV1 to φ4 are applied to the vertical CCDs forming the area CCD 1. The φH1, φH2, and φR output from the TG2 are directly applied to the horizontal CCD and the output gate that form the area CCD1.

[0007]

However, in the conventional solid-state image pickup device as described above, each time the number of types of pulses required to drive the solid-state image pickup element (area CCD 1) increases,
The number of pins and the number of wires of the driving IC (TG2) increase, which becomes a factor that makes it difficult to reduce the size and cost of the camera. Therefore, it is an object of the present invention to provide a solid-state imaging device in which the number of pins and wirings of a CCD driving LSI does not increase even if the types of driving pulses of the solid-state imaging device increase.

[0008]

To achieve the above object, a solid-state image pickup device according to the present invention is a solid-state image pickup device comprising a solid-state image pickup element and a driving IC for the solid-state image pickup device, wherein the driving ICs are connected in series. A serial-parallel conversion circuit that is configured to output data and that converts the serial data into parallel data, and a pulse generation circuit that generates a pulse for driving the solid-state imaging device from the parallel data are further provided. It is characterized by With such a configuration, even if the types of pulses required to drive the solid-state image sensor increase, the driving IC
The output from is only serial data (and the clock for transfer), and the number of pins and wiring does not increase.

It is preferable that the logic change of the serial data and the clock for transfer is performed only during the horizontal blanking period of the television signal. Further, by configuring the serial-parallel conversion circuit, the pulse generation circuit, and the solid-state image pickup device on the same semiconductor substrate, it is possible to reduce the size and cost of the device.

Preferably, when L, M and N are 0 or a natural number and n is a natural number of 4 or more, the driving IC is (L + 2 × M + (n-1) × N) bits of serial data. And the serial-parallel conversion circuit outputs (L + 2 × M +
(N-1) × N) serial data of (L + 2 × M +
(N-1) * N) parallel data is converted, and the pulse generation circuit drives (L + 2 * M + (n-1) * N) parallel data from binary drive pulses L and ternary. It is configured to generate M pulses and N driving pulses of n values and apply them to the solid-state imaging device.

In another preferred configuration example, when L, M, and N are 0 or a natural number and n is a natural number of 4 or more, the driving IC indicates the position of logical change of the parallel data (2 × (L + 2 × M + (n-1) × N)) serial data is output, and the serial-parallel conversion circuit outputs (2 ×
(L + 2 * M + (n-1) * N)) serial data is converted into (L + 2 * M + (n-1) * N) parallel data, and the pulse generation circuit (L + 2 * M + (n-). 1)
From the (N) parallel data, L binary driving pulses, M ternary driving pulses and N n driving pulses are generated and applied to the solid-state image sensor. In this case, more preferably, each bit forming the serial data is arranged in the order of logical change of the pulse for driving the solid-state image sensor.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. First, FIG. 1 shows a configuration diagram of a solid-state imaging device according to the first embodiment. This solid-state image pickup device is composed of an area CCD 6, a TG 4, and a V driver 5. The V driver 5 includes a serial-parallel conversion circuit 7 that converts serial data into parallel data, and a pulse generation circuit 8 that synthesizes a pulse for driving a vertical CCD from the output parallel data. Here, an area CCD composed of a vertical CCD having four-phase gates and a horizontal CCD having two-phase gates will be described as an example.

As shown in FIG. 1, the serial data Dsi output from the TG 4 and its clock CLK are input to the V driver 5. Then, the serial data is converted into parallel data by the serial-parallel conversion circuit 7 in the V driver 5, and V1 to C
It becomes H1 and CH2. This parallel data V1-4,
CH1 and CH2 are substantially the same as the pulses in the conventional device shown in the time chart of FIG.

Parallel data V1-4, CH1, and CH
2 is input to the pulse generation circuit 8 in the V driver 5, where the voltage conversion and synthesis processing is performed as in the V driver in the conventional device, and the driving pulses ΦV1 to 4 are output. The pulses ΦV1 to 4 are vertical CCs of the area CCD 6.
ΦH1, CH2, which is applied to D and output from TG4,
And φR are directly applied to the horizontal CCD of the area CCD 6 and the output gate, so that the same CC as the conventional device can be obtained.
A D signal output is obtained.

The serial data format (first data format) at this time is, for example, as shown in FIG.
1 for each pulse for 1 and CH2
One bit is allocated to make 6-bit serial data.
For example, in the horizontal blanking period, one cycle (6 clocks) is output each time V1 to V4 changes, and the serial data is changed. In this way, each bit (pulse) can be set freely. Also, the number of clocks per cycle for changing all the pulses can be small.

An example of another (second) serial data format is shown in FIG.
Shown in In this example, V1-4, CH1, and CH2
Separate bits are provided to control the rising and falling edges of the pulse. For example, in the horizontal blanking period,
A clock for one cycle is output every time V1 to V4 changes, and only the bit corresponding to the changing pulse in the serial data is changed. In this serial data format, only the change point information of each pulse needs to be set in the serial data.

As yet another example, in the third serial data format shown in FIG. 4, the horizontal blanking period and the pixel reading period are divided into V1 to CH4, CH1 and CH2 pulse rise and fall. Each bit to be arranged is arranged in the changing order of each pulse. For example, in the horizontal blanking period, V3 ↓, V1 ↑,
Place each bit such as V4 ↓, V2 ↑ ...
The clock is output once each time the logic changes. In this serial data format, it is not necessary for the V driver to input the clock or data for one cycle to refresh the data each time each pulse is changed, and it is sufficient to input only one clock for each pulse change. .

Here, the circuit for generating a pulse from the rising edge and the falling edge of each data can be constructed by using, for example, an RS flip-flop or a latch 9 as shown in FIG.

Examples of each of the above serial data formats are:
There are two binary drive pulses (ΦV2 and ΦV4) and two three-value drive pulses (Φ) in the vertical CCD that constitutes the area CCD 6.
This is the case where V1 and ΦV3 are applied, and 2 + 2 × 2 = 6 pieces of parallel data (V1 to 4, CH1, and CH2) are input to the pulse generation circuit 8 that generates these pulses. Therefore, in the first serial data format, 6 bits form one cycle of serial data, and in the second and third serial data formats, 2 × 6 = 12 bits form one cycle of serial data. Composed.

In general, when L, M, and N are 0 or a natural number and n is a natural number of 4 or more, and CC
When L binary drive pulses, M three drive pulses and N n drive pulses are applied to D, the drive IC is (L + 2 × M + (n−) in the first serial data format.
1) × N) bits of serial data are output, and second and third
In the serial data format of, the driving IC is (2 × (L + 2 × M
+ (N−1) × N)) serial data is output.
Then, in any of the data formats, the serial-parallel conversion circuit converts the data into (L + 2 × M + (n−1) × N) pieces of parallel data and supplies the parallel data to the pulse generation circuit. The pulse generation circuit
2 from (L + 2 × M + (n−1) × N) pieces of parallel data
L drive pulses of three values, M drive pulses of three values, and N drive pulses of n values are generated and applied to the solid-state imaging device.

The V driver 5 and the area CCD 6 may be formed on different semiconductor substrates or may be formed on the same substrate. In the above embodiment, the area CC
Regarding the drive pulse applied to the D vertical CCD, the number of pins and wiring of the drive LSI are reduced by adding the serial-parallel conversion circuit, but the present invention is also applied to the pulse applied to the horizontal CCD. You can also

Although the above embodiment relates to an interline type area CCD, the present invention is not limited to this, and can be applied to a solid-state image pickup device such as a FIT-CCD having a storage portion.

[0023]

As described above, according to the solid-state image pickup device of the present invention, even if the number of pulses required for driving the solid-state image pickup element increases, the number of pins and wirings of the driving IC does not increase.
It is possible to reduce the size and cost of the device. Further, it becomes easy to deal with the case where the solid-state image sensor used in the apparatus is replaced with a different one.

[Brief description of drawings]

FIG. 1 is a block diagram of a solid-state imaging device according to an embodiment of the invention.

FIG. 2 is a diagram showing an example of serial data and a clock output from a driving IC in the solid-state imaging device of FIG.

3 is a diagram showing another example of serial data and clocks output from a driving IC in the solid-state imaging device of FIG.

4 is a diagram showing still another example of serial data and clocks output from the driving IC in the solid-state imaging device of FIG.

FIG. 5 is a block diagram of a conventional solid-state imaging device.

FIG. 6 is a timing chart of each pulse in the solid-state imaging device.

FIG. 7 is a diagram showing an example of a circuit for generating the clock pulse of FIG.

[Explanation of symbols]

 1,4 Image sensor driving IC (TG) 2,5 V driver 3,6 Area CCD 7 Serial / parallel conversion circuit 8 Pulse generation circuit

Claims (6)

[Claims] 1. A solid-state imaging device comprising a solid-state imaging device and an IC for driving the solid-state imaging device, wherein the driving IC is configured to output serial data, and serial-parallel conversion of the serial data into parallel data. The solid-state imaging device further comprising a conversion circuit and a pulse generation circuit that generates a pulse for driving the solid-state imaging device from the parallel data. 2. The solid-state imaging device according to claim 1, wherein the serial data and the transfer clock are logically changed only during a horizontal blanking period of a television signal. 3. The solid-state imaging device according to claim 1, wherein the serial-parallel conversion circuit, the pulse generation circuit, and the solid-state imaging device are formed on the same semiconductor substrate. 4. L, M, and N are 0 or a natural number,
When n is a natural number of 4 or more, the driving IC outputs (L + 2 × M + (n−1) × N) bits of serial data, and the serial-parallel conversion circuit outputs (L + 2 × M + (n−
1) × N) serial data of (L + 2 × M + (n−
1) .times.N) parallel data, and the pulse generation circuit converts (L + 2.times.M + (n-1) .times.N) parallel data from L binary drive pulses and M ternary drive pulses. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is configured to generate N driving pulses of n values and apply the driving pulses to the solid-state imaging device. 5. L, M, and N are 0 or a natural number,
When n is a natural number of 4 or more, the driving IC indicates the position of logical change of the parallel data (2 × (L + 2 ×
M + (n-1) × N)) serial data is output,
The serial-parallel conversion circuit is (2 × (L + 2 × M + (n−1)
XN)) serial data of (L + 2 * M + (n-
1) .times.N) parallel data, and the pulse generation circuit converts (L + 2.times.M + (n-1) .times.N) parallel data from L binary drive pulses and M ternary drive pulses. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is configured to generate N driving pulses of n values and apply the driving pulses to the solid-state imaging device. 6. Each bit constituting the serial data comprises:
6. The solid-state imaging device according to claim 5, wherein the solid-state imaging devices are arranged in the order of logical change of pulses for driving the solid-state imaging device.