JP3122562B2 - Circuit for driving charge transfer element - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer element suitably used for a two-dimensional image sensor and the like, and more particularly to a method for driving a charge transfer element employing a multi-phase drive system of three or more phases, and to a method for implementing the method. Circuit.

[0002]

2. Description of the Related Art As a transfer system of a charge transfer device (CTD) such as a charge-coupled device (CCD) used as a two-dimensional image sensor, there is no charge transfer direction in a phase and one electrode corresponds to one. It is roughly divided into a multi-phase driving system having three or more phases, and a two-phase driving system having two electrodes corresponding to one, having a direction of charge transfer in each phase.

Here, the multi-phase driving method has an advantage that a large amount of charge that can be transferred is obtained, but has a disadvantage that it is not suitable for high-speed transfer. Conversely, the two-phase driving method has an advantage that the transfer speed can be increased, but has a disadvantage that the amount of charge that can be transferred is small.

For these reasons, a two-dimensional image sensor is generally an example of a multi-phase drive system in a vertical transfer unit which has a low transfer rate and requires a high charge density.
A two-phase driving method is adopted for a horizontal transfer unit that requires high-speed driving.

FIGS. 5 and 6 show a conventional method for driving a four-phase drive type charge transfer device. In the illustrated example, a CCD having a buried channel structure is illustrated.

FIG. 5 shows a cross section of an element according to a transfer method.
1A, a CCD is formed on a surface area of a P-type semiconductor substrate 1;
An N-type semiconductor layer is formed over the entire transfer channel. Thereby, a buried channel layer is formed in the surface region of P-type semiconductor substrate 1. A first-layer transfer electrode 4 and a second-layer transfer electrode 5 are alternately formed on the surface of the semiconductor substrate 1 via a thin insulating film 3 such as SiO _{2 in the} transfer direction. I have.

The transfer electrodes 4 have transfer waveforms (transfer clock pulses) φ ₁ and φ _{3 having the} waveforms shown in FIGS.
Is applied. FIG. 6B shows the transfer electrode 5.
Transfer clocks φ ₂ and φ ₄ having the waveform shown in FIG.

[0008]

In the above-described four-phase driving method, as shown in FIG. 5B, the signal accumulation area becomes 50% or more of the bit length, and the effective potential corresponds to the clock amplitude. Since the potential difference V _C can be obtained, there is an advantage that a large amount of charge can be transferred.

However, when the signal charge under the φ ₂ gate is transferred to the φ ₃ gate at the time when the time t ₁ changes from t ₁ to t ₂ in FIG. 6, as shown in FIG. At the final time point, the gradient of the potential, that is, the fringe electric field hardly works. Because of this, it takes time to transfer,
There is a possibility that some charges may flow backward, and there is a problem that transfer deterioration during high-speed driving is large.

As a technique for solving such a problem, there is one proposed by the present applicant in Japanese Patent Application No. 1-142592. FIG. 7A shows the element structure, and FIG. 7B shows a potential distribution diagram. In this proposal, a transfer direction is provided in each transfer electrode. That is, a potential step is formed by implanting impurity ions, and thereby the direction of transfer is determined. According to such a configuration, the fringe electric field works even at the final point of the transfer even in the four-phase drive, so that the transfer efficiency can be increased.

In FIG. 7A, 1 is a P-type semiconductor substrate, 2 is a buried channel layer, 3 is an insulating film, 4
Denotes a first-layer transfer electrode, 5 denotes a second-layer transfer electrode, 6 denotes a first region doped with an N-type impurity, 7 denotes a second region doped with a P-type impurity, respectively. Is shown.

However, in this prior art, since the structure of the transfer electrode is complicated, if such a transfer electrode is to be manufactured, a complicated process is required, so that it takes time to manufacture and the yield is reduced. However, there is a disadvantage that the cost is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve such problems of the prior art, and has a transfer efficiency of a multi-phase drive type charge transfer element while having a simple transfer electrode structure similar to the prior art. It is an object of the present invention to provide a method of driving a charge transfer element capable of increasing the charge transfer rate. Another object of the present invention is to provide a circuit suitable for implementing such a driving method.

[0014]

According to the driving method of the present invention, a plurality of transfer electrodes are formed on a surface of a semiconductor substrate via an insulating film, and a transfer clock applied to the transfer electrodes is provided. In a method of driving a charge transfer element using a multi-phase driving method of three or more phases in which one phase is provided per transfer electrode, the voltage level of the transfer clock corresponding to each phase is set to high when the potential of the transfer channel becomes deep. On the other hand, when the potential becomes shallow, it is set to low level,
In addition, for each transfer cycle of each transfer clock, the high level is once held at an intermediate level between the high level and the low level for a certain period of time, during which time the low level is only one phase and then changed to the low level. As a result, the above object is achieved.

Further, a circuit according to the present invention used for implementing the above-mentioned driving method includes an AND circuit for outputting an AND output of a transfer clock of two phases of the respective phases, the high level voltage and the high level. A transistor circuit connected to an external power supply that supplies two kinds of voltages of の of the above, and having a first transistor to which the AND output is input and a second transistor to which an inverted output of the AND output is input And the power supply voltage is connected to the transistor circuit, and when the AND output is at a high level, the power supply voltage is の of the high level, while when the AND output is at a low level, the power supply voltage is at a high level; When an inverted output of any one of the transfer clocks of the phases other than the two phases is input, the signal is once held from a high level to an intermediate level between a high level and a low level for a certain period, And an inverter for outputting a transfer clock changing waveform to the low level after,
Thereby, the above object is achieved.

[0016]

According to the driving method of the multi-phase driving method as described above, since the fringe electric field is formed even at the end of the transfer cycle, the backflow of the electric charge is reliably prevented. Therefore, the transfer efficiency during high-speed driving can be significantly improved.

[0017] The reason why the fringe electric field is formed, at the time of change from the time t ₁ in FIG. 2 to t _2, the signal charges under the phi ₂ gate phi ₃ gate side (transfer clock phi _2, phi ₃ is applied that each transfer electrode phi ₂ gates, referred to as phi ₃ gates)
Taking as an example the case of forwarding to
When t _1, phi ₂ voltage under the gate, as shown in FIG. 2 (B), is held in the V _H / 2 level. Therefore, the potential under the φ ₂ gate becomes V _C / 2, which is intermediate V _C , as shown in FIG. Therefore, as shown in FIG.
gradient of the potential towards the phi ₂ gate phi ₃ gate, i.e. fringe electric field is formed.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example in which the method of driving a charge transfer device according to the present invention is applied to a four-phase drive type CCD. This CCD is an n-channel type CCD using electrons as electric charges. In FIG. 1 (A) showing a cross section of the element according to the transfer method, an N-type semiconductor is formed over the entire surface of the P-type semiconductor substrate 1 in the CCD transfer channel. A layer is formed. Thereby, a buried channel layer is formed in the surface region of P-type semiconductor substrate 1. On the surface of the semiconductor substrate 1, SiO ₂
The first-layer transfer electrodes 4 and the second-layer transfer electrodes 5 are alternately formed in the transfer direction via a thin insulating film 3.

Transfer clocks φ ₁ and φ ₃ having waveforms shown in FIGS. 2A and 2C are applied to the transfer electrode 4. Further, transfer clocks φ ₂ and φ ₄ having waveforms shown in FIGS. 2B and 2D are applied to the transfer electrode 5.

As shown in FIGS. 2A, 2B, 2C, and 2D, each transfer clock φ ₁ , φ ₂ , φ ₃ , φ ₄
Is high level V _H [V] and low level is 0
[V]. Then, each transfer clock φ ₁ , φ ₂ ,
φ ₃ and φ ₄ are temporarily held at an intermediate level V _H / 2 [V] for a certain period of time when they change from a high level to a low level. The CCD is driven by the transfer clocks φ ₁ , φ ₂ , φ ₃ , φ _{4 having} such a waveform.
FIG. 1B is a potential distribution diagram showing the state of charge transfer at such a drive timing.

In such a driving method, the signal charge under the φ ₂ gate is transferred to the φ ₃ gate side at the point of time when it changes from time t ₁ to t ₂ in FIG. 2 (corresponding to the end of the transfer cycle). Suppose that As shown in FIG.
= T ₁ , since the voltage of the φ ₂ gate is held at the intermediate V _H / 2 level, the potential under the φ ₂ gate is
As shown in FIG. 1 (B), the voltage is intermediate V _C / 2. Therefore, as shown in FIG. 1 (B), a potential gradient toward the phi ₃ gate from phi ₂ gate, i.e. fringe electric field is formed.

When such a fringe electric field is formed at the end of the transfer cycle, the charge transfer is quickly performed,
The charge does not flow back. Therefore, according to such a driving method, the transfer efficiency can be remarkably improved in the charge transfer element of the multi-phase driving method. In addition, there is an advantage that the element structure of the charge transfer element can be the same as the element structure of the conventional example.

In the above driving method, the period during which the voltage level of the transfer clock is maintained at the intermediate V _H / 2 level can be set to about ８ of one cycle of the four-phase clock. Therefore, a sufficient period for charge transfer can be secured.

FIG. 3 shows a circuit configuration of a circuit used for implementing the above driving method. FIG. 4 shows the operation timing. As shown in FIGS. 4A to 4D, each transfer electrode is provided with a transfer clock φ similar to that of the conventional four-phase drive.
₁ ′, φ ₂ ′, φ ₃ ′, and φ ₄ ′ are applied. Then, in the circuit of FIG. 3, the transfer clocks φ ₃ ′ and φ ₄ ′ are input to the AND circuit 10, and the AND circuit 10 outputs φ ₃ ′ · φ ₄ ′ (see FIG. 4E).

The outputs φ ₃ ′ and φ ₄ ′ are connected to the transistor T ₁
Given to. The transistor T ₂ is supplied with inverted φ ₃ ′ · φ ₄ ′ whose polarity is inverted by the inverter 11. In addition, this circuit includes transistors T ₃ and T ₄
Is connected.

Note that T ₁ , T ₂ , and T ₃ are p-channel enhancement MOS transistors, and T ₄ is an n-channel enhancement MOS transistor.

In the above circuit, the external power supply is V _H , V _H
/ 2 power supply, and output φ ₃ '· φ ₄ ' of AND circuit 10
To T ₁ and its inverted signal, inverted φ ₃ ′ · φ ₄ ′, to T ₂ , the power supply voltage of the inverter 12 becomes φ ₃ ′
When φ ₄ ′ is at a high level, it is V _H / 2, and when it is at a low level, it is V _H. Accordingly, when the inverted φ ₂ ′, which is the inverted output of the transfer clock φ ₂ ′, is input to the inverter 12, the output has the waveform of the desired φ ₂ (see FIG. 4 (F)). That is,
Transfer clock transfer clock phi ₂ and the waveform shown in FIG. 2 (B) is obtained.

Here, as shown in FIGS. 4D and 4F, by using the φ ₃ ′ · φ ₄ ′ signal, the point in time when φ ₂ changes from the high level to the intermediate level is φ ₄ ′. At the time when the low level changes to the high level.

If the circuit shown in FIG. 3 is used, the transfer clocks φ ₁ , φ ₃ , φ _{4 having the} waveforms shown in FIGS. 2A, 2C, and 2D can be obtained by using the conventional transfer clock. Can be obtained. That is, if the circuit shown in FIG. 3 is used, the above-described method for driving the charge transfer element of the present invention can be reliably realized.

In the above embodiment, the case where the present invention is applied to a four-phase drive type charge transfer device has been described. However, the present invention is similarly applied to a three-phase or more drive type charge transfer device excluding four phases. It is possible.

In the above description, the case where the clock amplitude _VH is 1/2 as an intermediate level between the high level and the low level is taken as an example. However, the present invention is not limited to this. Needless to say, any level of both may be used as long as a certain potential difference is obtained with respect to the low level.

[0033]

According to the method of driving a charge transfer device according to the present invention , in a multi-phase drive type charge transfer device, a fringe electric field acts even at the end of a transfer cycle, so that there is an advantage that transfer efficiency can be remarkably improved. is there. In addition, since the device structure can be implemented only by changing the driving method without changing the conventional simple structure, the cost does not increase. And, in the driving circuit of the present invention,
According to the method for driving such a charge transfer device is implemented
Circuit can be realized.

[0034]

[Brief description of the drawings]

1A and 1B are diagrams illustrating an operation of a method for driving a charge transfer element according to the present invention, wherein FIG. 1A is a cross-sectional view of the charge transfer element, and FIG.

FIG. 2 is a timing chart showing a method of driving the charge transfer device of FIG.

FIG. 3 is a circuit diagram showing a circuit for obtaining a transfer clock waveform shown in FIG. 2;

FIG. 4 is a timing chart showing an operation procedure for obtaining a transfer clock waveform shown in FIG. 2;

5A and 5B are diagrams illustrating a method of driving a charge transfer element in a conventional example, wherein FIG. 5A is a cross-sectional view of the charge transfer element, and FIG.

FIG. 6 is a timing chart showing a method of driving a charge transfer element in a conventional example.

FIGS. 7A and 7B are diagrams showing a method of driving a charge transfer element proposed by the applicant of the present application, wherein FIG. 7A is a cross-sectional view of the charge transfer element, and FIG.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 2 buried channel layer 3 insulating film 4 first layer transfer electrode 5 second layer transfer electrode 10 AND circuit 11 inverter 12 inverter T ₁ , T ₂ , T ₃ p-channel enhancement type MO
S transistor T ₄ n-channel enhancement type MOS transistor

Claims (1)

(57) [Claims] A plurality of transfer electrodes are formed on a surface of a semiconductor substrate with an insulating film interposed therebetween, and a transfer clock applied to the transfer electrodes is one phase per transfer electrode. the method of driving a charge transfer device which takes the phase drive method,
The voltage level of the transfer clock corresponding to each phase is set to a high level when the potential of the transfer channel is deep, while it is set to a low level when the potential is shallow, and is set to a high level every transfer cycle of each transfer clock. From the high level to the low level once, and during this period, the low level is set to only one phase, and thereafter, the circuit is used for implementing the driving method of the charge transfer element in which the low level is changed to the low level. , outputs an aND output of the transfer clock of two phases of said phase
And a high level voltage and the high level
External power supply that supplies two types of voltage
A first transistor connected and receiving the AND output
And the second to which the inverted output of the AND output is input.
A transistor circuit having a transistor , and an AND output connected to the transistor circuit,
When the power supply voltage becomes half of the high level when
On the other hand, when the AND output is at a low level, the power supply voltage is high.
Level, and one of the phases other than the two
When the inverted output of the transmission clock is input,
Once fixed at an intermediate level between high level and low level
The waveform is held for a period and then changes to low level.
Charge transfer including an inverter for outputting a transmission clock
Element driving circuit.