JP6675998B2 - TDI type linear image sensor and driving method thereof - Google Patents

Description

  The present invention relates to a TDI-type linear image sensor used in the field of remote sensing and the like, and a driving method thereof.

  Many image sensors having a large number of photodetectors arranged in an array on a semiconductor substrate and having a signal charge readout circuit and an output amplifier on the same substrate have been developed. In remote sensing, a two-dimensional image of the earth's surface is captured by mounting a linear image sensor with photodetectors arranged in a one-dimensional array on an artificial satellite or the like and matching the direction perpendicular to the array with the direction of travel of the satellite. I do. To improve the image resolution, it is desirable to reduce the pixel pitch as much as possible. However, there is a problem that the amount of incident light is reduced by the reduction in the area of the photodetector, and the S / N ratio is deteriorated.

  As a sophisticated means for improving the S / N ratio, a TDI (Time Delay and Integration) image sensor has been developed. The TDI method uses a two-dimensional image sensor, an FFT (full frame transfer) type CCD (Charge Coupled Device), and synchronizes the timing of charge transfer with the movement timing of a subject image to improve S / N. , A CCD image sensor reading method. In the case of remote sensing, the TDI operation can be realized by adjusting the vertical charge transfer to the moving speed of the satellite. When an M-stage TDI operation is performed by the vertical CCD, the accumulation time is effectively increased by M times, so that the sensitivity is improved by M times and the S / N is improved by √M times.

  Since the sensitivity of a TDI image sensor changes in proportion to the number of TDI stages, it is desirable that the number of TDI stages can be switched in accordance with the luminance of the subject. As one of the methods for realizing the function of switching the number of TDI stages, for example, a method described in Patent Document 1 has been proposed. Patent Literature 1 is configured to switch the transfer direction of a vertical CCD between a forward direction and a reverse direction on an upstream side and a downstream side of a predetermined pixel row, and outputs only charges transferred in a forward direction as a signal. You. At this time, the number of TDI stages can be arbitrarily set by controlling the switching position in the transfer direction by a stage number switching circuit including a vertical shift register and a line selection circuit.

  Further, a bidirectional TDI has been proposed in which a transfer direction in a TDI operation is switched between a forward direction and a reverse direction depending on how an external clock is applied. Patent Document 2 discloses, as an example of such a bidirectional TDI, a back-illuminated image sensor in which light is incident from the back surface of a substrate. In the image sensor of Patent Literature 2, the vertical transfer clock is externally provided via a drive pad conversion substrate joined by metal bumps. In Patent Literature 2, the transfer direction of the TDI operation based on the vertical transfer clock is controlled to reduce the time required for imaging in the TDI operation.

  Also, in a CCD image sensor, an MPP (Multi Pinned Phase) operation is known as a technique for reducing the output when a pixel is dark. In a CCD, a potential well is formed in a transfer channel according to a voltage applied to a transfer electrode, and charge transfer is performed by moving the potential well according to a clock operation. According to the MPP operation, by applying a sufficiently low negative voltage to the transfer electrode to cause pinning under the electrode to an inverted state, generation of thermally excited electrons at the oxide film interface is suppressed, and the pixel dark current is reduced.

Japanese Patent No. 4968227 Japanese Patent No. 5941659

  The inventor of the present application has studied applying the MPP operation to a TDI image sensor. In a TDI-type image sensor, using a negative voltage that enables an MPP operation as a transfer clock is considered to be advantageous in terms of noise reduction.

  In addition, the upper limit of the amount of charge that can be transferred in the TDI operation (that is, the amount of saturated charge of a pixel) is determined by the area and depth of the potential well. The depth of the potential well corresponds to the voltage amplitude of the transfer clock, and the larger the voltage amplitude of the transfer clock, the more charges can be transferred. Since the area of the potential well tends to shrink as pixels become finer, it is necessary to deepen the potential well in order to secure a dynamic range. Therefore, it is considered that increasing the clock voltage amplitude by using a negative voltage as the transfer clock in the TDI-type image sensor is also advantageous in terms of expanding the dynamic range.

  In the study of the inventor of the present application as described above, in the conventional TDI-type image sensor as disclosed in Patent Documents 1 and 2, a transfer clock is applied to the transfer electrode via a stage number switching circuit for controlling the TDI operation. This has revealed the problem that a negative voltage cannot be used for the transfer clock (details will be described later).

  SUMMARY OF THE INVENTION It is an object of the present invention to provide a TDI-type linear image sensor which can use a negative voltage for a transfer clock applied to a transfer electrode in a TDI-type image sensor having a function of controlling a TDI operation by an external clock.

  A TDI-type linear image sensor according to the present invention includes a pixel group, a plurality of selection lines, a line selection circuit, and a horizontal transfer unit. In the pixel group, two-dimensionally arranged pixels having transfer electrodes for performing photoelectric conversion, time-delay integration of generated charges, and vertical transfer are performed. The plurality of selection lines are connected to each of the transfer electrodes and supply a multi-phase transfer clock. The line selection circuit selects a transfer clock to be supplied to a predetermined one of the plurality of select lines in the multi-phase transfer clock. The horizontal transfer unit horizontally transfers the charge subjected to the time delay integration. A pixel group, a plurality of selection lines, and a horizontal transfer unit are formed on a first semiconductor substrate. The line selection circuit is formed on a second semiconductor substrate electrically connected to the first semiconductor substrate. The substrate potential of the first semiconductor substrate and the substrate potential of the second semiconductor substrate are electrically independent.

  Also, in the driving method of the TDI-type linear image sensor according to the present invention, the step of setting the substrate potential of the second semiconductor substrate to be lower than the substrate potential of the first semiconductor substrate; And outputting a signal based on the low potential. The low potential of the signal output by the line selection circuit is lower than the substrate potential of the first semiconductor substrate.

  According to the TDI linear image sensor and the driving method thereof according to the present invention, a potential lower than the substrate potential of the first semiconductor substrate can be set as the substrate potential of the second semiconductor substrate. This makes it possible to use a negative voltage for the transfer clock applied to the transfer electrode in a TDI image sensor having a function of controlling the TDI operation using an external clock.

FIG. 2 is a block diagram illustrating a configuration of a TDI-type linear image sensor according to Embodiment 1 of the present invention. FIG. 2 is a perspective view showing a schematic structure of a TDI-type linear image sensor according to Embodiment 1. FIG. 2 is a cross-sectional view illustrating a cross-sectional structure of the TDI-type linear image sensor according to the first embodiment. FIG. 3 is a circuit diagram of a circuit formed on a first semiconductor substrate in the TDI-type linear image sensor according to the first embodiment. FIG. 3 is a block diagram showing a circuit configuration of a circuit formed on a second semiconductor substrate in the TDI-type linear image sensor according to the first embodiment. FIG. 2 is a circuit diagram showing a configuration of a unit cell circuit of a line selection circuit in the TDI-type linear image sensor according to the first embodiment. FIG. 2 is a circuit diagram showing a configuration of a unit cell circuit of a shift register circuit in the TDI-type linear image sensor according to the first embodiment. FIGS. 3A and 3B are a circuit diagram and a cross-sectional view illustrating a structure of a transmission gate used in the TDI-type linear image sensor according to Embodiment 1. FIGS. 4 is a timing chart of a vertical transfer clock supplied to a four-phase drive CCD for driving a TDI-type linear image sensor. FIG. 2 is a schematic diagram showing a cross-sectional structure of a four-phase drive CCD along a charge transfer direction and a change in potential of a transfer channel in the cross-section in a time series. FIG. 3 is a schematic diagram showing a cross-sectional structure of a four-phase drive CCD along a charge transfer direction and a potential change of a transfer channel in the cross-section in a time series. 5 is an example of a clock timing chart given to a TDI stage number switching circuit in the TDI-type linear image sensor according to the first embodiment. FIG. 3 is a diagram for explaining an operation of a TDI stage number switching circuit in the TDI-type linear image sensor according to the first embodiment. FIG. 4 is a diagram for explaining a TDI stage number switching circuit method in the TDI linear image sensor according to the first embodiment; FIG. 9 is a block diagram illustrating a configuration of a TDI-type linear image sensor according to Embodiment 2 of the present invention. FIG. 9 is a circuit diagram showing a configuration of a unit cell circuit of a clock driver circuit in a TDI-type linear image sensor according to a second embodiment. FIG. 9 is a block diagram illustrating a configuration of a TDI-type linear image sensor according to Embodiment 3 of the present invention. FIG. 13 is a circuit diagram showing a configuration of a unit cell circuit of a clock driver circuit in a TDI-type linear image sensor according to a third embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. It is to be noted that components denoted by the same reference numerals are the same or equivalent, and this is common in the entire text of the specification.

Embodiment 1 FIG.
In the first embodiment, a TDI-type linear image sensor capable of controlling switching of the number of TDI stages is configured using first and second semiconductor substrates having mutually independent substrate potentials. The configuration of the TDI linear image sensor according to the first embodiment will be described below.

1. Configuration The overall configuration of the TDI linear image sensor according to the present embodiment will be described with reference to FIGS.

  FIG. 1 is a block diagram showing a configuration of a TDI-type linear image sensor according to Embodiment 1 of the present invention. As shown in FIG. 1, the TDI-type linear image sensor according to the present embodiment includes a first semiconductor substrate 1, a second semiconductor substrate 2, a pixel array 3, a horizontal CCD 5, an output amplifier 6, and a bump. 8, select lines 15 and 16, and a TDI stage number switching circuit 13.

  The first semiconductor substrate 1 forms a CCD chip. The second semiconductor substrate 2 forms a CMOS chip. The pixel array 3 is an example of a pixel group in which pixels having transfer electrodes described below are two-dimensionally arranged in an array. Hereinafter, as shown in FIG. 1, the horizontal direction in which the pixels are arranged in the pixel array 3 is referred to as “X direction”, and the vertical direction is referred to as “Y direction”. Further, the + Y direction may be referred to as “upper” and the −Y direction may be referred to as “downward”.

  The horizontal CCD 5 is an example of a horizontal transfer unit that horizontally transfers the charge delayed and integrated in the pixel array 3. The output amplifier 6 is provided to read the output of the horizontal CCD 5 to the outside. The TDI stage number switching circuit 13 is a circuit for executing a TDI stage number setting operation described later.

  In the TDI-type linear image sensor according to the present embodiment, the pixel array 3, the horizontal CCD 5, and the output amplifier 6 are provided on the first semiconductor substrate 1, and the TDI stage number switching circuit 13 is provided on the second semiconductor substrate 2. The substrate potentials Vsub1 and Vsub2 are respectively independently applied to the first semiconductor substrate 1 and the second semiconductor substrate 2 as described above. This makes it possible to set the low-level voltage of the multi-phase transfer clock φV to be applied to the TDI-type linear image sensor to a negative voltage (hereinafter, the low levels of various clocks φV and φT are described as “L” and the high levels are "H").

  FIG. 2 is a perspective view showing a schematic structure of the TDI type linear image sensor shown in FIG. Hereinafter, as shown in FIG. 2, the thickness direction of the first semiconductor substrate 1 orthogonal to the X direction and the Y direction is referred to as “Z direction”.

  In FIG. 2, the pixel array 3 is formed by arranging pixels in a two-dimensional array in a specific region on the + Z side main surface (front surface) of the first semiconductor substrate 1. A plurality of input / output pads 4 are formed on the + Z-side main surface of the first semiconductor substrate 1 together with the horizontal CCD 5 and the output amplifier 6.

  The second semiconductor substrate 2 is a separate substrate from the first semiconductor substrate 1, and mounts a CMOS transistor circuit such as a line selection circuit described later. The second semiconductor substrate 2 is coupled to the first semiconductor substrate 1 on the + Z side with its main surfaces facing each other.

  FIG. 3 is a cross-sectional structural view taken along line A-A ′ of the TDI-type linear image sensor shown in FIG. FIG. 3 shows a state in which the TDI type linear image sensor is mounted on a package.

  As shown in FIG. 3, the first semiconductor substrate 1 and the second semiconductor substrate 2 are electrically joined by bumps 8 made of metal, and in FIG. 3 are further adhered on a package 9 made of ceramic or the like. I have. Further, the input / output pads 4 on the first semiconductor substrate 1 and the metal electrodes 10 on the package 9 are electrically connected by wire bonds 11. A lead 12 is formed on the main surface (back surface) on the −Z side of the package 9.

  Returning to FIG. 1, the bump 8 connects the selection line 15 for selecting a pixel in the pixel array 3 on the first semiconductor substrate 1 to the corresponding selection line 16 on the second semiconductor substrate 2 by bump bonding. To form a joint.

  Further, on the first semiconductor substrate 1, an input pin for the multi-phase transfer clock ΦV and a setting terminal for setting the substrate potential Vsub1 are provided corresponding to the input / output pads 4 (FIG. 2). . The setting terminal of the substrate potential Vsub1 is grounded, for example.

  The second semiconductor substrate 2 has a setting terminal for setting a substrate potential Vsub2, input pins for various clocks ΦV and ΦT, supply terminals for various power supply voltages Vdd and Vss, and a setting terminal for a well potential Vwell. Is provided. The setting terminal of the substrate potential Vsub2 is connected to, for example, a constant voltage source of a predetermined negative voltage. The predetermined negative voltage is a voltage lower than the ground potential (GND potential) of the substrate potential Vsub1, and is appropriately set, for example, from the viewpoint of enabling the above-described MPP operation.

  Hereinafter, a circuit configuration on the first semiconductor substrate 1 and a circuit configuration on the second semiconductor substrate 2 will be described.

1-1. Circuit Configuration on First Semiconductor Substrate FIG. 4 is a circuit diagram showing a circuit configuration formed on the first semiconductor substrate 1 in the TDI-type linear image sensor shown in FIG.

  As shown in FIG. 4, on the first semiconductor substrate 1, the pixels 17 are arranged in a two-dimensional array to form a pixel array 3. A region indicated by a bold broken frame in FIG. 4 is a boundary line schematically illustrating a boundary between the pixels 17. Note that the pixel here generates an image signal, and is the minimum repeating unit of the array of the vertical transfer gates 20 and the separation regions 21 arranged on the linear image sensor.

  As shown in FIG. 4, the pixel array 3 of the first semiconductor substrate 1 has a plurality of stages in the vertical direction (Y direction). In each stage, a plurality of pixels 17 arranged in the horizontal direction (X direction) are connected to common selection lines 15a to 15d.

  The horizontal CCD 5 is arranged on the −Y side of the pixel array 3 via the charge accumulation unit 19. As will be described later, the signal charges that have been time-delay integrated by the plurality of pixels 17 are transferred vertically downward (−Y direction) toward the horizontal CCD 5 in the pixel array 3, and further transferred horizontally (+ X direction) in the horizontal CCD 5. ) Is read from the output amplifier 6.

  Further, on the side (+ Y side) of the pixel array 3 opposite to the arrangement of the horizontal CCD 5, a charge discharging drain 18 for discharging unnecessary charges is provided.

  In the present embodiment, a four-phase drive CCD is used for TDI transfer in the vertical direction (Y direction) (see FIGS. 9 to 11). The pixel 17 includes a set of four transfer gates 20 corresponding to the first to fourth transfer clocks φV1 to φV4 forming the multi-phase transfer clock φV. The transfer electrodes 20a, 20b, 20c, and 20d in the pixel 17 are made of polysilicon, and are sequentially arranged on the Si substrate. A transfer channel (not shown) is formed below the transfer electrodes 20a to 20d. The transfer channel is electrically isolated from the Si substrate by an isolation region 21 made of an impurity region of the opposite conductivity type.

  The two transfer electrodes 20a and 20c in the transfer gate 20 are connected to the input pins of the first transfer clock φV1 via metal wires 15a and 15c, contact holes 22a and 22c, and metal wires 23a and 23c, respectively, as select lines. 24a and the input pin 24c of the third transfer clock φV3. The remaining two transfer electrodes 20b and 20d are connected to bump pads 34b and 34d via metal wires 15b and 15d, which are selection lines, respectively.

1-2. Circuit Configuration on Second Semiconductor Substrate FIG. 5 is a block diagram showing a circuit configuration of the TDI stage number switching circuit 13 formed on the second semiconductor substrate 2 in the TDI type linear image sensor shown in FIG. .

  As shown in FIG. 5, the TDI stage number switching circuit 13 on the second semiconductor substrate 2 includes a line selection circuit 28 and a vertical shift register 33. The line selection circuit 28 is connected to the metal wires 26b and 26d. The second and fourth transfer clocks φV2 and φV4 are input to the metal wires 26b and 26d via input pins 27b and 27d, respectively. The vertical shift register 33 is connected to the three metal wires 31. Input clocks φT1, φT2, and φTS from the outside are input to the respective metal wirings 31 via input pins 32.

  The bump pads 35b and 35d on the second semiconductor substrate 2 and the bump pads 34b and 34d (FIG. 4) on the first semiconductor substrate 1 are in a one-to-one relationship via the metal bumps 8. Connected. Thereby, the selection lines 15b and 15d on the first semiconductor substrate 1 are connected to the metal wirings 16b and 16d on the second semiconductor substrate 1 on a one-to-one basis.

  The line selection circuit 28 is configured by arranging unit cell circuits 25 each composed of a selection MOS transistor group by the number of vertical pixels. FIG. 6 is a circuit diagram of the unit cell circuit 25 of the line selection circuit 28.

  As shown in FIG. 6, the unit cell circuit 25 in the line selection circuit 28 includes four transmission gates 38a, 38b, 38c, 38d and two inverters 39a, 39b. Each transmission gate 38 is formed by pairing one NMOS transistor 36 and one PMOS transistor 37. The operation of the line selection circuit 28 including the unit cell circuit 25 will be described later.

  Returning to FIG. 5, the vertical shift register 33 is configured by arranging unit cell circuits 30 of the shift register by the number of vertical pixels. FIG. 7 is a circuit diagram of the unit cell circuit 30 of the vertical shift register 33.

  As shown in FIG. 7, the unit cell circuit 30 of the vertical shift register 33 includes two transmission gates 40a and 40b and two inverters 41a and 41b. Each transmission gate 40a, 40b is composed of an NMOS transistor. The transmission gates 40a, 40b and the inverters 41a, 41b are alternately connected in series. The operation of the vertical shift register 33 including the unit cell circuit 30 will be described later.

2. Operation Hereinafter, the operation of the TDI-type linear image sensor according to the present embodiment will be described with reference to the drawings.

  In the TDI type linear image sensor (FIG. 1) according to the present embodiment, for example, the substrate potential Vsub1 of the first semiconductor substrate 1 is set to the GND potential (= 0 V), and the substrate potential Vsub2 of the second semiconductor substrate 2 is set to a negative potential. Set to voltage (<0V). This makes it possible to set the L voltage (low-level voltage) of the transfer clocks φV1 to φV4 to a negative voltage. The relationship between the L voltages of the transfer clocks φV1 to φV4 and the substrate potentials Vsub1 and Vsub2 will be described below by the present inventor.

2-1. Regarding Transfer Clock and Substrate Potential In the TDI-type linear image sensor according to the present embodiment, a negative voltage sufficiently lower than the substrate potential Vsub1 of the first semiconductor substrate 1 is set to the L voltage of each of the transfer clocks φV1 to φV4. As in the case of the MPP operation of the CCD image sensor, the pixel dark current can be reduced by pinning the lower part of the transfer electrode to the inverted state. As shown in FIG. 4, the first transfer clock φV1 is input from the input pin 24a to the transfer electrode 20a, and the third transfer clock φV3 is input from the input pin 24c to the transfer electrode 20c. At this time, no transistor or the like is interposed between the input pins 24a and 24c and the transfer electrodes 20a and 20c.

  On the other hand, as shown in FIG. 5, the second transfer clock φV2 and the fourth transfer clock φV4 are transmitted from the respective input pins 27b and 27d via the line selection circuit 26 to any of the remaining transfer electrodes 20b and 20d. Is input (see FIG. 14). At this time, a transmission gate 38 is interposed between the input pins 27b and 27d and the transfer electrodes 20b and 20d, as shown in FIG. The inventor of the present application has found that the transmission gate 38 is a factor that prevents the L voltage of the second transfer clock φV2 and the fourth transfer clock φV4 from becoming negative. Hereinafter, this point will be described with reference to FIG.

  FIG. 8 shows the structure of the transmission gate 38 used in the line selection circuit 28. FIG. 3A is a circuit diagram of the transmission gate 38, and FIG. 3B is a diagram showing a cross-sectional structure of an element of the transmission gate 38.

  In FIG. 8A, the transmission gate 38 includes an NMOS transistor 36 and a PMOS transistor 37 connected to each other at two connection points A and B. Clocks φ and / φ having phases opposite to each other are input to the gates of the transistors 36 and 37, respectively (superscript bars in the drawing are denoted by “/”).

  8B, the NMOS transistor 36 includes a gate electrode 46 formed on a p-type silicon substrate 44 with a gate oxide film 45 interposed therebetween, and a source and a drain including an n-type impurity region 47. . The PMOS transistor 37 includes a gate electrode 51 formed on an N well 49 formed on a p-type silicon substrate 44 with a gate oxide film 50 interposed therebetween, and a source and a drain including a p-type impurity region 52. Is done. The substrate potential Vsub is set on the p-type silicon substrate 44 by external connection such as grounding. The well potential Vwell of the N well 49 is set by a power supply voltage of an external power supply or the like.

  At the transmission gate 38 in the line selection circuit 28 (FIG. 6), a clock voltage according to the second transfer clock φV2 or the fourth transfer clock φV4 is applied to the connection point A or the connection point B in FIG. 8A. When the applied clock voltage is lower than the substrate potential Vsub, a bias is applied in the forward direction to the PN junction formed by the p-type silicon substrate 44 and the n-type impurity region 47. Therefore, it is assumed that an excessive current flows and hinders the normal operation of the line selection circuit 28.

  When the applied clock voltage is higher than the well potential Vwell, a bias is applied in the forward direction to the PN junction formed by the N well 49 and the p-type impurity region 52, and an excessive current may flow. It is assumed as well. Therefore, for the transmission gate 38, the transfer clock voltage applied to the connection point A or the connection point B in FIG. 8A needs to be equal to or higher than the substrate potential Vsub (and equal to or lower than the well potential Vwell).

  In a conventional (for example, Patent Document 1) TDI-type linear image sensor, a line selection circuit and pixels are formed on the same semiconductor substrate, and a common substrate potential (0 V) is used. For this reason, the conventional TDI type linear image sensor has a problem that when the L voltage of the transfer clock is set to a negative voltage, an excessive current flows and the circuit does not operate normally. Further, in order to reduce the pixel dark current as in the MPP operation of the CCD image sensor, the L voltage of the transfer clock is set to be lower than the substrate potential (Vsub1) of the pixel so as to pin the electrode under the pixel in an inverted state. It must be a sufficiently low negative voltage.

  In order to solve the above problems, the inventor of the present application has made intensive studies and formed the first semiconductor substrate 1 and the second semiconductor substrate 2 separately as shown in FIG. , Vsub2 are independent. According to this configuration, for example, the substrate potential Vsub2 of the second semiconductor substrate 2 can be set lower than the substrate potential Vsub1 of the first semiconductor substrate 1 such as the GND potential. All the L voltages of the transfer clocks φV1 to φV4 can be set to negative voltages. That is, while maintaining the substrate potential Vsub1 higher than the L voltage in the first semiconductor substrate 1, the substrate potential Vsub2 with respect to the second semiconductor substrate 2 is increased without lowering the L level without disturbing the normal operation of the transmission gate 38. It can be set to a value lower than the voltage. As a result, it is possible to reduce the dark output of the pixel of the TDI-type linear image sensor and to expand the dynamic range.

  Hereinafter, the operation of the TDI-type linear image sensor according to the present embodiment will be described in detail.

2-2. Vertical Transfer Operation First, a vertical transfer operation (TDI operation) in the TDI-type linear image sensor according to the present embodiment will be described with reference to FIGS.

  9 to 11 are schematic diagrams for explaining potential changes of the CCD transfer channel caused by a clock supplied to the TDI-type linear image sensor according to the present embodiment. FIGS. 9A to 9D are timing charts of the vertical transfer clock supplied to the four-phase drive CCD. FIG. 10A shows a cross-sectional structure of the four-phase driven CCD along the charge transfer direction. FIGS. 10B to 10F show changes in potential of the transfer channel in the same section in a time series. FIGS. 11 (a) to 11 (f) are the same as FIGS. 10 (a) to 10 (f) when the clock supplied to the transfer electrode is different from FIGS. 10 (a) to 10 (f). FIG.

  In the present embodiment, the first to fourth transfer clocks φV1 to φV4 as shown in FIGS. 9A to 9D are used as drive clocks of the four-phase drive CCD, and the transfer electrodes of the pixel 17 (FIG. 4) are used. To supply.

  Here, FIGS. 10B to 10F show first, second, third, and fourth transfer clocks for four transfer electrodes 20a, 20b, 20c, and 20d (FIG. 10A), respectively. The potential distribution of the transfer channel at times t1 to t5 when φV1, φV2, φV3, and φV4 are supplied is shown. FIGS. 11B to 11F show the second transfer clock φV2 and the fourth transfer clock φV1 to φV4 in the first to fourth transfer clocks φV1 to φV4 supplied to the four transfer electrodes 20a, 20b, 20c, and 20d. 5 shows the potential distribution of the transfer channel at times t1 to t5 when the transfer clock φV4 is replaced.

  As shown in FIGS. 10A to 10F and FIGS. 11A to 11F, the voltage “H” of the transfer clock φV is applied among the four transfer electrodes 20a, 20b, 20c, and 20d. A potential well 43 is formed below the gate.

  In the case of FIG. 10, the signal charges 42 generated by the light incidence move to the right in the drawing as the potential well 43 moves rightward in the drawing (corresponding to the −Y direction) by the transfer operation of the CCD. Will be transferred. At this time, the TDI operation can be realized by matching the moving speed of the subject image with the CCD transfer speed, and the charge transfer and the charge integration are performed simultaneously.

  In the case of FIG. 11, the signal charge 42 is transferred to the left (corresponding to the + Y direction) of the drawing as the potential well 43 moves to the left of the drawing by the transfer operation of the CCD. As described above, in the four-phase drive CCD, the direction of vertical transfer can be reversed by exchanging, for example, φV2 and φV4 among the transfer clocks supplied to the four transfer electrodes 20a, 20b, 20c, and 20d.

  In the vertical transfer operation as described above, the depth of the potential well 43 is defined by the voltage amplitude between “H” and “L” of each of the transfer clocks φV1 to φV4. In the present embodiment, as shown in FIG. 9, the L voltage of each of the transfer clocks φV1 to φV4 can be set lower than “0 (GND potential)”, so that the potential well 43 is deepened to expand the dynamic range. Can be.

2-3. Next, the operation of the line selection circuit 28 in the TDI stage number switching circuit 13 for switching the direction of vertical transfer will be described with reference to FIG.

  In the unit cell circuit 25 of the line selection circuit 28 shown in FIG. 6, one end of two transmission gates 38a and 38b is connected to one metal wiring 16b connected to one transfer electrode 20b. I have. The other end of one transmission gate 38a is connected to an input pin 27b (= φV2) via a metal wiring 26b, and the other end of the other transmission gate 38b is connected to an input pin 27d (= φV4) via a metal wiring 26d. It is connected to the.

  The line output 29 of the vertical shift register 33 (hereinafter, referred to as shift register output) is input to the gate of the NMOS transistor 36a of the transmission gate 38a, and at the same time, the line output 29 is transmitted via the inverter 39a to the PMOS of the transmission gate 38a. The signal is input to the gate of the transistor 37a. Therefore, when the shift register output 29 is "H", the transmission gate 38a is turned on, the input pin 27b is connected (conducted) to the metal wiring 16b, and the second transfer clock φV2 is supplied to the transfer electrode 20b.

  The shift register output 29 is input to the gate of the PMOS transistor 37b of the transmission gate 38b, and at the same time, is input to the gate of the NMOS transistor 36b of the transmission gate 38b via the inverter 39a. Therefore, when the shift register output 29 is "L", the transmission gate 38b is turned ON, the input pin 27d is connected to the metal wiring 16b, and the fourth transfer clock φV4 is supplied to the transfer electrode 20b.

  On the other hand, one end of two transmission gates 38c and 38d is connected to one metal wiring 16d connected to one transfer electrode 20d. The other end of one transmission gate 38c is connected to an input pin 27d via a metal wiring 26d, and the other end of the other transmission gate 38d is connected to the input pin 27b via a metal wiring 26b.

  The shift register output 29 is input to the gate of the NMOS transistor 36c of the transmission gate 38c, and at the same time, is input to the gate of the PMOS transistor 37c of the transmission gate 38c via the inverter 39c. Therefore, when the shift register output 29 is "H", the transmission gate 38c is turned on, the input pin 27D is connected to the metal wiring 16d, and the fourth transfer clock φV4 is supplied to the transfer electrode 20d.

  The shift register output 29 is input to the gate of the PMOS transistor 37d of the transmission gate 38d, and at the same time, is input to the gate of the NMOS transistor 36d of the transmission gate 38d via the inverter 39c. Therefore, when the shift register output 29 is "L", the transmission gate 38d is turned on, the input pin 27b is connected to the metal wiring 16d, and the second transfer clock φV2 is supplied to the transfer electrode 20d.

  That is, the unit cell circuit 25 of the line selection circuit 28 switches the two transfer clocks φV2 and φV4 supplied to the two transfer electrodes 20b and 20d according to whether the shift register output 29 is “H” or “L”. Works.

2-4. Operation of Vertical Shift Register Next, the operation of the vertical shift register 33 related to the above-described shift register output 29 will be described with reference to FIG.

  In the unit cell circuit 30 of the vertical shift register 33 shown in FIG. 7, when the clock (= φT1) supplied to the input pin 32a is set to “H”, the transmission gate 40a is turned on. As a result, the output of the preceding unit cell circuit 30 is input to the inverter 41a, and the inverter 41a performs an inverted output. When the unit cell circuit 30 is in the first stage, the clock (= φTS) supplied to the input pin 32c instead of the output of the previous stage is input to the inverter 41a, and the output of the inverter 41a is an inverted output of the input clock φTS. .

  Next, assume that the input clock φT1 is set to “L”. The transmission gate 40a is turned off, and the input and output of the inverter 41a are held as they are.

  Next, when the clock (= φT2) supplied to the input pin 32b is set to “H”, the transmission gate 40b is turned on. The held output of the inverter 41a is input to the inverter 41b, and is inverted and output by the inverter 41b. The output signal thus inverted twice is transmitted as the shift register output 29 to the unit cell circuit 25 (FIG. 6) of the line selection circuit 28.

  Next, when the input clock φT2 is set to “L”, the transmission gate 40b is turned off. Thus, the input and output of the inverter 41b are maintained as they are. Further, when the input clock φT1 is set to “H”, the above series of operations is repeated.

  As described above, in the vertical shift register 33, the clock pulse input as the input clock φTS is sequentially transmitted to the next stage in the unit cell circuits 30 of a plurality of stages one by one and output as the line output 29.

2-5. Next, a setting method and a setting operation of the number of TDI stages in the TDI-type linear image sensor according to the present embodiment will be described with reference to specific examples. As an example, a case where the number of TDI stages is set to 5 in the TDI linear image sensor of 8 vertical pixels × 10 horizontal pixels shown in FIG. 4 will be described with reference to FIGS.

  12 and 13 are diagrams for explaining a method of setting the number of TDI stages by the TDI stage number switching circuit. FIGS. 12A to 12C are examples of timing charts of input clocks φTS, φT1, and φT2 supplied to the TDI stage number switching circuit 13. FIGS. 13A to 13F are diagrams for explaining the operation of the TDI stage number switching circuit 13.

  First, the setting of the number of TDI stages is performed before imaging (stage number setting mode). Specifically, the number of TDI stages is set by operating the vertical shift register 33 of the TDI stage number switching circuit 13. FIG. 12 shows an example of a clock for driving the vertical shift register 33 when the number of TDI stages is set to five. FIG. 13 shows how the shift register output changes at times t = 0, 1, 2, 5, 6, and 8 when the driving clock shown in FIG. 12 is supplied.

  The vertical shift register 33 is driven by supplying clock pulses of three input clocks φTS, φT1, and φT2 as illustrated in FIGS. 12A to 12C. A period 0 shown in FIG. 12 is a period for initializing the vertical shift register 33. At this time, while the input clock φTS in FIG. 12A is kept “L”, the input clock φT1 in FIG. 12B and the input clock φT2 in FIG. As a result, at time t = 0, the shift register outputs 29 of all lines (all unit cell circuits 30) are reset to “L” as shown in FIG.

  Next, in the periods 1 to 5, the input clock φT1 in FIG. 12B and the input clock φT2 in FIG. 12C are alternately set while the input clock φTS in FIG. The level is set to “H” to operate the vertical shift register 33. As a result, at times t = 1 to 5, the signal from the preceding unit cell circuit 30 is transmitted to the next unit cell circuit 30 as shown in FIGS. The shift register output 29 shifts down by one stage.

  Next, in periods 6 to 8, the input clock φT1 in FIG. 12B and the input clock φT2 in FIG. 12C are alternately set while the input clock φTS in FIG. The level is set to “H” to operate the vertical shift register 33.

  As a result, at times t = 6 to 8, as shown in FIGS. 13E and 13F, the “H” outputs of five lines are grouped and shifted downward by one stage. Thereafter, when the clock pulses of the three input clocks φT1, φT2, and φTS are stopped at t = 8, the output of the shift register 29 of each line becomes “H” for the five lines from the lower side in FIG. The output is held at "L".

  The series of operations described above completes the TDI stage number setting mode, and then shifts to the following TDI imaging mode.

2-5. Operation in TDI Imaging Mode Next, the operation in the TDI imaging mode will be described with reference to FIG.

  FIG. 14 is a diagram showing the relationship between the voltage of each part of the vertical scanning circuit and the transfer direction of the vertical transfer electrode when the number of TDI stages is set to five. FIG. 14 shows a part of the circuit configuration of the TDI-type linear image sensor according to the present embodiment shown in FIG.

  As described above, the clock pulses illustrated in FIGS. 12A to 12C are supplied to the vertical shift register 33 to set the number of TDI stages to five. Then, as shown in FIG. 14, the shift register output 29 of each line is set to “H” from the first stage to the fifth stage from the lower side in the vertical direction (−Y direction), and from the sixth stage to the eighth stage. "L" is set by then.

  At this time, the second transfer clock φV2 is supplied to the first to fifth metal wires 15b by the operation of the above-described line selection circuit 28, and the first to fifth metal wires 15d are supplied to the first to fifth metal wires 15d. Is supplied with a fourth transfer clock φV4. The fourth transfer clock φV4 is supplied to the metal wirings 15b of the sixth to eighth stages, and the second transfer clock φV2 clock is supplied to the metal wiring 15d of the sixth to eighth stages. You.

  Here, the first to fourth transfer clocks φV1 to φV4 shown in FIGS. 9A to 9D are supplied while the vertical shift register 33 is stopped. Then, in the TDI type linear image sensor shown in FIG. 14, the vertical transfer is in the −Y direction (forward direction) from the first stage to the fifth stage from below, and the vertical transfer is from the sixth stage to the eighth stage from below. Is in the + Y direction (reverse direction). At this time, by making the transfer speed of the vertical CCD (that is, the operation speed of the vertical transfer operation) coincide with the moving speed of the subject image, it is possible to perform time-delay integration of pixel signals of five stages from the bottom in FIG.

  In the above example, the case where TDI imaging is performed with the number of TDI stages set to five is shown, but the present invention is not particularly limited to this. Only by changing the clock pulse φTS supplied to the vertical shift register 33, the number of TDI stages can be set to an arbitrary number.

  That is, in the shift register driving input clocks φTS, φT1, and φT2 as shown in FIGS. 12A to 12C, a period 1 to a period M (M is a natural number equal to or less than the number of transfer stages of the vertical CCD) is illustrated. By setting the input φTS of 12 (a) to “H”, the number of TDI stages can be set to M stages.

3. Conclusion As described above, the TDI-type linear image sensor according to the present embodiment includes the pixel array 3, the plurality of selection lines 15, the line selection circuit 28, and the horizontal CCD 5. In the pixel array 3, pixels 17 having transfer electrodes 20a to 20d for performing photoelectric conversion, integrating the generated charges with a time delay, and vertically transferring the charges are two-dimensionally arranged. The plurality of selection lines 15 are connected to each of the transfer electrodes 20a to 20d, and supply multi-phase transfer clocks φV1 to φV4. The line selection circuit 28 selects transfer clocks φV2 and φV4 to be supplied to predetermined selection lines 15b and 15d among the plurality of selection lines 15 among the multi-phase transfer clocks φV1 to φV4. The horizontal CCD 5 horizontally transfers the charge delayed and integrated. The pixel array 3, the plurality of selection lines 15, and the horizontal CCD 5 are formed on the first semiconductor substrate 1. The line selection circuit 28 is formed on the second semiconductor substrate 2 electrically connected to the first semiconductor substrate 1. The substrate potential Vsub1 of the first semiconductor substrate 1 and the substrate potential Vsub2 of the second semiconductor substrate 2 are electrically independent.

  According to the TDI-type linear image sensor described above, it is possible to make the L voltages of the transfer clocks φV1 to φV4 negative while operating the line selection circuit 28 normally. As a result, the voltage amplitudes of the transfer clocks φV1 to φV4 increase and the depth of the potential well 43 formed in the transfer channel increases, so that the maximum transfer charge amount of the vertical CCD increases and the dynamic range can be expanded. .

  In the present embodiment, the substrate potential Vsub2 of the second semiconductor substrate 2 is lower than the substrate potential Vsub1 of the first semiconductor substrate 1. The TDI-type linear image sensor according to the present embodiment includes a setting terminal of the substrate potential Vsub1 of the first semiconductor substrate 1 and a substrate of the second semiconductor substrate 2 so that the substrate potentials Vsub1 and Vsub2 can be set. A setting terminal for the potential Vsub2 (see FIG. 1).

  Further, in the present embodiment, the transfer clocks φV1 to φV4 have a high level “H” higher than the substrate potential Vsub1 such as a GND potential and a low level “L” lower than the same potential Vsub1 (see FIG. 9). . The substrate potential Vsub2 of the second semiconductor substrate 2 is lower than or equal to the low level “L” of the transfer clocks φV1 to φV4.

  For example, when the L voltage of the transfer clocks φV1 to φV4 is set to a sufficiently low negative voltage so that the lower portions of the transfer electrodes 22a to 22d pinch in an inverted state, the substrate potential Vsub2 of the second semiconductor substrate 2 becomes The potential is set to be equal to or lower than the L voltage. Thus, the generation of thermally excited electrons at the oxide film interface is suppressed by the transfer clocks φV1 to φV4, and the pixel dark current is reduced.

  Note that the L voltage of the transfer clocks φV1 to φV4 does not have to be a sufficiently low negative voltage as described above. Also in this case, the substrate potential Vsub2 of the second semiconductor substrate 2 is appropriately set to be equal to or lower than the L voltage of the transfer clocks φV1 to φV4. Thereby, a dynamic range can be secured according to the voltage amplitude of the transfer clocks φV1 to φV4.

  Further, the TDI-type linear image sensor according to the present embodiment further includes a vertical shift register 33. The vertical shift register 33 outputs a shift register output 29 for setting a transfer direction in which charges are transferred in the pixel array 3 to the line selection circuit 28. The line selection circuit 28 replaces one of the multi-phase transfer clocks φV1 to φV4 (FIG. 10) based on the shift register output 29 to generate an opposite-phase transfer clock (FIG. 11) (see FIG. 14).

  With the above configuration, it is possible to switch the charge transfer direction from the arbitrary position of the pixel array 3 to the forward direction and the reverse direction. Thus, while having the function of arbitrarily setting the number of TDI stages, it is possible to expand the dynamic range and to reduce the dark output when the pixel is dark. The line selection circuit 28 may be used not only for switching the number of TDI stages but also for switching the transfer direction of signal charges (see Patent Document 2).

  Further, the driving method of the TDI-type linear image sensor according to the present embodiment includes a step of setting the substrate potential Vsub2 of the second semiconductor substrate 2 lower than the substrate potential Vsub1 of the first semiconductor substrate 1. The method includes a step in which the line selection circuit 28 outputs the second and fourth transfer clocks φV2 and φV4 as signals based on the predetermined high potential (H) and low potential (L). The low potential (L) of the signal output by the line selection circuit 28 is lower than the substrate potential Vsub1 of the first semiconductor substrate 1.

  According to the driving method of the TDI-type linear image sensor described above, the TDI-type linear image sensor can be operated normally by setting the L voltage of the transfer clocks φV1 to φV4 to a negative voltage, and the dynamic range can be expanded and the pixel dark output can be reduced.

Embodiment 2 FIG.
In the second embodiment, the substrate potentials Vsub1 and Vsub2 of the first and second semiconductor substrates 1 and 2 are set in the TDI linear image sensor as in the first embodiment, and the L voltage of the transfer clock φV is set to a negative voltage. . In the second embodiment, a TDI-type linear image sensor that uses a voltage amplitude of an external input clock φT which is enlarged will be described. The TDI-type linear image sensor according to the second embodiment will be described with reference to FIGS.

  FIG. 15 is a block diagram illustrating a configuration of a TDI-type linear image sensor according to Embodiment 2 of the present invention. FIG. 16 is a circuit diagram showing a configuration of the unit cell circuit 60 of the clock driver circuit 14 provided before the TDI stage number switching circuit 13 in the TDI type linear image sensor shown in FIG.

  The TDI-type linear image sensor according to the second embodiment has a configuration similar to that of the TDI-type linear image sensor according to the first embodiment shown in FIG. A clock driver circuit 14 is further provided in a preceding stage.

  The clock driver circuit 14 is a circuit that converts an external input clock φT so as to increase the respective voltage amplitudes and supplies the converted clock to the TDI stage number switching circuit 13. In the present embodiment, the clock driver circuit 14 is configured by providing one (ie, three) unit cell circuits 60 shown in FIG. 15 for each of the input clocks φT1, φT2, and φTS.

  As shown in FIG. 16, in the unit cell circuit 60 of the clock driver circuit 14, three inverters 55, 56, and 57 are connected in series, and for example, an inverted clock / φT is output with respect to the input clock φT. The power supply voltage Vdd1 is supplied to the first-stage inverter 55, and the power supply voltage Vdd2 higher than the power supply voltage Vdd1 of the first-stage inverter 55 is supplied to the second and subsequent inverters 56 to 58 (Vdd1 <Vdd2). Each of the power supply voltages Vdd1 and Vdd2 is set to a desired level by using an external power supply. The operation of the clock driver circuit 14 will be described later.

  According to the TDI-type linear image sensor according to the second embodiment configured as described above, power consumption when the L voltage of the transfer clock φV is set to a negative voltage is reduced. Hereinafter, this point will be described with reference to the drawings.

  For example, in the TDI linear image sensor shown in FIG. 1, in the unit cell circuit 30 (FIG. 7) of the vertical shift register 33, two inverters 41a and 41b are used for each unit cell circuit. In the unit cell circuit 25 of the line selection circuit 28 shown in FIG. 6, two inverters 39a and 39b are used for each unit cell circuit. In such an inverter circuit, the power supply voltage Vdd on the high level is set equal to the well potential Vwell of the second semiconductor substrate 2 (FIG. 1), and the power supply voltage Vss on the low level is set equal to the substrate potential Vsub2. You.

  In the above case, in order to operate the inverter circuit normally, the power supply voltage Vdd needs to be higher than the H voltage (high level voltage) of the transfer clock φV, and the substrate potential Vsub2 needs to be lower than the L voltage of the transfer clock φV. .

  Here, the clock voltages of the input clocks φT1, φT2, and φTS generally applied from the outside are often so-called TTL levels or the like, and it is assumed that the voltage amplitude is smaller than that of the transfer clock φV. In this case, in the unit cell circuit 30 shown in FIG. 7, the voltage applied to the input gates of the inverters 41a and 41b becomes a voltage near the middle between Vdd and Vss, and a large through current flows, which increases power consumption. Conceivable.

  On the other hand, in the TDI linear image sensor according to the present embodiment, the through current as described above is suppressed by using the clock driver circuit 14. Hereinafter, the operation of the TDI-type linear image sensor according to the present embodiment will be described.

  In the TDI-type linear image sensor according to the second embodiment of the present invention shown in FIG. 15, the input clocks φT1, φT2, and φTS are input to the clock driver circuit. The clock driver circuit 14 boosts each of the input clocks φT1, φT2, and φTS, and the output signal of the clock driver circuit 14 is input to the shift register 33.

  In the unit cell circuit 60 of the clock driver circuit 14 shown in FIG. 16, when the input clock φT is “L”, the output of the first-stage inverter 55 becomes “H”, and the potential at the point B becomes “Vdd1”. Since the input of the second-stage inverter 56 is “H”, its output becomes “L” and the potential at the point D becomes “Vss”. At this time, since the input of the inverter 58 in the opposite direction is "L", its output becomes "H" and the potential at the point C is raised to "Vdd2". At this time, the NMOS transistor 59 provided between the points B and C functions as a switch for cutting off a current generated by a potential difference between the points B and C. Since the input of the third-stage inverter 57 is “L”, its output becomes “H” and the potential at the point F becomes “Vdd2”.

  When the input clock φT is “H”, the output of the first-stage inverter 55 becomes “L”, and the potential at the point B becomes “Vss”. Since the input of the second-stage inverter 56 is "L", its output becomes "H" and the potential at the point D becomes "Vdd2". At this time, since the input of the inverter 58 in the opposite direction is "H", its output becomes "L" and the potential at the point C becomes "Vss". Since the input of the third-stage inverter 57 is "H", its output becomes "L" and the potential at the point F becomes "Vss".

  In the above operation, the input voltage of the second and subsequent inverters 56 to 58 is “Vdd2” or “Vss” and is equal to the well potential Vwell or the substrate potential Vsub2. It can be prevented from flowing.

  Further, by setting the power supply voltage Vdd1 of the first-stage inverter 55 to be equal to the H voltage of the input clock φT, a through current does not flow through the first-stage inverter 55 when the input clock φT is “H”. . When the input clock φT is “L” and the L voltage is 0 V, for example, if the low-level power supply voltage Vsub2 is set to a negative voltage in order to make the L voltage of the transfer clock φV negative, the first-stage inverter 55 It is assumed that a through-current flows through the. At this time, by minimizing the size of the transistors constituting the first-stage inverter 55 to a necessary minimum, the amount of through current can be reduced.

  According to the above configuration, when the L voltage of the transfer clock φV is set to a negative voltage, the power consumption can be reduced even when the clock amplitude of the external input clock φT for setting the number of TDI stages is small. is there.

  As described above, the TDI linear image sensor according to the present embodiment further includes the clock driver circuit 14. The clock driver circuit 14 changes the input clock φT, which is a selection signal input from the outside, to a high potential “H” corresponding to the high-level power supply voltage Vdd2 and a low potential “L” corresponding to the low-level power supply voltage Vss. To a signal based on ". The line selection circuit 28 in the TDI stage number switching circuit 13 operates based on the signal converted by the clock driver circuit 14.

  According to the TDI-type linear image sensor described above, the voltage amplitude of the transfer clock φV output from the line selection circuit 22 can be larger than the voltage amplitude of the input clock φT as an external selection signal. Further, the through current at this time can be suppressed.

Embodiment 3 FIG.
In the third embodiment, the substrate potentials Vsub1 and Vsub2 of the first and second semiconductor substrates 1 and 2 are set in the TDI linear image sensor as in the first and second embodiments, and the L voltage of the transfer clock φV is set to a negative voltage. To In the second embodiment, the power consumption in the clock driver circuit is reduced by dividing the high-level power supply voltage into two. In the third embodiment, a TDI-type linear image sensor in which a low-level power supply voltage is further divided into two in a clock driver circuit will be described with reference to FIGS.

  FIG. 17 is a block diagram showing a configuration of a TDI-type linear image sensor according to Embodiment 3 of the present invention. FIG. 18 is a circuit diagram showing a configuration of a unit cell circuit 60A of a clock driver circuit 14A provided in a stage preceding the TDI stage number switching circuit 13 in the TDI type linear image sensor shown in FIG.

  The TDI-type linear image sensor according to the third embodiment of the present invention has the same configuration as the TDI-type linear image sensor according to the second embodiment shown in FIG. 15, and has two power supply voltages Vss1 and Vss2 on the low level side. Is provided.

  As shown in FIG. 18, in the unit cell circuit 60A of the clock driver circuit 14A according to the present embodiment, the voltage Vss1 having a smaller absolute value among the low-level power supply voltages Vss1 and Vss2 is supplied to the first-stage inverter 55. , And the other voltage Vss1 is applied to the second and subsequent inverters 56 to 58. The setting of the low-level power supply voltages Vss1 and Vss2 is performed by connecting the low-level side of each inverter to an external power supply or the like. In addition, Vss1 may be 0 V. In this case, the first-stage inverter 55 is grounded.

  Further, in the present embodiment, the inverter and the PMOS transistor in the clock driver circuit 14A are constituted by CMOS transistors having a triple well structure.

  According to the TDI-type linear image sensor according to the third embodiment configured as described above, power consumption when the L voltage of the transfer clock φV is set to a negative voltage is further reduced. Hereinafter, this point will be described with reference to the drawings.

  In the TDI-type linear image sensor shown in FIG. 15, when the substrate potential Vsub2 is set to a negative potential when the input clock φT is 0 V, it is assumed that a through current flows to the first-stage inverter 55. On the other hand, in the TDI-type linear image sensor according to the present embodiment shown in FIG. 18, the through-current flows even when the input clock φT is 0 V by using the two power supply voltages Vss1 and Vss2 on the low level side. Not to be.

  In the unit cell circuit of FIG. 18, when the input clock φT is “H”, the output of the first-stage inverter 55 becomes “L”, and the potential at the point B becomes “Vss1”. Since the input of the second-stage inverter 56 is "L", its output becomes "H" and the potential at the point D becomes "Vdd2". At this time, since the input of the inverter 58 in the opposite direction is "H", its output becomes "L" and the potential at the point C is reduced to "Vss2". At this time, the PMOS transistor 61 provided between the points B and C functions as a switch for cutting off a current generated by a potential difference between the points B and C. Since the input of the third-stage inverter 57 is “H”, its output becomes “L” and the potential at the point F becomes “Vss2”.

  The operation when the input clock φT is “L” in the unit cell circuit 60A of FIG. 18 is the same as that of the second embodiment (FIG. 16), and therefore the description is omitted.

  In the above operation, the input voltages of the second and subsequent inverters 56 to 58 are “Vdd2” or “Vss2”. By setting the power supply voltages Vdd2 and Vss2 equal to the well potential Vwell and the substrate potential Vsub2, it is possible to prevent a through current from flowing in these inverters 56 to 58.

  Further, by setting the high-level power supply voltage Vdd1 of the first-stage inverter 55 equal to the H voltage of the input clock φT and setting the low-level power supply voltage Vss1 equal to the L voltage of the input clock φT, the first-stage inverter 55 Also at 55, it is possible to prevent a through current from flowing.

  In the TDI-type linear image sensor according to this embodiment as described above, the substrate potential of the CMOS circuit in the circuit formed on the common semiconductor substrate 2 needs to be divided into two, "Vss1" and "Vss2". . This can be realized by employing a triple well CMOS circuit.

  According to the above configuration, when the L voltage of the transfer clock φV is set to a negative voltage, power consumption can be reduced more effectively when the clock amplitude of the external input clock φT for setting the number of TDI stages is small. is there.

  As described above, in the TDI-type linear image sensor according to the present embodiment, the clock driver circuit 14A, the line selection circuit 22, and the like are configured on the second semiconductor substrate 2 as CMOS circuits including transistors having a triple well structure. . As a result, the VDD voltage and the VSS voltage of the clock driver circuit 14A and the line selection circuit 22 can be set to different potentials, and the power consumption of the circuit on the second semiconductor substrate 2 can be reduced.

  The method of driving the TDI-type linear image sensor according to the present embodiment includes the steps of: setting a potential “Vdd1” equal to the H voltage of the input clock φT as a selection signal in the clock driver circuit 14A; Setting a potential “Vss1” equal to the voltage. Thereby, a through current that can flow through the clock driver circuit 14A is reduced, and power consumption can be reduced.

  As described above, specific embodiments and modified examples of the present invention have been described. However, the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the present invention. it can. For example, an embodiment of the present invention may be appropriately combined with the contents of the individual embodiments described above.

  1 1st semiconductor substrate, 2nd semiconductor substrate, 3 pixel array, 4 pads, 5 horizontal CCD, 6 output amplifier, 7 CMOS circuit, 8 bumps, 9 packages, 10 pads (on package), 11 wire bonds, 12 lead pin, 13 TDI stage number switching circuit, 14 clock driver circuit, 15 selection line, 16 selection line, 17 pixel, 18 charge discharging drain, 19 charge storage section, 20 transfer gate, 21 isolation region, 22 contact, 23 metal wiring, 24 pads, 25 unit cell circuits, 26 metal wirings, 27 pads, 28 line selection circuits, 29 line outputs, 30 unit cell circuits, 31 metal wirings, 32 pads, 33 vertical shift registers, 34 bump pads, 35 bump pads , 36 NMOS, 37 PMOS, 38 transformer Mission gate, 39 inverter, 40 NMOS, 41 inverter, 42 charge, 43 potential well, 44 p-type Si substrate, 45 gate oxide film, 46 gate, 47 n-type impurity region, 48 channel, 49 N well, 50 gate oxide film , 51 gate, 52 p-type impurity region, 53 channel, 54 field oxide film, 55 inverter, 56 inverter, 57 inverter, 58 inverter, 59 NMOS, 60 unit cell circuit, 61 PMOS

Claims (6)

A pixel group in which pixels having a transfer electrode for performing photoelectric conversion, integrating the generated charges with a time delay, and vertically transferring the pixels are two-dimensionally arranged;
A plurality of selection lines connected to each of the transfer electrodes and supplying a multi-phase transfer clock;
A line selection circuit that selects a transfer clock to be supplied to a predetermined one of the plurality of selection lines in the multi-phase transfer clock;
A horizontal transfer unit for horizontally transferring the charge delayed and integrated,
The pixel group, the plurality of selection lines, and the horizontal transfer unit are formed on a first semiconductor substrate;
The line selection circuit is formed on a second semiconductor substrate electrically connected to the first semiconductor substrate,
And the substrate potential of said first substrate potential of the semiconductor substrate and the second semiconductor substrate, Ri electrically independent der,
A substrate potential of the second semiconductor substrate is a negative voltage lower than a ground potential of the substrate potential of the first semiconductor substrate;
The multi-phase transfer clock has a high level higher than the substrate potential of the first semiconductor substrate, and a low level that is a negative voltage lower than the substrate potential of the first semiconductor substrate,
The TDI-type linear image sensor , wherein a substrate potential of the second semiconductor substrate is lower than a low-level negative voltage of the multi-phase transfer clock . The pixel group further includes a vertical shift register that outputs an output signal for setting a transfer direction in which the charge is transferred to the line selection circuit,
2. The TDI-type linear image sensor according to claim 1, wherein the line selection circuit replaces one of the multi-phase transfer clocks and generates a reverse-phase transfer clock based on the output signal. 3. Wherein the second semiconductor substrate, TDI scheme linear image sensor according to claim 1 or 2 CMOS circuit is formed including a transistor of triple-well structure. A clock driver circuit that converts a selection signal input from outside into a signal based on predetermined high potential and low potential,
It said line selection circuit, TDI scheme linear image sensor according to any one of claims 1 to 3 operates based on the converted signal by the clock driver circuit. Setting the substrate potential of the second semiconductor substrate lower than the substrate potential of the first semiconductor substrate;
The line selection circuit includes a step of outputting a signal based on predetermined high potential and low potential,
The method of driving a TDI-type linear image sensor according to any one of claims 1 to 4 , wherein a low potential of the signal output by the line selection circuit is lower than a substrate potential of the first semiconductor substrate. Setting a potential equal to a high level of the selection signal in the clock driver circuit;
5. The method according to claim 4 , further comprising: setting a potential equal to a low level of the selection signal in the clock driver circuit.

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