JP2018133703A - Tdi-type linear image sensor and driving method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To use negative voltage for a transfer clock in a TDI-type image sensor.SOLUTION: The TDI-type linear image sensor comprises a pixel group (3), selection lines (15), a line selection circuit (28), and a horizontal transfer part (5). Pixels (17) with transfer electrodes are arranged two-dimensionally. Plural selection lines are connected to each transfer electrode to supply diplophase transfer clocks. The line selection circuit selects a transfer clock to supply to a predetermined selection line among the selection lines, among the diplophase transfer clocks. The horizontal transfer part horizontally transfers electric charges delayed and integrated temporally. The pixel group, the selection lines and the horizontal transfer part are formed on a first semiconductor substrate (1). The line selection circuit is formed on a second semiconductor substrate (2) electrically connected with the first semiconductor substrate. The substrate potential(Vsub1) of the first semiconductor substrate and the substrate potential (Vsub2) of the second semiconductor substrate are independent electrically.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a TDI linear image sensor used in the field of remote sensing and the like, and a driving method thereof.

  A large number of image sensors have been developed in which a large number of photodetectors are arranged in an array on a semiconductor substrate, and a signal charge readout circuit and an output amplifier are provided on the same substrate. In remote sensing, a linear image sensor with photodetectors arranged in a one-dimensional array is mounted on an artificial satellite, etc., and a two-dimensional image of the ground surface is taken by matching the direction perpendicular to the array with the direction of travel of the satellite. To do. In order to improve the image resolution, it is desirable to make the pixel pitch as small as possible. However, there is a problem that the incident light amount is reduced by the reduction in the area of the photodetector and the S / N ratio is deteriorated.

  As a clever means for improving the S / N ratio, a TDI (Time Delay and Integration) image sensor has been developed. The TDI method uses an FFT (full frame transfer) CCD (Charge Coupled Devices), which is a two-dimensional image sensor, to improve the S / N by synchronizing the charge transfer timing with the movement timing of the subject image. This is a readout method of a CCD image sensor. In the case of remote sensing, TDI operation can be realized by adjusting the charge transfer in the vertical direction to the moving speed of the satellite. When an M-stage TDI operation is performed with a vertical CCD, the accumulation time is effectively M times, so that the sensitivity is improved M times and the S / N is improved to √M times.

  Since the sensitivity of the TDI image sensor changes in proportion to the number of TDI stages, it is desirable that the number of TDI stages can be switched according to the luminance of the subject. As one of methods for realizing such a TDI stage number switching function, for example, a method described in Patent Document 1 has been proposed. Patent Document 1 is configured to switch the transfer direction of the vertical CCD between the forward direction and the reverse direction on the upstream side and the downstream side of a predetermined pixel row, and only the charge transferred in the forward direction is output as a signal. The At this time, it is possible to arbitrarily set the number of TDI stages by controlling the switching position in the transfer direction by a stage number switching circuit including a vertical shift register and a line selection circuit.

  In addition, a bidirectional TDI has been proposed that controls switching between the forward direction and the reverse direction of the transfer direction in a TDI operation depending on how the external clock is applied. Patent Document 2 discloses a back-illuminated image sensor that makes light incident from the back surface of the substrate as an example of such a bidirectional TDI. In the image sensor of Patent Document 2, the vertical transfer clock is given from the outside via a drive pad conversion substrate joined by metal bumps. In Patent Document 2, the transfer direction of the TDI operation based on the vertical transfer clock is controlled to reduce the time required for imaging the TDI operation.

  In a CCD image sensor, an MPP (Multi Pinned Phase) operation is known as a technique for reducing pixel dark output. In a CCD, a potential well is formed in a transfer channel according to a voltage applied to a transfer electrode, and charge transfer is performed by moving the potential well according to a clock operation. According to the MPP operation, by applying a sufficiently low negative voltage to the transfer electrode and pinning the bottom of the electrode in an inverted state, the generation of thermally excited electrons at the oxide film interface is suppressed and the pixel dark current is reduced.

Japanese Patent No. 4968227 Japanese Patent No. 5916659

  The inventor of the present application examined applying the MPP operation to a TDI type image sensor. In a TDI type image sensor, it is considered that it is advantageous in terms of noise reduction to use a negative voltage that enables MPP operation as a transfer clock.

  Further, the upper limit of the amount of charge that can be transferred in the TDI operation (that is, the saturation charge amount of the pixel) is determined by the area and depth of the potential well. The depth of the potential well corresponds to the voltage amplitude of the transfer clock, and the larger the voltage amplitude of the transfer clock, the more charge can be transferred. As the area of the potential well tends to shrink as the pixels become finer, it is necessary to deepen the potential well in order to ensure a dynamic range. Therefore, it is considered advantageous to increase the clock voltage amplitude by using a negative voltage for the transfer clock in the TDI image sensor in terms of expanding the dynamic range.

  As described above, in the inventor's examination as described above, in the conventional TDI type image sensors such as Patent Documents 1 and 2, a transfer clock is applied to the transfer electrode via a stage number switching circuit for controlling the TDI operation. Thus, the problem that a negative voltage cannot be used for the transfer clock has been clarified (details will be described later).

  An object of the present invention is to provide a TDI type linear image sensor that can use a negative voltage as a transfer clock applied to a transfer electrode in a TDI type image sensor having a function of controlling a TDI operation by an external clock.

  The TDI linear image sensor according to the present invention includes a pixel group, a plurality of selection lines, a line selection circuit, and a horizontal transfer unit. In the pixel group, pixels having transfer electrodes that perform photoelectric conversion and vertically transfer the generated charges by time delay integration are arranged two-dimensionally. The plurality of selection lines are connected to each of the transfer electrodes and supply a multiphase transfer clock. The line selection circuit selects a transfer clock to be supplied to a predetermined selection line among the plurality of selection lines in the multi-phase transfer clock. The horizontal transfer unit horizontally transfers the charge integrated with time delay. A pixel group, a plurality of selection lines, and a horizontal transfer unit are formed on the first semiconductor substrate. The line selection circuit is formed on a second semiconductor substrate that is electrically connected to the first semiconductor substrate. The substrate potential of the first semiconductor substrate and the substrate potential of the second semiconductor substrate are electrically independent.

  The TDI linear image sensor driving method according to the present invention includes a step of setting the substrate potential of the second semiconductor substrate to be lower than the substrate potential of the first semiconductor substrate, and the line selection circuit includes a predetermined high potential. And outputting a signal based on the low potential. The low potential of the signal output by the line selection circuit is lower than the substrate potential of the first semiconductor substrate.

  According to the TDI linear image sensor and the driving method thereof according to the present invention, a potential lower than the substrate potential of the first semiconductor substrate can be set as the substrate potential of the second semiconductor substrate. This makes it possible to use a negative voltage for the transfer clock applied to the transfer electrode in the TDI image sensor having a function of controlling the TDI operation by the external clock.

It is a block diagram which shows the structure of the TDI system linear image sensor which concerns on Embodiment 1 of this invention. 1 is a perspective view showing a schematic structure of a TDI linear image sensor according to Embodiment 1. FIG. 1 is a cross-sectional view showing a cross-sectional structure of a TDI linear image sensor according to Embodiment 1. FIG. FIG. 3 is a circuit diagram of a circuit formed on a first semiconductor substrate in the TDI linear image sensor according to the first embodiment. 4 is a block diagram illustrating a circuit configuration of a circuit formed on a second semiconductor substrate in the TDI linear image sensor according to Embodiment 1. FIG. 4 is a circuit diagram showing a configuration of a unit cell circuit of a line selection circuit in the TDI linear image sensor according to the first embodiment. FIG. FIG. 3 is a circuit diagram illustrating a configuration of a unit cell circuit of a shift register circuit in the TDI linear image sensor according to the first embodiment. FIG. 2 is a circuit diagram and a cross-sectional view showing the structure of a transmission gate used in the TDI linear image sensor according to the first embodiment. 4 is a timing chart of a vertical transfer clock supplied to a four-phase drive CCD for driving a TDI linear image sensor. It is the schematic diagram which represented the cross-sectional structure along the charge transfer direction of 4 phase drive CCD, and the potential change of the transfer channel in the same cross section in time series. It is the schematic diagram which represented the cross-sectional structure along the charge transfer direction of 4-phase drive CCD, and the change of the potential of the transfer channel in the same cross section in time series. 4 is an example of a clock timing chart provided to a TDI stage number switching circuit in the TDI linear image sensor according to the first embodiment. FIG. 5 is a diagram for explaining the operation of a TDI stage number switching circuit in the TDI linear image sensor according to the first embodiment. 5 is a diagram for explaining a TDI stage number switching circuit method in the TDI linear image sensor according to Embodiment 1. FIG. It is a block diagram which shows the structure of the TDI system linear image sensor which concerns on Embodiment 2 of this invention. FIG. 6 is a circuit diagram illustrating a configuration of a unit cell circuit of a clock driver circuit in a TDI linear image sensor according to a second embodiment. It is a block diagram which shows the structure of the TDI system linear image sensor which concerns on Embodiment 3 of this invention. FIG. 6 is a circuit diagram showing a configuration of a unit cell circuit of a clock driver circuit in a TDI linear image sensor according to a third embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, what attached | subjected the same code | symbol is the same or it corresponds, and this is common in the whole text of a specification.

Embodiment 1 FIG.
In the first embodiment, a TDI linear image sensor capable of switching control of the number of TDI stages is configured using first and second semiconductor substrates having substrate potentials independent of each other. The configuration of the TDI linear image sensor according to the first embodiment will be described below.

1. Configuration The overall configuration of the TDI linear image sensor according to the present embodiment will be described with reference to FIGS.

  FIG. 1 is a block diagram showing the configuration of a TDI linear image sensor according to Embodiment 1 of the present invention. As shown in FIG. 1, the TDI linear image sensor according to the present embodiment includes a first semiconductor substrate 1, a second semiconductor substrate 2, a pixel array 3, a horizontal CCD 5, an output amplifier 6, and bumps. 8, selection lines 15 and 16, and a TDI stage number switching circuit 13.

  The first semiconductor substrate 1 constitutes a CCD chip. The second semiconductor substrate 2 constitutes a CMOS chip. The pixel array 3 is an example of a pixel group in which pixels having transfer electrodes described later are two-dimensionally arranged in an array. Hereinafter, as shown in FIG. 1, the horizontal direction in which pixels are arranged in the pixel array 3 is referred to as “X direction”, and the vertical direction is referred to as “Y direction”. Further, the + Y direction may be referred to as the upper side, and the −Y direction may be referred to as the lower side.

  The horizontal CCD 5 is an example of a horizontal transfer unit that horizontally transfers charges that are time-delay integrated in the pixel array 3. The output amplifier 6 is provided for reading out the output of the horizontal CCD 5 to the outside. The TDI stage number switching circuit 13 is a circuit for executing a TDI stage number setting operation described later.

  In the TDI linear image sensor according to the present embodiment, the pixel array 3, the horizontal CCD 5 and the output amplifier 6 are provided on the first semiconductor substrate 1, and the TDI stage number switching circuit 13 is provided on the second semiconductor substrate 2. The first semiconductor substrate 1 and the second semiconductor substrate 2 are supplied with substrate potentials Vsub1 and Vsub2 electrically independently. As a result, the low level voltage of the multi-phase transfer clock φV applied to the TDI linear image sensor can be set to a negative voltage (hereinafter, the low levels of the various clocks φV and φT are denoted as “L” and the high level is "H" may be written).

  FIG. 2 is a perspective view showing a schematic structure of the TDI linear image sensor shown in FIG. Hereinafter, as shown in FIG. 2, the thickness direction of the first semiconductor substrate 1 orthogonal to the X direction and the Y direction is referred to as a “Z direction”.

  In FIG. 2, the pixel array 3 is formed by arranging pixels in a two-dimensional array in a specific region on the main surface (front surface) on the + Z side in the first semiconductor substrate 1. On the main surface on the + Z side of the first semiconductor substrate 1, a plurality of input / output pads 4 are formed together with the horizontal CCD 5 and the output amplifier 6.

  The second semiconductor substrate 2 is a separate substrate from the first semiconductor substrate 1 and mounts a CMOS transistor circuit such as a line selection circuit described later. The second semiconductor substrate 2 is coupled to the + Z side of the first semiconductor substrate 1 with their main surfaces facing each other.

  FIG. 3 is a cross-sectional structural view of the TDI linear image sensor shown in FIG. FIG. 3 shows a state in which the TDI linear image sensor is mounted on the package.

  As shown in FIG. 3, the first semiconductor substrate 1 and the second semiconductor substrate 2 are electrically joined by bumps 8 made of metal, and further bonded on a package 9 made of ceramic or the like in FIG. Yes. The input / output pad 4 on the first semiconductor substrate 1 and the metal electrode 10 on the package 9 are electrically connected by a wire bond 11. A lead 12 is formed on the main surface (back surface) on the −Z side of the package 9.

  Returning to FIG. 1, the bump 8 is formed by bump bonding between a selection line 15 for selecting a pixel in the pixel array 3 in the first semiconductor substrate 1 and a corresponding selection line 16 in the second semiconductor substrate 2. The joint part to be configured is configured.

  The first semiconductor substrate 1 is also provided with input pins for the multiphase transfer clock ΦV and setting terminals for setting the substrate potential Vsub1, corresponding to the input / output pads 4 (FIG. 2). . The setting terminal for the substrate potential Vsub1 is grounded, for example.

  The second semiconductor substrate 2 includes a setting terminal for setting the substrate potential Vsub2, input pins for various clocks ΦV and ΦT, supply terminals for various power supply voltages Vdd and Vss, and a setting terminal for the well potential Vwell. Is provided. The setting terminal for the substrate potential Vsub2 is connected to a constant voltage source having a predetermined negative voltage, for example. The predetermined negative voltage is a voltage lower than the ground potential (GND potential) of the substrate potential Vsub1, and is appropriately set, for example, from the viewpoint of enabling the MPP operation.

  Hereinafter, the circuit configuration on the first semiconductor substrate 1 and the circuit configuration on the second semiconductor substrate 2 will be described, respectively.

1-1. Circuit Configuration on First Semiconductor Substrate FIG. 4 is a circuit diagram showing a circuit configuration formed on the first semiconductor substrate 1 in the TDI linear image sensor shown in FIG.

  As shown in FIG. 4, on the first semiconductor substrate 1, pixels 17 are arranged in a two-dimensional array to form a pixel array 3. A region indicated by a thick broken line in FIG. 4 is a boundary line schematically showing a boundary between the pixels 17. The pixel here is for generating an image signal, and is the smallest repeating unit in the arrangement of the vertical transfer gate 20 and the separation region 21 arranged on the linear image sensor.

  As shown in FIG. 4, the pixel array 3 of the first semiconductor substrate 1 has a plurality of stages in the vertical direction (Y direction). In each stage, a plurality of pixels 17 arranged in the horizontal direction (X direction) are connected to common selection lines 15a to 15d.

  Further, the horizontal CCD 5 is disposed on the side of the pixel array 3 on the −Y side via the charge storage unit 19. As will be described later, the signal charges that have been time-delay integrated by the pixels 17 in a plurality of stages are transferred vertically downward (−Y direction) toward the horizontal CCD 5 in the pixel array 3, and further in the horizontal direction (+ X direction) in the horizontal CCD 5. ) Is read out from the output amplifier 6.

  A charge discharge drain 18 for discharging unnecessary charges is provided on the side (+ Y side) of the pixel array 3 opposite to the arrangement of the horizontal CCD 5.

  In the present embodiment, a four-phase drive CCD is used for TDI transfer in the vertical direction (Y direction) (see FIGS. 9 to 11). The pixel 17 includes a set of four transfer gates 20 corresponding to the first to fourth transfer clocks φV1 to φV4 constituting the multiphase transfer clock φV. The transfer electrodes 20a, 20b, 20c, and 20d in the pixel 17 are made of polysilicon and are sequentially arranged on the Si substrate. A transfer channel (not shown) is formed below the transfer electrodes 20a to 20d. The transfer channel is electrically isolated by an isolation region 21 made of an impurity region having a conductivity type opposite to that of the Si substrate.

  The two transfer electrodes 20a and 20c in the transfer gate 20 are input pins of the first transfer clock φV1 through metal wirings 15a and 15c, contact holes 22a and 22c, and metal wirings 23a and 23c, which are selection lines, respectively. 24a and the third transfer clock φV3 are connected to the input pin 24c. The remaining two transfer electrodes 20b and 20d are connected to bump pads 34b and 34d through metal wirings 15b and 15d, respectively, which are selection lines.

1-2. Circuit Configuration on Second Semiconductor Substrate FIG. 5 is a block diagram showing a circuit configuration of a TDI stage number switching circuit 13 formed on the second semiconductor substrate 2 in the TDI linear image sensor shown in FIG. .

  As shown in FIG. 5, the TDI stage number switching circuit 13 on the second semiconductor substrate 2 includes a line selection circuit 28 and a vertical shift register 33. The line selection circuit 28 is connected to the metal wirings 26b and 26d. Second and fourth transfer clocks φV2 and φV4 are input to the metal wirings 26b and 26d via the input pins 27b and 27d, respectively. The vertical shift register 33 is connected to the three metal wirings 31. Input clocks φT 1, φT 2, and φTS from the outside are input to the respective metal wirings 31 through the input pins 32.

  The bump pads 35b and 35d on the second semiconductor substrate 2 and the bump pads 34b and 34d (FIG. 4) on the first semiconductor substrate 1 are in a one-to-one relationship via the metal bumps 8. Connected. Thereby, the selection lines 15b and 15d on the first semiconductor substrate 1 are connected to the metal wirings 16b and 16d on the second semiconductor substrate 2 on a one-to-one basis.

  The line selection circuit 28 is configured by arranging unit cell circuits 25 each including a selection MOS transistor group by the number of vertical pixels. FIG. 6 shows a circuit diagram of the unit cell circuit 25 of the line selection circuit 28.

  As shown in FIG. 6, the unit cell circuit 25 in the line selection circuit 28 includes four transmission gates 38a, 38b, 38c, and 38d and two inverters 39a and 39b. Each transmission gate 38 is constituted by a pair of one NMOS transistor 36 and one PMOS transistor 37. The operation of the line selection circuit 28 including the unit cell circuit 25 will be described later.

  Returning to FIG. 5, the vertical shift register 33 is configured by arranging the unit cell circuits 30 of the shift register by the number of vertical pixels. FIG. 7 shows a circuit diagram of the unit cell circuit 30 of the vertical shift register 33.

  As shown in FIG. 7, the unit cell circuit 30 of the vertical shift register 33 includes two transmission gates 40a and 40b and two inverters 41a and 41b. Each transmission gate 40a, 40b consists of an NMOS transistor. Transmission gates 40a and 40b and inverters 41a and 41b are alternately connected in series. The operation of the vertical shift register 33 including the unit cell circuit 30 will be described later.

2. Operation The operation of the TDI linear image sensor according to the present embodiment will be described below with reference to the drawings.

  In the TDI linear image sensor (FIG. 1) according to the present embodiment, for example, the substrate potential Vsub1 of the first semiconductor substrate 1 is set to the GND potential (= 0V), and the substrate potential Vsub2 of the second semiconductor substrate 2 is negative. Set to voltage (<0V). As a result, the L voltage (low level voltage) of the transfer clocks φV1 to φV4 can be set to a negative voltage. Regarding the relationship between the L voltage of the transfer clocks φV1 to φV4 and the substrate potentials Vsub1 and Vsub2, the inventor's consideration will be described below.

2-1. Transfer Clock and Substrate Potential In the TDI linear image sensor according to this embodiment, a negative voltage sufficiently lower than the substrate potential Vsub1 of the first semiconductor substrate 1 is set as the L voltage of each transfer clock φV1 to φV4. Thus, similarly to the MPP operation of the CCD image sensor, the pixel dark current can be reduced by pinning the bottom of the transfer electrode in an inverted state. As shown in FIG. 4, the first transfer clock φV1 is input from the input pin 24a to the transfer electrode 20a, and the third transfer clock φV3 is input from the input pin 24c to the transfer electrode 20c. At this time, no transistor or the like is interposed between the input pins 24a and 24c and the transfer electrodes 20a and 20c.

  On the other hand, as shown in FIG. 5, the second transfer clock φV2 and the fourth transfer clock φV4 are connected to the remaining transfer electrodes 20b and 20d via the line selection circuit 26 from the respective input pins 27b and 27d. (See FIG. 14). At this time, a transmission gate 38 is interposed between the input pins 27b and 27d and the transfer electrodes 20b and 20d, as shown in FIG. The inventor of the present application has found that the transmission gate 38 is a factor that prevents the L voltage of the second transfer clock φV2 and the fourth transfer clock φV4 from becoming a negative voltage. Hereinafter, this point will be described with reference to FIG.

  FIG. 8 shows the structure of the transmission gate 38 used in the line selection circuit 28. 2A is a circuit diagram of the transmission gate 38, and FIG. 2B is a diagram showing a cross-sectional structure of elements of the transmission gate 38. FIG.

  In FIG. 8A, the transmission gate 38 includes an NMOS transistor 36 and a PMOS transistor 37 connected to each other at two connection points A and B. Clocks φ and / φ having opposite phases are input to the gates of the transistors 36 and 37, respectively (superscript bars in the figure are indicated by “/”).

  In FIG. 8B, the NMOS transistor 36 includes a gate electrode 46 formed on a p-type silicon substrate 44 with a gate oxide film 45 interposed therebetween, and a source and drain made of an n-type impurity region 47. . The PMOS transistor 37 includes a gate electrode 51 formed on an N well 49 formed on a p-type silicon substrate 44 with a gate oxide film 50 interposed therebetween, and a source and a drain made of a p-type impurity region 52. Is done. A substrate potential Vsub is set to the p-type silicon substrate 44 by an external connection such as ground. The well potential Vwell of the N well 49 is set by the power supply voltage of the external power supply.

  In the transmission gate 38 in the line selection circuit 28 (FIG. 6), the clock voltage based on the second transfer clock φV2 or the fourth transfer clock φV4 is applied to the connection point A or the connection point B in FIG. When the applied clock voltage is lower than the substrate potential Vsub, a forward bias is applied to the PN junction formed by the p-type silicon substrate 44 and the n-type impurity region 47. For this reason, it is assumed that an excessive current flows and prevents the normal operation of the line selection circuit 28.

  When the applied clock voltage is higher than the well potential Vwell, a forward bias is applied to the PN junction formed by the N well 49 and the p-type impurity region 52, and an excessive current flows. The same is assumed. Therefore, for the transmission gate 38, the transfer clock voltage applied to the connection point A or the connection point B in FIG. 8A needs to be not less than the substrate potential Vsub (and not more than the well potential Vwell).

  In a conventional (for example, Patent Document 1) TDI linear image sensor, a line selection circuit and a pixel are formed on the same semiconductor substrate, and a common substrate potential (0 V) is used. For this reason, the conventional TDI linear image sensor has a problem that if the L voltage of the transfer clock is set to a negative voltage, an excessive current flows and the circuit does not operate normally. Further, in order to reduce the pixel dark current as in the MPP operation of the CCD image sensor, the L voltage of the transfer clock is set to be higher than the substrate potential (Vsub1) of the pixel so that the bottom of the pixel electrode is pinned in an inverted state. It must be a sufficiently low negative voltage.

  The inventors of the present application have made extensive studies on the above problems, and as shown in FIG. 1, the first semiconductor substrate 1 and the second semiconductor substrate 2 are formed separately, and the respective substrate potentials Vsub1. The inventors have come up with a configuration that makes Vsub2 independent. According to this configuration, for example, the substrate potential Vsub2 of the second semiconductor substrate 2 can be set lower than the substrate potential Vsub1 of the first semiconductor substrate 1 such as the GND potential, and the first to fourth All L voltages of the transfer clocks φV1 to φV4 can be set to negative voltages. That is, in the first semiconductor substrate 1, the substrate potential Vsub1 with respect to the second semiconductor substrate 2 is maintained at a level higher than the L voltage while the substrate potential Vsub2 is maintained at the L level without disturbing the normal operation of the transmission gate 38. It can be set to a value lower than the voltage. Thereby, the pixel dark output of the TDI linear image sensor can be reduced, or the dynamic range can be expanded.

  Details of the operation of the TDI linear image sensor according to this embodiment will be described below.

2-2. Vertical Transfer Operation First, a vertical transfer operation (TDI operation) in the TDI linear image sensor according to the present embodiment will be described with reference to FIGS.

  9 to 11 are schematic diagrams for explaining the potential change of the CCD transfer channel caused by the clock supplied to the TDI type linear image sensor according to this embodiment. FIGS. 9A to 9D are timing charts of the vertical transfer clock supplied to the four-phase drive CCD. FIG. 10A shows a cross-sectional structure along the charge transfer direction of the four-phase drive CCD. FIGS. 10B to 10F show the state of potential change of the transfer channel in the same section in time series. FIGS. 11A to 11F are the same as FIGS. 10A to 10F in the case where the clock supplied to the transfer electrode is different from FIGS. 10A to 10F. FIG.

  In the present embodiment, first to fourth transfer clocks φV1 to φV4 as shown in FIGS. 9A to 9D are used as drive clocks for the four-phase drive CCD, and each transfer electrode of the pixel 17 (FIG. 4). To supply.

  Here, FIGS. 10B to 10F show the first, second, third, and fourth transfer clocks in order for the four transfer electrodes 20a, 20b, 20c, and 20d (FIG. 10A). The potential distribution of the transfer channel at times t1 to t5 when φV1, φV2, φV3, and φV4 are supplied is shown. 11B to 11F show the second transfer clock φV2 and the fourth transfer clock among the first to fourth transfer clocks φV1 to φV4 supplied to the four transfer electrodes 20a, 20b, 20c, and 20d. The potential distribution of the transfer channel at times t1 to t5 when the transfer clock φV4 is replaced is shown.

  As shown in FIGS. 10A to 10F and FIGS. 11A to 11F, the voltage “H” of the transfer clock φV is applied among the four transfer electrodes 20a, 20b, 20c, and 20d. A potential well 43 is formed under the gate.

  In the case of FIG. 10, the signal charge 42 generated by light incidence is charged to the right side of the drawing as the potential well 43 moves to the right side of the drawing (corresponding to the −Y direction) by the transfer operation of the CCD. Transferred. At this time, the TDI operation can be realized by matching the moving speed of the subject image with the CCD transfer speed, and charge transfer and charge integration are performed simultaneously.

  In the case of FIG. 11, as the potential well 43 moves to the left of the drawing by the CCD transfer operation, the signal charge 42 is transferred to the left of the drawing (corresponding to the + Y direction). Thus, in the four-phase drive CCD, the direction of vertical transfer can be reversed by, for example, replacing φV2 and φV4 among the transfer clocks supplied to the four transfer electrodes 20a, 20b, 20c, and 20d.

  In the vertical transfer operation as described above, the depth of the potential well 43 is defined by the voltage amplitude between “H” and “L” of each transfer clock φV1 to φV4. In the present embodiment, as shown in FIG. 9, the L voltage of each transfer clock φV1 to φV4 can be set lower than “0 (GND potential)”, so that the potential well 43 is deepened and the dynamic range is expanded. Can do.

2-3. Operation of Line Selection Circuit Next, the operation of the line selection circuit 28 in the TDI stage number switching circuit 13 for switching the direction of vertical transfer will be described with reference to FIG.

  In the unit cell circuit 25 of the line selection circuit 28 shown in FIG. 6, one end of two transmission gates 38a and 38b is connected to one metal wiring 16b connected to one transfer electrode 20b. Yes. The other end of one transmission gate 38a is connected to the input pin 27b (= φV2) via the metal wiring 26b, and the other end of the other transmission gate 38b is connected to the input pin 27d (= φV4) via the metal wiring 26d. It is connected to the.

  The line output 29 of the vertical shift register 33 (hereinafter referred to as shift register output) is input to the gate of the NMOS transistor 36a of the transmission gate 38a, and at the same time, the line output 29 passes through the inverter 39a and the PMOS of the transmission gate 38a. Input to the gate of the transistor 37a. Therefore, when the shift register output 29 is “H”, the transmission gate 38a is turned on, the input pin 27b is connected (conductive) to the metal wiring 16b, and the second transfer clock φV2 is supplied to the transfer electrode 20b.

  Further, the shift register output 29 is input to the gate of the PMOS transistor 37b of the transmission gate 38b and simultaneously to the gate of the NMOS transistor 36b of the transmission gate 38b via the inverter 39a. Therefore, when the shift register output 29 is “L”, the transmission gate 38b is turned on, the input pin 27d is connected to the metal wiring 16b, and the fourth transfer clock φV4 is supplied to the transfer electrode 20b.

  On the other hand, one end of two transmission gates 38c and 38d is connected to one metal wiring 16d connected to one transfer electrode 20d. The other end of one transmission gate 38c is connected to the input pin 27d via the metal wiring 26d, and the other end of the other transmission gate 38d is connected to the input pin 27b via the metal wiring 26b.

  The shift register output 29 is input to the gate of the NMOS transistor 36c of the transmission gate 38c and simultaneously input to the gate of the PMOS transistor 37c of the transmission gate 38c via the inverter 39c. Therefore, when the shift register output 29 is “H”, the transmission gate 38c is turned ON, the input pin 27D is connected to the metal wiring 16d, and the fourth transfer clock φV4 is supplied to the transfer electrode 20d.

  The shift register output 29 is input to the gate of the PMOS transistor 37d of the transmission gate 38d, and simultaneously to the gate of the NMOS transistor 36d of the transmission gate 38d via the inverter 39c. Therefore, when the shift register output 29 is “L”, the transmission gate 38d is turned on, the input pin 27b is connected to the metal wiring 16d, and the second transfer clock φV2 is supplied to the transfer electrode 20d.

  That is, the unit cell circuit 25 of the line selection circuit 28 switches the two transfer clocks φV2 and φV4 supplied to the two transfer electrodes 20b and 20d according to whether the shift register output 29 is “H” or “L”. To work.

2-4. Operation of Vertical Shift Register Next, the operation of the vertical shift register 33 according to the shift register output 29 will be described with reference to FIG.

  In the unit cell circuit 30 of the vertical shift register 33 shown in FIG. 7, when the clock (= φT1) supplied to the input pin 32a is set to “H”, the transmission gate 40a is turned on. As a result, the output of the unit cell circuit 30 in the previous stage is input to the inverter 41a, and the inverter 41a performs an inverted output. When the unit cell circuit 30 is in the first stage, not the output of the previous stage but the clock (= φTS) supplied to the input pin 32c is input to the inverter 41a, and the output of the inverter 41a becomes the inverted output of the input clock φTS. .

  Next, when the input clock φT1 is set to “L”. The transmission gate 40a is turned off, and the input and output of the inverter 41a are held as they are.

  Next, when the clock (= φT2) supplied to the input pin 32b is set to “H”, the transmission gate 40b is turned on. The held output of the inverter 41a is input to the inverter 41b and inverted by the inverter 41b. The output signal subjected to the inversion twice in this way is transmitted as the shift register output 29 to the unit cell circuit 25 (FIG. 6) of the line selection circuit 28.

  Next, when the input clock φT2 is set to “L”, the transmission gate 40b is turned OFF. Thereby, the input and output of the inverter 41b are held as they are. Further, when the input clock φT1 is set to “H”, the above series of operations are repeated.

  As described above, in the vertical shift register 33, the clock pulse input as the input clock φTS is sequentially transmitted to the next stage one by one in the plurality of unit cell circuits 30, and is output as the line output 29.

2-5. Next, the setting method and setting operation of the TDI stage number in the TDI type linear image sensor according to the present embodiment will be described with a specific example. As an example, a case where the number of TDI stages is set to 5 in the TDI linear image sensor of 8 vertical pixels × 10 horizontal pixels shown in FIG. 4 will be described with reference to FIGS.

  12 to 13 are diagrams for explaining a TDI stage number setting method by the TDI stage number switching circuit. 12A to 12C are examples of timing charts of the input clocks φTS, φT1, and φT2 supplied to the TDI stage number switching circuit 13. FIG. FIGS. 13A to 13F are diagrams for explaining the operation of the TDI stage number switching circuit 13.

  First, the number of TDI stages is set before imaging (stage number setting mode). Specifically, the number of TDI stages is set by operating the vertical shift register 33 of the TDI stage number switching circuit 13. An example of a clock for driving the vertical shift register 33 when the number of TDI stages is set to 5 is shown in FIG. In addition, FIG. 13 shows how the shift register output changes at times t = 0, 1, 2, 5, 6, and 8 when the drive clock shown in FIG. 12 is supplied.

  The vertical shift register 33 is driven by being supplied with clock pulses of three input clocks φTS, φT1, and φT2 as illustrated in FIGS. A period 0 shown in FIG. 12 is a period for initializing the vertical shift register 33. At this time, the input clock φT1 of FIG. 12B and the input clock φT2 of FIG. 12C are simultaneously set to “H” while the input clock φTS of FIG. As a result, at time t = 0, as shown in FIG. 13A, the shift register outputs 29 of all lines (all unit cell circuits 30) are reset to “L”.

  Next, in the period 1 to the period 5, the input clock φT1 in FIG. 12B and the input clock φT2 in FIG. 12C are alternately set while the input clock φTS in FIG. The vertical shift register 33 is operated by setting it to “H”. As a result, at time t = 1-5, as shown in FIGS. 13B to 13D, the signal from the previous unit cell circuit 30 is transmitted to the next unit cell circuit 30, and each line The shift register output 29 is shifted downward by one stage.

  Next, in the period 6 to the period 8, the input clock φT1 in FIG. 12B and the input clock φT2 in FIG. 12C are alternately set while the input clock φTS in FIG. The vertical shift register 33 is operated by setting it to “H”.

  As a result, at time t = 6 to 8, as shown in FIGS. 13E and 13F, the “H” outputs for five lines are grouped and shifted downward by one stage. Thereafter, when the clock pulses of the three input clocks φT1, φT2, and φTS are stopped at t = 8, the shift register output 29 of each line has an output of “H” for five lines from the lower side in the figure, and the other lines The output is held at “L”.

  Through the above series of operations, the TDI stage number setting mode is completed, and then the following TDI imaging mode is entered.

2-5. Operation in TDI Imaging Mode Next, the operation in the TDI imaging mode will be described with reference to FIG.

  FIG. 14 is a diagram showing the relationship between the voltage of each part of the vertical scanning circuit and the transfer direction of the vertical transfer electrode in a state where the number of TDI stages is set to five. In FIG. 14, a part is extracted from the circuit configuration of the TDI type linear image sensor according to the present embodiment shown in FIG.

  As described above, the clock pulses illustrated in FIGS. 12A to 12C are supplied to the vertical shift register 33 to set the number of TDI stages to five. Then, as shown in FIG. 14, the shift register output 29 of each line is set to “H” from the first stage to the fifth stage from the lower side in the vertical direction (−Y direction), and from the sixth stage to the eighth stage. "L" is set up to this point.

  At this time, by the operation of the line selection circuit 28 described above, the second transfer clock φV2 is supplied to the metal wiring 15b from the first stage to the fifth stage, and the metal wiring 15d from the first stage to the fifth stage is supplied. Is supplied with a fourth transfer clock φV4. Further, the fourth transfer clock φV4 is supplied to the metal wiring 15b from the sixth stage to the eighth stage, and the second transfer clock φV2 clock is supplied to the metal wiring 15d from the sixth stage to the eighth stage. The

  Here, the first to fourth transfer clocks φV1 to φV4 shown in FIGS. 9A to 9D are supplied with the vertical shift register 33 stopped. Then, in the TDI linear image sensor shown in FIG. 14, the vertical transfer is in the −Y direction (forward direction) from the first stage to the fifth stage from below, and the vertical transfer from the sixth stage to the eighth stage from below. Becomes the + Y direction (reverse direction). At this time, by matching the transfer speed of the vertical CCD (that is, the operation speed of the vertical transfer operation) with the moving speed of the subject image, it is possible to time-delay and integrate the pixel signals for five stages from the lower side of the figure.

  In the above example, the case where TDI imaging is performed with the number of TDI stages set to 5 has been described, but the present invention is not particularly limited thereto. By simply changing the clock pulse φTS supplied to the vertical shift register 33, the number of TDI stages can be set to an arbitrary number.

  That is, in the input clocks φTS, φT1, and φT2 for driving the shift register as shown in FIGS. 12A to 12C, the period is from 1 to M (M is a natural number equal to or less than the number of transfer stages of the vertical CCD). By setting the input φTS of 12 (a) to “H”, the number of TDI stages can be set to M stages.

3. Summary As described above, the TDI linear image sensor according to the present embodiment includes the pixel array 3, the plurality of selection lines 15, the line selection circuit 28, and the horizontal CCD 5. In the pixel array 3, pixels 17 having transfer electrodes 20 a to 20 d for performing photoelectric conversion and vertically transferring the generated charges by time delay integration are arranged two-dimensionally. The plurality of selection lines 15 are connected to the transfer electrodes 20a to 20d, and supply multiphase transfer clocks φV1 to φV4. The line selection circuit 28 selects transfer clocks φV2 and φV4 to be supplied to predetermined selection lines 15b and 15d among the plurality of selection lines 15 in the multiphase transfer clocks φV1 to φV4. The horizontal CCD 5 horizontally transfers the charge integrated with time delay. A pixel array 3, a plurality of selection lines 15, and a horizontal CCD 5 are formed on the first semiconductor substrate 1. The line selection circuit 28 is formed on the second semiconductor substrate 2 that is electrically connected to the first semiconductor substrate 1. The substrate potential Vsub1 of the first semiconductor substrate 1 and the substrate potential Vsub2 of the second semiconductor substrate 2 are electrically independent.

  According to the TDI linear image sensor described above, the L voltage of the transfer clocks φV1 to φV4 can be set to a negative voltage while the line selection circuit 28 is normally operated. As a result, the voltage amplitude of the transfer clocks φV1 to φV4 is increased, and the depth of the potential well 43 formed in the transfer channel is increased, so that the maximum transfer charge amount of the vertical CCD is increased and the dynamic range can be expanded. .

  In the present embodiment, the substrate potential Vsub2 of the second semiconductor substrate 2 is lower than the substrate potential Vsub1 of the first semiconductor substrate 1. The TDI linear image sensor according to the present embodiment is configured so that the substrate potential Vsub1 of the first semiconductor substrate 1 and the substrate of the second semiconductor substrate 2 can be set so that the substrate potentials Vsub1 and Vsub2 can be set. And a setting terminal for the potential Vsub2 (see FIG. 1).

  In this embodiment, the transfer clocks φV1 to φV4 have a high level “H” higher than the substrate potential Vsub1, such as the GND potential, and a low level “L” lower than the same potential Vsub1 (see FIG. 9). . The substrate potential Vsub2 of the second semiconductor substrate 2 is lower than the low level “L” of the transfer clocks φV1 to φV4.

  For example, when the L voltage of the transfer clocks φV1 to φV4 is set to a sufficiently low negative voltage so that the bottom of the transfer electrodes 22a to 22d is pinned in an inverted state, the substrate potential Vsub2 of the second semiconductor substrate 2 is Such a potential is set to the L voltage or lower. Accordingly, the generation of thermally excited electrons at the oxide film interface is suppressed by the transfer clocks φV1 to φV4, and the pixel dark current is reduced.

  Note that the L voltage of the transfer clocks φV1 to φV4 may not be a sufficiently low negative voltage as described above. Even in this case, the substrate potential Vsub2 of the second semiconductor substrate 2 is appropriately set to be equal to or lower than the L voltage of the transfer clocks φV1 to φV4. Thereby, a dynamic range can be ensured according to the voltage amplitude of the transfer clocks φV1 to φV4.

  The TDI linear image sensor according to this embodiment further includes a vertical shift register 33. The vertical shift register 33 outputs to the line selection circuit 28 a shift register output 29 that sets a transfer direction in which charges are transferred in the pixel array 3. Based on the shift register output 29, the line selection circuit 28 replaces any of the multi-phase transfer clocks φV1 to φV4 (FIG. 10) to generate a reverse-phase transfer clock (FIG. 11) (see FIG. 14).

  With the above configuration, the charge transfer direction can be switched between the forward direction and the reverse direction from an arbitrary position of the pixel array 3. As a result, it is possible to expand the dynamic range and reduce the pixel dark output while having the function of arbitrarily setting the number of TDI stages. Note that the line selection circuit 28 may be used not only for switching the number of TDI stages but also for switching the signal charge transfer direction (see Patent Document 2).

  The driving method of the TDI linear image sensor according to the present embodiment includes a step of setting the substrate potential Vsub2 of the second semiconductor substrate 2 to be lower than the substrate potential Vsub1 of the first semiconductor substrate 1. The method includes the step of the line selection circuit 28 outputting the second and fourth transfer clocks φV2 and φV4 as signals based on predetermined high potential (H) and low potential (L). The low potential (L) of the signal output by the line selection circuit 28 is lower than the substrate potential Vsub1 of the first semiconductor substrate 1.

  According to the driving method of the TDI linear image sensor described above, the LDI of the transfer clocks φV1 to φV4 is set to a negative voltage so that the TDI linear image sensor operates normally, and the dynamic range can be expanded and the pixel dark output can be reduced.

Embodiment 2. FIG.
In the second embodiment, similarly to the first embodiment, the substrate potentials Vsub1 and Vsub2 of the first and second semiconductor substrates 1 and 2 are set in the TDI linear image sensor, and the L voltage of the transfer clock φV is set to a negative voltage. . In the second embodiment, a TDI linear image sensor that uses an expanded voltage amplitude of an external input clock φT will be described. A TDI linear image sensor according to Embodiment 2 will be described with reference to FIGS.

  FIG. 15 is a block diagram showing a configuration of a TDI linear image sensor according to Embodiment 2 of the present invention. FIG. 16 is a circuit diagram showing the configuration of the unit cell circuit 60 of the clock driver circuit 14 provided in the previous stage of the TDI stage number switching circuit 13 in the TDI linear image sensor shown in FIG.

  The TDI linear image sensor according to the second embodiment has the same configuration as that of the TDI linear image sensor according to the first embodiment shown in FIG. A clock driver circuit 14 is further provided in the previous stage.

  The clock driver circuit 14 is a circuit that converts the input clock φT from the outside so as to increase the respective voltage amplitudes and supplies the converted voltage to the TDI stage number switching circuit 13. In the present embodiment, the clock driver circuit 14 is configured by providing one unit cell circuit 60 shown in FIG. 15 (that is, three) for each input clock φT1, φT2, and φTS.

  As shown in FIG. 16, in the unit cell circuit 60 of the clock driver circuit 14, three inverters 55, 56, and 57 are connected in series, and for example, an inverted clock / φT is output with respect to the input clock φT. A power supply voltage Vdd1 is supplied to the first-stage inverter 55, and a power-supply voltage Vdd2 larger than the power-supply voltage Vdd1 of the first-stage inverter 55 is supplied to the second and subsequent inverters 56 to 58 (Vdd1 <Vdd2). Each power supply voltage Vdd1, Vdd2 is set to a desired magnitude using an external power supply. The operation of the clock driver circuit 14 will be described later.

  According to the TDI linear image sensor according to the second embodiment configured as described above, power consumption when the L voltage of the transfer clock φV is set to a negative voltage is reduced. Hereinafter, this point will be described with reference to the drawings.

  For example, in the TDI linear image sensor shown in FIG. 1, in the unit cell circuit 30 (FIG. 7) of the vertical shift register 33, two inverters 41a and 41b are used per unit cell circuit. In the unit cell circuit 25 of the line selection circuit 28 shown in FIG. 6, two inverters 39a and 39b are used for each unit cell circuit. In such an inverter circuit, the high-level power supply voltage Vdd is set equal to the well potential Vwell of the second semiconductor substrate 2 (FIG. 1), and the low-level power supply voltage Vss is set equal to the substrate potential Vsub2. The

  In the above case, in order to operate the inverter circuit normally, it is necessary to set the power supply voltage Vdd to the H voltage (high level voltage) of the transfer clock φV or higher and the substrate potential Vsub2 to the L voltage of the transfer clock φV or lower. .

  Here, generally, the clock voltages of the input clocks φT1, φT2, and φTS given from the outside are often at a so-called TTL level and the like, and it is assumed that the voltage amplitude is smaller than that of the transfer clock φV. In this case, in the unit cell circuit 30 shown in FIG. 7, the voltage applied to the input gates of the inverters 41a and 41b becomes a voltage near the middle of Vdd and Vss, and a large amount of through current flows, resulting in an increase in power consumption. Conceivable.

  On the other hand, in the TDI linear image sensor according to the present embodiment, the through current as described above is suppressed by using the clock driver circuit 14. Hereinafter, the operation of the TDI linear image sensor according to this embodiment will be described.

  In the TDI linear image sensor according to the second embodiment of the present invention shown in FIG. 15, input clocks φT1, φT2, and φTS are input to the clock driver circuit 14. The clock driver circuit 14 boosts the input clocks φT1, φT2, and φTS, and the output signal of the clock driver circuit 14 is input to the shift register 33.

  In the unit cell circuit 60 of the clock driver circuit 14 shown in FIG. 16, when the input clock φT is “L”, the output of the first stage inverter 55 becomes “H” and the potential at the point B becomes “Vdd1”. Since the input of the second stage inverter 56 is “H”, its output is “L”, and the potential at the point D is “Vss”. At this time, since the input of the inverter 58 in the reverse direction is “L”, its output becomes “H”, and the potential at the point C is raised to “Vdd2”. At this time, the NMOS transistor 59 provided between the point B and the point C functions as a switch for cutting off the current generated by the potential difference between the points B and C. Since the input of the third stage inverter 57 is “L”, its output is “H”, and the potential at the F point is “Vdd2”.

  Further, when the input clock φT is “H”, the output of the first stage inverter 55 becomes “L”, and the potential at the point B becomes “Vss”. Since the input of the second stage inverter 56 is “L”, its output is “H”, and the potential at the point D is “Vdd2”. At this time, since the input of the inverter 58 in the reverse direction is “H”, the output is “L”, and the potential at the point C is “Vss”. Since the input of the third stage inverter 57 is “H”, its output is “L”, and the potential at the point F is “Vss”.

  In the above operation, the input voltage of the inverters 56 to 58 in the second and subsequent stages is “Vdd2” or “Vss”, which is equal to the well potential Vwell or the substrate potential Vsub2. It can be prevented from flowing.

  Further, by setting the power supply voltage Vdd1 of the first-stage inverter 55 to be equal to the H voltage of the input clock φT, when the input clock φT is “H”, no through current flows through the first-stage inverter 55. . When the input clock φT is “L” and the L voltage is 0 V, for example, if the low-level power supply voltage Vsub2 is made negative in order to make the L voltage of the transfer clock φV negative, the first-stage inverter 55 It is assumed that a through current flows in At this time, the amount of through current can be reduced by minimizing the size of the transistor constituting the first-stage inverter 55.

  According to the above configuration, when the L voltage of the transfer clock φV is a negative voltage, the power consumption can be reduced even when the clock amplitude of the external input clock φT for setting the number of TDI stages is small. is there.

  As described above, the TDI linear image sensor according to this embodiment further includes the clock driver circuit 14. The clock driver circuit 14 applies an input clock φT, which is a selection signal input from the outside, to a high potential “H” corresponding to the high-level power supply voltage Vdd2 and a low potential “L” corresponding to the low-level power supply voltage Vss. To a signal based on "". The line selection circuit 28 in the TDI stage number switching circuit 13 operates based on the signal converted by the clock driver circuit 14.

  According to the TDI linear image sensor described above, the voltage amplitude of the transfer clock φV output from the line selection circuit 22 can be made larger than the voltage amplitude of the input clock φT as an external selection signal. Further, the through current at this time can be suppressed.

Embodiment 3 FIG.
In the third embodiment, similarly to the first and second embodiments, the substrate potentials Vsub1 and Vsub2 of the first and second semiconductor substrates 1 and 2 are set in the TDI linear image sensor, and the L voltage of the transfer clock φV is set to a negative voltage. To. In the second embodiment, the power consumption in the clock driver circuit is reduced by dividing the power supply voltage on the high level side into two. In the third embodiment, a TDI linear image sensor that further divides a low-level power supply voltage into two in a clock driver circuit will be described with reference to FIGS.

  FIG. 17 is a block diagram showing a configuration of a TDI linear image sensor according to Embodiment 3 of the present invention. FIG. 18 is a circuit diagram showing the configuration of the unit cell circuit 60A of the clock driver circuit 14A provided in the previous stage of the TDI stage number switching circuit 13 in the TDI linear image sensor shown in FIG.

  The TDI linear image sensor according to the third embodiment of the present invention has the same configuration as that of the TDI linear image sensor according to the second embodiment shown in FIG. 15, and two power supply voltages Vss1 and Vss2 are also provided on the low level side. A clock driver circuit 14A is used.

  As shown in FIG. 18, in the unit cell circuit 60A of the clock driver circuit 14A according to the present embodiment, the voltage Vss1 having the smaller absolute value of the power supply voltages Vss1 and Vss2 on the low level side is supplied to the first-stage inverter 55. The other voltage Vss1 is applied to the second and subsequent inverters 56-58. The setting of the power supply voltages Vss1 and Vss2 on the low level side is performed by connecting the low level side of each inverter to an external power supply or the like. Further, Vss1 = 0V may be used. In this case, the first-stage inverter 55 is grounded.

  In the present embodiment, the inverter and the PMOS transistor in the clock driver circuit 14A are composed of CMOS transistors having a triple well structure.

  According to the TDI linear image sensor according to the third embodiment configured as described above, the power consumption when the L voltage of the transfer clock φV is set to a negative voltage is further reduced. Hereinafter, this point will be described with reference to the drawings.

  In the TDI linear image sensor shown in FIG. 15, when the substrate clock Vsub2 is set to a negative potential when the input clock φT is 0V, it is assumed that a through current flows through the first-stage inverter 55. On the other hand, in the TDI type linear image sensor according to the present embodiment shown in FIG. 18, the through-current flows even when the input clock φT is 0 V by using the two power supply voltages Vss1 and Vss2 on the low level side. Do not.

  In the unit cell circuit of FIG. 18, when the input clock φT is “H”, the output of the first stage inverter 55 becomes “L”, and the potential at the point B becomes “Vss1”. Since the input of the second stage inverter 56 is “L”, its output is “H”, and the potential at the point D is “Vdd2”. At this time, since the input of the inverter 58 in the reverse direction is “H”, the output is “L”, and the potential at the point C is lowered to “Vss2”. At this time, the PMOS transistor 61 provided between the points B and C acts as a switch for cutting off a current generated by the potential difference between the points B and C. Since the input of the third stage inverter 57 is “H”, its output is “L”, and the potential at the F point is “Vss2”.

  Since the operation when the input clock φT is “L” in the unit cell circuit 60A of FIG. 18 is the same as that of the second embodiment (FIG. 16), description thereof is omitted.

  In the above operation, the input voltages of the inverters 56 to 58 after the second stage are “Vdd2” or “Vss2”. By setting the power supply voltages Vdd2 and Vss2 equal to the well potential Vwell and the substrate potential Vsub2, it is possible to prevent a through current from flowing through the inverters 56 to 58.

  Further, by setting the high-level power supply voltage Vdd1 of the first-stage inverter 55 equal to the H voltage of the input clock φT and setting the low-level power supply voltage Vss1 equal to the L voltage of the input clock φT, the first-stage inverter Even at 55, it is possible to prevent a through current from flowing.

  In the TDI linear image sensor according to this embodiment as described above, the substrate potential of the CMOS circuit among the circuits formed on the common semiconductor substrate 2 needs to be divided into two, “Vss1” and “Vss2”. . Therefore, this can be realized by adopting a triple well CMOS circuit.

  According to the above configuration, when the L voltage of the transfer clock φV is set to a negative voltage, the power consumption can be reduced more effectively when the clock amplitude of the external input clock φT for setting the number of TDI stages is small. is there.

  As described above, in the TDI linear image sensor according to the present embodiment, the second semiconductor substrate 2 includes the clock driver circuit 14A, the line selection circuit 22 and the like as a CMOS circuit including a triple well transistor. . Thereby, the VDD voltage and the VSS voltage of the clock driver circuit 14A and the line selection circuit 22 can be set to different potentials, and the power consumption of the circuit on the second semiconductor substrate 2 can be reduced.

  The TDI linear image sensor driving method according to the present embodiment includes a step of setting a potential “Vdd1” equal to the H voltage of the input clock φT as a selection signal in the clock driver circuit 14A, and the L of the input clock φT. Setting a potential “Vss1” equal to the voltage. Thereby, the through current that can flow through the clock driver circuit 14A is reduced, and the power consumption can be reduced.

  As described above, specific embodiments and modifications of the present invention have been described. However, the present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the present invention. it can. For example, a combination of the contents of the individual embodiments described above may be used as an embodiment of the present invention.

  DESCRIPTION OF SYMBOLS 1 1st semiconductor substrate, 2nd 2nd semiconductor substrate, 3 pixel array, 4 pad, 5 horizontal CCD, 6 output amplifier, 7 CMOS circuit, 8 bump, 9 package, 10 pad (on package), 11 wire bond, 12 lead pin, 13 TDI stage number switching circuit, 14 clock driver circuit, 15 selection line, 16 selection line, 17 pixel, 18 charge discharge drain, 19 charge storage unit, 20 transfer gate, 21 isolation region, 22 contact, 23 metal wiring, 24 pad, 25 unit cell circuit, 26 metal wiring, 27 pad, 28 line selection circuit, 29 line output, 30 unit cell circuit, 31 metal wiring, 32 pad, 33 vertical shift register, 34 bump pad, 35 bump pad 36 NMOS, 37 PMOS, 38 Transformer Mission gate, 39 inverter, 40 NMOS, 41 inverter, 42 charge, 43 potential well, 44 p-type Si substrate, 45 gate oxide film, 46 gate, 47 n-type impurity region, 48 channel, 49 N well, 50 gate oxide film , 51 gate, 52 p-type impurity region, 53 channel, 54 field oxide film, 55 inverter, 56 inverter, 57 inverter, 58 inverter, 59 NMOS, 60 unit cell circuit, 61 PMOS

Claims (8)

A pixel group in which two-dimensionally arranged pixels having transfer electrodes for performing photoelectric conversion and vertically transferring the generated charges by time delay integration;
A plurality of selection lines connected to each of the transfer electrodes and supplying a multi-phase transfer clock;
A line selection circuit for selecting a transfer clock to be supplied to a predetermined selection line among the plurality of selection lines in the multi-phase transfer clock;
A horizontal transfer unit that horizontally transfers the time-delay integrated charge,
The pixel group, the plurality of selection lines, and the horizontal transfer unit are formed on a first semiconductor substrate,
The line selection circuit is formed on a second semiconductor substrate electrically connected to the first semiconductor substrate,
A TDI linear image sensor, wherein a substrate potential of the first semiconductor substrate and a substrate potential of the second semiconductor substrate are electrically independent. The TDI linear image sensor according to claim 1, wherein a substrate potential of the second semiconductor substrate is lower than a substrate potential of the first semiconductor substrate. The multi-phase transfer clock has a high level higher than the substrate potential of the first semiconductor substrate and a low level lower than the substrate potential of the first semiconductor substrate;
3. The TDI linear image sensor according to claim 2, wherein a substrate potential of the second semiconductor substrate is equal to or lower than a low level of the multiphase transfer clock. A vertical shift register that outputs to the line selection circuit an output signal that sets a transfer direction in which the charge is transferred in the pixel group;
4. The TDI linear image according to claim 1, wherein the line selection circuit generates a reverse-phase transfer clock by replacing any of the multi-phase transfer clocks based on the output signal. 5. Sensor. 5. The TDI linear image sensor according to claim 1, wherein a CMOS circuit including a triple well structure transistor is formed on the second semiconductor substrate. A clock driver circuit for converting a selection signal input from the outside into a signal based on a predetermined high potential and low potential;
The TDI linear image sensor according to claim 1, wherein the line selection circuit operates based on a signal converted by the clock driver circuit. Setting the substrate potential of the second semiconductor substrate to be lower than the substrate potential of the first semiconductor substrate;
The line selection circuit outputs a signal based on a predetermined high potential and low potential, and
7. The TDI linear image sensor driving method according to claim 1, wherein a low potential of a signal output by the line selection circuit is lower than a substrate potential of the first semiconductor substrate. 8. Setting a potential equal to the high level of the selection signal in the clock driver circuit;
The method for driving a TDI linear image sensor according to claim 6, further comprising: setting a potential equal to a low level of the selection signal in the clock driver circuit.

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