JPH0471280B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a signal transmission device suitable for application to an analog delay device using a charge transfer element such as a CCD.

BACKGROUND TECHNOLOGY AND PROBLEMS For example, when an analog delay element is constructed from a CCD, a predetermined delay time is established between an input section 1 and an output section 2 provided on a semiconductor substrate, as shown in Fig. 1. A signal transfer unit 3 is provided as shown in FIG. The signal transfer section 3 is configured as an n-bit shift register, and two-phase drive is adopted for transferring the analog signal S. φ ₁ and φ ₂ indicate the transfer clocks. First and second input gates IG ₁ and IG ₂ are provided before the signal transfer section 3, and
A first stage transfer electrode _φ1F is provided between the second input gate _IG2 and the transfer electrode. 4 is a generator of transfer clocks φ ₁ and φ ₂ , and 5 is a driver thereof.

FIG. 2 is a cross-sectional view of the signal transfer section 3, in which the semiconductor substrate 7 is a P-type substrate.

Reference numeral 8 denotes an N ⁺ type region that constitutes the analog signal input section 1, and since it is configured as an embedded channel in this example, an N type region 9 is formed at a predetermined interval in the signal transfer section 3. At the same time, an N ^- type region 11 forming a predetermined potential barrier in the transfer direction is formed.

A predetermined analog signal S is supplied to the input electrode IN, and two-phase transfer clocks φ ₁ and φ ₂ shown in FIG. 3A and B are supplied to the two-phase transfer electrode, and the first input gate A transfer clock φ ₂ is supplied to IG ₁ , a predetermined DC bias (several to 10 V) is supplied to the second input gate IG ₂ , and a transfer clock φ ₁ is supplied to the first stage transfer electrode φ _1F . be done.

As is well known, the analog signal S supplied to the input section 1 is taken in one bit at a time and sequentially transferred via the signal transfer section 3, so that an analog input signal delayed by a predetermined time is output. Obtained on the part 2 side.

Now, in order to reduce power consumption and save power in the analog delay device 10 configured as described above, the amplitudes of the transfer clocks φ ₁ and φ ₂ may be made smaller than the current ones, for example. For example, if the current amplitude value is
If the voltage is 10V, lowering it to around 5V can significantly reduce power consumption. In this way, when the amplitude values of the transfer clocks φ ₁ and φ ₂ are decreased, the first input gate
As the amplitude of the pulse applied to IG ₁ and the first stage transfer electrode φ _1F becomes smaller, the applied voltage naturally becomes lower, but lowering the gate voltage applied to these signal input stages causes the following inconvenient problems. arise.

That is, although the signal input stage between the input section 1 and the signal transfer section 3 has a surface channel configuration, the voltage applied to the signal input section (gate voltage V _G ),
The relationship between the depth PW of the potential well formed in the semiconductor substrate 7 by this gate voltage V _G is as shown by curve 1 in FIG. 4.

Here, the gate voltage V _G is a general term for the voltage applied to the signal input stage, and specifically, the voltage applied to the input electrode IN, the first and second input gate voltages, and the first stage transfer electrode φ Refers to the voltage of the clock pulse applied to _1F .

Region I where the gate voltage V _G is high as shown in the figure
(5V to 10V) has a linear characteristic, so a potential well PW proportional to the applied gate voltage _VG is formed in the semiconductor substrate 7 corresponding to each electrode, so that it operates in this region I. By selecting the voltages of each part as follows, the signal charge corresponding to the analog input signal S can be taken in, and the taken-in signal charge can be transferred to the signal transfer section 3.
Conventionally, this region I has been used as the operating region. Therefore, the amplitude value of the transfer clocks φ ₁ and φ ₂ is 10V,
The voltage applied to the input gate IG ₂ of is
7.5V, and the offset voltage of the input signal is selected to be 4 to 6V, respectively.

On the other hand, in a region where the gate voltage V _G is relatively small (for example, 5 V or less), the characteristics are nonlinear.
Therefore, in order to reduce power consumption, if the level of the transfer clocks φ ₁ and φ ₂ is lowered to about 5V, the first
input gate voltage and first stage transfer electrode φ _1F
The voltage will also be below 5V. With such a voltage, the second input gate voltage must also be lower than 5V, and the DC offset voltage of the input signal must also be lowered to about 3 to 4V.

Therefore, in such a case, the signal input stage operates in the range, and the linearity of the analog delay device 10 deteriorates significantly.

OBJECTS OF THE INVENTION Accordingly, the present invention is intended to reduce power consumption and to prevent deterioration of the linearity of input/output characteristics in the signal input stage that occurs due to power saving.

SUMMARY OF THE INVENTION Therefore, in the present invention, the gate pulse applied to the first input gate IG ₁ and the clock pulse applied to the first stage transfer electrode φ _1F are not shared by the transfer clocks φ ₁ and φ ₂ , but are applied independently to each other. In addition, the voltages at each part are selected so that at least the characteristics of the signal input stage are in the above-mentioned region.

Embodiment Next, an example of the present invention applied to the above-mentioned analog delay device will be described in detail with reference to FIG. 5 and subsequent figures.

In this invention, the peak values of the amplitudes of the transfer clocks φ ₁ ' and φ ₂ ' supplied to the clock terminals 20 and 21 as shown in FIG. A low voltage, for example 5V, is selected, and a first input gate terminal 22 and a first stage transfer electrode terminal 23 are provided. The terminal 22 is supplied with the first input gate pulse IG ₁ whose amplitude peak value as shown in FIG. As shown in D, a transfer clock φ _1F whose peak amplitude value is also selected to be 10V is supplied. The DC value of the second input gate IG ₂ is, as before, 7.5V in this example.

The first input gate pulse IG ₁ and the transfer clock φ _1F are selected to have the same frequency as the two-phase transfer clocks φ ₁ ′ and φ ₂ ′, and have a duty of 50% or less, thereby ensuring non-overlap. Supplied as a drop. The reason for this non-overlapping arrangement is to enable the analog input signal to be sequentially transferred one bit at a time to the signal transfer section 3 via the signal input stage, as will be clear from the explanation below.

In addition, the duty of the two-phase transfer clocks φ ₁ ' and φ ₂ ' is selected to be 50% or more, and the phase relationship is such that the edges of one transfer clock correspond to the high level section of the other transfer clock in an overlapping state. was chosen because of the pulse noise that occurs at the rising and falling edges of the transfer clock (Fig. 6 E and F).
This is to prevent unnecessary charges generated by the signal charges from being mixed into the signal charges.

Now, if the terminals 22 and 23 are provided respectively in this way and the pulse IG ₁ and the clock φ _1F of a predetermined level are supplied, the gate voltage V _G at the signal input stage will both correspond to the area shown in FIG. Therefore, the DC offset of the input signal is set to 4 as before.
By selecting a voltage of .about.6V, the input/output characteristics at the signal input stage become linear characteristics as shown in the region of FIG. This makes it possible to realize low-voltage driving of the signal transfer section 3 and to improve the linearity of the signal input stage.

Potential wells showing the analog input signal capture and transfer states when these pulses IG ₁ , φ _1F and transfer clocks φ ₁ ′φ ₂ ′ are used are shown in FIGS. 5B to 5G. These potential wells correspond to time points _t1 to _t6 in FIG. 6, respectively. In FIG. 5, the diagonal lines indicate signal charges corresponding to the analog input signal.

Application Example The above embodiment is an example in which the present invention is applied to an analog delay device, but the present invention can also be applied to an analog field memory, an image sensor, etc. that uses a charge transfer device such as a CCD.

Charge transfer devices are not limited to CCDs.

Effects of the Invention As explained above, according to the present invention, the amplitude values of the transfer clocks φ ₁ ′, φ ₂ ′ can be reduced, so power consumption can be reduced, and the transfer clocks φ ₁ ′, φ 2 ′ can be reduced in amplitude.
It is possible to prevent deterioration of the linearity of the signal input stage due to the reduction in the amplitude value of φ ₂ '. Therefore,
The present invention is extremely suitable for application to a signal transmission device that handles analog signals.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of an analog delay device used to explain the present invention, Fig. 2 is a cross-sectional view of a part thereof, Fig. 3 is a waveform diagram of a transfer clock, and Fig. 4 is a gate at a signal input stage. FIG. 5 is a curve diagram showing the relationship between voltage and potential well; FIG. 5 is a sectional view similar to FIG. 2 showing an example of the application of the present invention to an analog delay device; and FIG. FIG. 3 is a waveform diagram for explaining the operation of the present invention. 1 is an input section, 2 is an output section, 3 is a signal transfer section,
4 and 5 are peripheral circuits, and φ ₁ , φ ₂ , φ ₁ ', and φ ₂ ' are transfer clocks.

Claims (1)

[Claims] 1. In a signal transmission device having an analog signal transmission element using a charge transfer element, a signal input stage of the analog signal transmission element is provided with first and second input gates and a first stage transfer electrode, A signal transmission device in which the amplitude value of the two-phase transfer clock supplied to the transfer electrode of the analog signal transmission element is selected to be smaller than the amplitude value of the signal supplied to the input gate and the first stage transfer electrode.