JPS5813999B2 - Denkaketsugososhinokudohou - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for driving a charge-coupled device, and its purpose is to simplify peripheral circuitry.

In recent years, charge-coupled devices have been rapidly developed on the back of integrated circuit technology, and their applications in various fields have been proposed.

The feature of this element is that the movement of a group of charges corresponding to an analog quantity is controlled from an external circuit.

Various analyzes have been conducted on the mechanism of charge movement, and device structures that enable faster charge movement have also been proposed.

However, since this movement requires a finite amount of time, there is a maximum movement speed determined by the element structure and manufacturing process.

That is, there is a maximum operating frequency.

On the other hand, according to communication theory, it is known that the highest signal frequency propagating inside a charge-coupled device is a factor in the operating frequency.

Therefore, the element cannot propagate a signal higher than the maximum operating frequency i.

However, by using multiple rows of charge-coupled devices and shifting the phase of their respective operating frequencies, it is possible to increase the apparent propagation frequency.

Such a configuration is called a multiplex configuration, and has been well known as a method of increasing the propagation frequency in a shift register using a group of MOS elements.

Such a multiplex configuration can also be easily achieved when a charge-coupled device is used as a signal delay line or an imaging device.

On the other hand, in order to operate a charge-coupled device, it is necessary to inject a certain amount of bias charge in order to increase the transfer efficiency or reduce the occurrence of distortion inside the device.

Furthermore, such bias charge injection is required to be sufficiently stable and have low noise.

The object of the present invention is to provide a novel driving method for injecting signal charges or bias charges into a charge-coupled device having such a multiplex configuration with low noise.

The present invention includes a plurality of charge transfer column groups arranged in parallel, a single charge detection floating diffusion layer provided at one end of the transfer column group, and a reset gate electrode that moves the diffusion layer at a constant period. means for charging the diffusion layer, means for detecting the potential of the diffusion layer,
a single charge injection diffusion layer provided at the other end of the transfer column group; a first input gate electrode; a second input gate electrode having a DC bias means; In a charge-coupled device comprising a third input gate electrode that functions to sequentially inject charges under a transfer electrode, applying a common pulse train to the reset gate electrode and the third input gate electrode. easily achieved by

In the prior art, the reset gate electrode and the third input gate electrode were driven by different pulsers with different phases, but in the present invention, it is possible to drive them with a single pulser.

That is, according to the present invention, there are great advantages such as the simplification of peripheral circuits and the ability to reduce the number of pins of an element package.

Next, a detailed explanation will be given with reference to the drawings.

FIG. 1 is a diagram showing one embodiment of the present invention, and is a structural plan view showing a charge coupled device.

In the figure, reference numeral 1 denotes an input diffusion layer having a conductivity type different from that of the grounded substrate semiconductor.

In this specification, for convenience, an N-channel structure, that is, a structure using a p-type semiconductor substrate is used.

In such a case, 1 is an n-type diffusion layer.

Reference numerals 2, 3, and 4 are first, second, and third gate electrodes, respectively, which are arranged adjacent to each other on an insulating film such as an oxide film covering the substrate.

11, 12.13...18.19 and 1 1',
12', 13', . . . 18', 19' are transfer electrode groups forming a set of charge transfer paths, respectively.

In Figure 1, the numbers 1 and 2 shown within the electrode shape
indicates the type of transfer pulse applied to the electrode.

That is, it is clear that the figure shows a two-phase drive type charge coupled device as an example.

In FIG. 1, 5 is an output gate electrode including means to be DC biased by an external power source, 6 is a floating n-type diffusion layer for detecting charges, 8 is an n-type diffusion layer biased to DC, and 7 is an output gate electrode including a means for DC biasing by an external power source. The reset gate electrode located in the middle is a MOSFET.

The gate electrode 10 of the MOSFET is electrically connected to the floating diffusion layer 6.

Note that the electrical connection may be a direct current connection via a contact hole provided in the insulating film, or may be an alternating current coupling using capacitance via the insulating film.

Furthermore, the source 20 and drain 2 of the MOSFET 9
1 are each connected to a suitable external electrical network,
1 operates as a source follower or a source-grounded amplifier.

FIG. 2 is a time chart of pulse waveforms of various parts and output signal waveforms for driving the embodiment shown in FIG. 1.

In the same figure, 31.32 are respectively 11, 13,...
・18, 12',...19' and 12,...19
, 11', 13', .

33 is a pulse waveform supplied to the input diffusion layer 1, 34 is a pulse waveform commonly connected to the third input gate electrode 4 and reset gate electrode 7, and 35 is a pulse waveform supplied to the MOSFET 9.
This is the output signal waveform observed outside the element via 6
It is similar to the potential change of .

Next, the operation of the embodiment shown in FIG. 1 will be explained using the time chart shown in FIG.

As mentioned above, one set of charge transfer paths in FIG.
It is driven in two phases by the first phase and second phase pulse groups, and the signal charges inside the transfer path are sequentially transferred to the right, that is, to the side where the floating diffusion layer 6 is present, according to a well-known operation.

Final electrode 1 of two transfer paths adjacent to output gate electrode 5
Since pulse waveforms of different phases, that is, 32.31, are applied to electrodes 9 and 19', if the voltage applied to the electrode 5 is smaller than the peak value of the pulse waveform, the voltage from 19, 19' The times at which the signal charges are released coincide with falling times 1, 14 of 32.31, respectively.

Therefore, since the phases of the pulses applied to 19 and 19' are shifted, the signal charges from the two transfer paths are alternately released.

Further, since the signal charge is released to the floating diffusion layer region 6, the reset pulse 34 is applied to the floating diffusion layer region 6 via the reset gate electrode 7 at time to, t3 preceding the release time 11.14. If is charged to the same potential as 8, the release of the signal charge to 6 will partially discharge the charged charge of 6.

Further, the floating diffusion layer 6 is applied with a reset pulse at time t.

, t3 are insulated from the external circuit, so t1
The potential is held from time t3 to time t4 and from time t4 to t6.

Since the amount of discharge is equal to the signal charge, the potential of 6 becomes equal to the transfer charge signal train, as shown in the output signal waveform 35.

According to this operation, charges from a set of charge transfer paths are alternately detected as an output signal.

Next, a description will be given of means for alternately injecting charges into the set of charge transfer paths.

As mentioned above, the negative direction pulse 33 is applied to the input diffusion layer 1.
is supplied.

It is undesirable for the peak value of the pulse to be negative because it forward biases the pn junction.

A preferable waveform of the pulse is a negative direction pulse in which a positive voltage of 100 or more is the peak value of the pulse groups 31 and 32 at times other than times t2 and t5, and a positive voltage close to 0 volts at times t2 and t5. It is a waveform.

The second input gate electrode has means for being DC biased by an external DC power source.

Preferably, the bias value is a positive voltage value of 7, which is the peak value of the pulse groups 31 and 32.

The first input gate electrode has means connected to an input signal source for emitting a delayed signal.

The maximum value of the delayed signal voltage needs to be the DC bias value of the second input gate electrode, and the minimum value needs to be O volts.

Note that when bias charges are injected when operating the device as an imaging device, the first input gate electrode must be biased with DC bias.

Such a bias value is determined according to the required amount of bias charge.

During the time from time t0 to t2, 33 is a positive voltage value,
Since 34 is O volt, the input diffusion layer 1 is strongly reverse biased, and on the other hand, a large potential barrier is formed on the substrate surface under the third input gate electrode 4 against transferred charges.

Next, at time t2, when the input diffusion layer 1 is weakly reverse biased, a large amount of charge (electrons in this case) in the diffusion layer passes under the first input gate electrode and 2
It reaches below the input gate electrode.

The amount of charge in such a case does not depend on the voltage applied to the first input gate electrode, but depends on the potential of the diffusion layer 1.

Immediately after time t2, when the voltage of the pulse 33 returns to a large positive voltage, part of the charge localized under the second input gate electrode passes under the first input gate electrode and returns to region 1. .

However, in such a case, all the charges do not return to 1, and the return of charges is in a state where the surface potential under the first input gate electrode and the surface potential under the second input gate electrode are equal to each other. will be stopped.

As a result, an amount of charge corresponding to the voltage applied to the first input gate electrode is left behind under the second input gate electrode.

Note that it is clear that the amount of charge decreases as the voltage applied to the first input gate electrode increases, and becomes O when the voltage is higher than the voltage applied to the second input gate electrode.

Next, at time t3, the pulse 34 is applied to the third input gate electrode 4, so the potential barrier disappears and the local charge is guided below the transfer electrode 11 to which the first phase pulse is applied. .

Note that at this time, the second phase pulse 32 applied to the electrode 11' is 0 volts, so no potential well for receiving charges is formed on the substrate surface, and the localized charges are 11'.
There is no flow downward.

After time t3, a potential barrier is formed again under the third input gate electrode 11, preventing the reverse flow of charges from directly below 11, and at the same time electrically insulating the region under the second input gate electrode 3.

At time t5, charge is again injected from 1 to 3 below, and at time t6, charge is injected via 4 below to transfer electrode 11' to which the second phase pulse 32 is applied.

Following the above operation, the charge from the input diffusion layer 1 is transferred to the third
Input gate electrode 4 injects alternately into transfer electrodes 11 and 11'.

As shown in FIG. 1, in order to efficiently accomplish this operation, the second input gate electrode 3, the first transfer electrode 1
1.11' area as other transfer electrodes 12.13,...
It is preferable to make the area twice the area of 12', 13', . . . .

Of course, the area of 11.11' is 12.13...,12'
, 13'..., 1 1 . 1
Although it is possible to set only the peak value of the pulse applied to 1' to twice the peak value of the other pulses, this is not preferable because the number of pulsers increases.

The present invention has been described in detail based on one embodiment.

According to the present invention, since it is possible to supply pulses of the same waveform to the third input gate electrode and the reset gate electrode by one pulser, the peripheral circuit becomes simple, and at the same time, the two electrodes can be connected to the third input gate electrode and the reset gate electrode on the semiconductor substrate. This has the great advantage of reducing the number of pins on the package.

Particularly, the latter advantage is that when the present invention is applied to a surventine structure charge-coupled device, the input/output parts of the rightward charge transfer column and the leftward charge transfer column are close to each other, making wiring easier. It is clear that this will happen.

In addition, a group of photoelectric conversion elements is provided in the middle of a set of charge transfer columns in FIG. It is clear that the present invention can be applied to a solid-state image pickup device that is transported without any modification.

In this structure, when sending charges from the photoelectric conversion element to the upper and lower transfer columns, 31. It is necessary to pause 32 pulses.

During this stop period, the reset gate electrode and the third
The common pulse to the input gate electrode may be stopped or may be continuously supplied.

That is, the present invention does not depend on intermittent pulse trains.

In this specification, for the sake of convenience, only one embodiment has been described; however, other structures such as three-phase, four-phase, pseudo-two-phase, pseudo-single-phase drive charge-coupled devices, and multiple rows of charge transfer paths are also possible. It is clear from the description of the specification that the present invention can be widely applied to a multi-break structure constructed from the above.

[Brief explanation of drawings]

FIG. 1 is a drawing for explaining one embodiment of the present invention.
are the input diffusion layers, 2, 3.4 are the first, second, and third layers, respectively.
Input gate electrodes, 11, 12, 13...18, 1
9, 11', 12', . . . 18', 19' are transfer electrode groups, 5 is an output gate electrode, 6 is a floating diffusion layer, 7 is a reset gate electrode, 8 is a diffusion layer, and 9 is a MOSFET. FIG. 2 is a time chart of voltage waveforms at various parts for explaining the operation of the embodiment shown in FIG. In the figure, 31 and 32 are transfer pulses, 33 is an application pulse to 1, 34 is a common supply pulse to 4 and 7,
35 is an output signal waveform.

Claims (1)

[Claims] 1 A plurality of charge transfer column groups arranged in parallel, a single charge detection floating diffusion layer provided at one end of the transfer column group, and charging the diffusion layer at a constant cycle via a reset gate electrode. a means for detecting the potential of the diffusion layer, a single charge injection diffusion layer provided at the other end of the transfer column group, a first input gate electrode, and a second input having a DC bias means. In a charge-coupled device comprising a gate electrode and a third input gate electrode that functions to sequentially inject charges under the first transfer electrode constituting the transfer column group, the reset gate electrode and the third input gate electrode 1. A driving method for the charge transfer device, characterized in that a common pulse train is applied to three input gate electrodes.