JPS6370453A - Charge accumulating device - Google Patents

Abstract

PURPOSE:To detect signal charges highly accurately, by detecting the signal charges with floating gates. CONSTITUTION:Floating gates FG1-FGn are arranged in line at the neighboring parts of charge transfer elements CD1-CDn. Electrode layers, which are kept at specified potentials, are laminated at positions facing a substrate with respect to the floating gates FG1-FGn. Then, the potentials of the floating gates FG1-FGn are changed by control elements M1-Mn, which are provided at the floating gates FG1-FGn. Thus, the depths of potential wells in the substrate are controlled. The signal charges from the transfer elements CD1-CDn are sent and received. The changes in capacitances corresponding to the amounts of the signal charges are detected by the floating gates FG1-FGn. In this way, the signal charges can be detected by a non-destructive way, and the highly accurate detection can be performed.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention is based on 'T! The present invention relates to a 1ri1 transfer device, and particularly to a charge transfer device equipped with an output mechanism for detecting signal charges using a floating gate.

(Conventional example) Conventionally, as a signal charge detection means in a charge transfer device (hereinafter referred to as COD), an F D shown in FIG.
A (floating diffusion amp
lfier) method. This forms a floating diffusion FD next to the transfer element of the COD via a transform gate OG, and uses the floating diffusion FD as one node and the other diffusion DD as a voltage V. Detection MO connected to
3FET Ma and MO3FET for discharge connected as source follower to floating diffusion FD
Mb is formed.

A reset signal Re5et is applied to the gate of the MO3FET Ma for detection, and the signal charge is transferred to a resistor connected between one node of the MO3FET Ma for discharging and the power supply ■. Voltage V generated in R4
Detected as out.

That is, the detection MOSFETMa is set to the cut-off state, and the floating diffusion FD
■ Power supply. . By supplying the signal charge from the CCD to the floating diffusion FD via the output gate OG and the gate capacitance Co and Cg related to the output gate OG and the gate DG and the depletion layer capacitance of the floating diffusion FD during the cutoff period. The detection signal Vout corresponding to the signal charge can be detected by the gate capacitance seen from Cd and the gate of the discharge MO3FET Mb.

(Problem to be Solved by the Invention) However, in a COD equipped with such an output mechanism, the signal charge is destroyed by detection, and for example, if an appropriate signal charge is detected during transfer, the signal charge is destroyed. After that, there is a drawback that the signal charges cannot be transferred again as they are and other signal processing etc. cannot be performed. If such processing were to be carried out, a device for storing the detected signals would be required, which would result in higher costs or complexity of the device.

(Means for Solving the Problems) In view of the above problems, the present invention provides a charge storage device that non-destructively detects signal charges and is equipped with an output mechanism capable of highly accurate detection. The purpose is to

In order to achieve this object, the present invention provides floating gates that are arranged in parallel adjacent to the charge transfer element, further stacked with an electrode layer held at a predetermined potential at a position facing the substrate of the floating gate, and The floating gate is provided with a control B element that controls the capacitance, and by changing the potential of the floating gate, the control element controls the depth of the potential well in the substrate and transfers signal charges from the transfer element. The technical point is that a potential change corresponding to the amount of signal charge is detected by a floating gate.

(Embodiment) Hereinafter, one embodiment of the charge storage device according to the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment in which an image sensor is formed by providing a photoelectric conversion element in a charge storage device that is the basis of the present invention.

First, the configurations of the CCD section and output section, which correspond to the basic parts of the present invention, will be explained. The CCD section is a CC in which a plurality of charge transfer elements (CDI-CD) are formed in series in the horizontal direction.
D, and the respective charge transfer elements CD1 to CD, ,
is the 4-phase lock signal φ1. by the 4-phase transfer force formula. φ2. φ
The signal charges are transferred horizontally in synchronization with φ4. The output section is connected to each charge transfer element CD + ~CD,l
Floating gates FC and -FC are formed adjacent to the charge transfer element. Each floating gate FG1~FG
, , are field effect transistors (hereinafter referred to as MOSFETs) Tr, -Tr for impedance conversion by wiring.
n and each M connected as a source follower
The source terminals of OS FETTr + ~Trn are connected to output terminals q, ~q7. Moreover, between terminal 1 and each floating gate FGI-FG,
MOSFETs M, .about.M1 for capacitance control, which are controlled by an enable signal CE from the terminal 2, are provided.

In addition to the above basic circuit, adjacent to each charge transfer element CD, to CD of the CCD section, a storage section is connected via a transfer gate TG, and a photoelectric conversion section is connected via a BA. It is set up. The photoelectric conversion section includes photoelectric conversion elements P D + -PD such as photodiodes, which perform charge transfer.

~CD, are formed in the horizontal direction in equal numbers, and the storage sections are connected to the transfer elements CD1~CD, by the control signal STS.
, consisting of electrodes that form a shallower potential well.

Therefore, the signal charges generated in the photoelectric conversion elements PD+ to PDi pass through the barrier gate BA-t-, apply a voltage to the storage gate ST, and form a potential well in the storage element ST+ to ST. S T
+ ~ST, and then the first transfer gate TG is made conductive with the control signal φT, and the signal charge of the storage element ST + ~5Tll is transferred to the CCD.
Charge transfer in the section) CD, to CD, 1 are transferred in parallel.

The circuit configuration shown in FIG. 1 will be further explained in detail based on FIGS. 2 and 3. FIG. 2 is a surface view showing a part of FIG. 1 in a layout configuration based on semiconductor integrated circuit technology, and FIG. 3 is a longitudinal cross-sectional view schematically showing a cross section taken along the line X--X in FIG.

In FIGS. 2 and 3, a plurality of N-type layers are formed in a part of a P-type nucleic acid Q (P-well) formed on the surface of an N-type semiconductor substrate, resulting in a photoelectric conversion element PDI-P.
D, is configured. Furthermore, 5iO on the semiconductor substrate
xli (not shown), barrier gate BA,
Storage element ST, ~ST1, transfer gate TG,
Gate electrode layer 3 of each of transfer elements CD, ~CD,
, 4, 5.6 are arranged in parallel, and a floating gate N7 forming floating gates FG1 to FG9 and a power supply voltage (2). An electrode layer 8 is laminated to be clamped. Note that the gate 1 bottle j13, 4.5° 6 and the floating gate layer 7 in FIG. 3 are shown corresponding to the first element and the floating gate FG i.

One end of each of the floating gates FCI to FG is connected to the MOSFETTr shown in FIG. 1 via a contact, respectively.
Wirings 6i, i, etc. connected to +A-Trn are formed, and transistors corresponding to MOSFETs M, -M, l are formed.

Next, the operation of the charge transfer device having such a configuration will be explained with reference to the timing chart of FIG. 4.

First, when the clock signal φ1 is set to "H" level during the period from time t1 to t3, a potential well is formed under the gate electrode to which the clock signal φ is applied.
It is possible to transfer the signal charges of the storage elements ST, to ST7 to the charge transfer elements CD, to CD. Also, the control signal CE is “H” within the period from time t1 to time t.
” level, and the MSFETs M, -M, are not conductive and the floating gates FG + ~F
G, , is the "L" level reset signal φ1. is applied, and the unnecessary charges of the floating gates) FC, ~FG, 1 are recombined. Furthermore, after the floating gate drive signal φ becomes "H" level at time t8, at time t
Since the control signal CE is inverted to "L" level a little before , the floating game ) FC, ~ at time t.
The potential of FG is held at the power supply voltage v0°.

Next, when the 4-phase low frequency signals φ, ~φ4 are applied according to the 4-phase drive method until time t4, signal charges are moved within the respective charge transfer units CD, ~CD, and at time t4. At this point, signal charges move to the potential well to which the clock signal φ4 is applied. Here, since the floating gate (FGI-FC) is held at the power supply voltage, the clock signal φ, ~
Due to φ4, the signal charge is transferred to the floating gate FC.

Moved under FC. The movement of the signal charge toward the floating gates FC, -FC starts with the application of the clock signal φ, and is completed with the clock signal φ4.

As a result, the floating game FF G + ~
The potential of FG7 changes according to the amount of each signal charge, and the output terminal ql-Q outputs a signal ■ as a voltage drop △■ corresponding to the amount of each signal charge. .

occurs.

That is, to describe the principle of each floating gate, for example, the capacitance between the electrode layer 8 and the floating gate layer 7 shown in FIG. 3 is Co, the capacitance between the floating date layer 7 and the substrate is Cox, and the depletion layer capacitance of the potential well is cd, and if the signal charge amount is Qi, it becomes Cox.

At this time, floating game) FC, ~FG.

Since it simply floats on the substrate, the signal charge is held without any electrical influence.

Next, at time t, reset signal φF6 is set to “L”.
level, and then at time t, the control i11 signal CE is set to the ``H'' level.

When ~M7 is made conductive, the floating gates FC and ~FG are biased to the 'L3 level, so that the potential well becomes shallow as shown in FIG. ,
Moved to l. And time t.

Thereafter, by repeating the same operation from time t to t4, the signal charges transferred for each charge transfer element are detected from the output terminals q, to q.

As described above, according to this embodiment, by using the floating gate, signal charges in arbitrary charge transfer elements can be detected in parallel and non-destructively. In addition, as in this example, surface type CC
By using D (SCCD), almost no settling time (signal charge sweeping time) is required, and the load on the circuit for controlling the operation is reduced. Furthermore, since processes such as ion implantation are not required in the semiconductor manufacturing process, the manufacturing process is simplified. Further, since the electrode g43 stacked on the floating gate is maintained at the power supply voltage, the structure has an excellent S/N ratio. Furthermore, in the conventional structure, a floating gate is interposed between the gate electrode layer and the substrate for forming each charge transfer element of the COD, but in such a conventional structure, the clock signal φ.

~ Affected by cuff pulling noise etc. due to φ4,
In this embodiment, since a floating gate is provided adjacent to the CCD and the electrode layer 8 is opposed to it, signal charges can be detected with high precision without being affected by such noise.

Although this embodiment shows the case where a floating gate is provided in a surface type CCD, the floating gate of the present invention can also be used in a BCCD (buried type COD).

(Effects of the Invention) As explained above, according to the present invention, floating gates are arranged in parallel adjacent to charge transfer elements, and a voltage tx The floating gate is provided with a control element that controls the capacitance, and the control element changes the potential of the floating gate to control the depth of the potential well in the substrate and transfer the signal charge from the transfer element. Since the floating gate transfers and receives the signal charge and detects a change in the capacity corresponding to the amount of signal charge using the floating gate, the signal charge can be detected non-destructively. Furthermore, the electrode layer laminated on the floating gate can improve the S/N ratio and the signal charge to detection signal linearity, making it possible to perform highly accurate detection.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a charge storage device according to the present invention, FIG. 2 is a surface diagram showing a part of FIG. 1 in a layout configuration based on a semiconductor integrated circuit waveform, and FIG. is a cross-sectional view schematically showing the structure of the x-x vA cross section in FIG. 2, FIG. 4 is a timing chart for explaining the operation of the embodiment shown in FIG. 1, and FIG. 5 is a conventional It is a cross-sectional view showing an example of a charge storage device. CD, ~CD, l: Charge transfer element FGI-FG
, :Floating gate M, ~M, :MO
SFET (control element) 8: electrode layer

Claims (1)

[Scope of Claim] A charge storage device that transfers signal charges by a charge transfer element, comprising: a floating gate provided adjacent to the charge transfer element; and a control element that controls the capacitance by applying a predetermined voltage to the floating gate and controls the depth of the potential well in the semiconductor substrate, and the floating gate controls the signal charge A charge storage device that detects.