JP2604905B2 - Solid-state imaging device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device, and more particularly, to a structure of a charge input device of a charge coupled device (hereinafter, referred to as a CCD).

[Conventional technology]

In general, a linear image sensor adopts a method of reading out signal charges of a plurality of light receiving elements arranged one-dimensionally using a single CCD. In recent years, the demand for higher resolution has increased, and the number of light receiving elements has tended to increase accordingly.
However, as the number of light receiving elements increases, the number of CCD stages increases, and there are problems such as deterioration of the total transfer efficiency and speeding up of the data rate. The light receiving element is divided and two
A method of reading a signal with a book CCD has been considered.

In FIG. 10, reference numeral 3 denotes a semiconductor substrate, on which a plurality of photodiodes (light receiving elements) 4 constituting a photoelectric conversion unit are formed in a line, and
Two CCDs 5 are formed in parallel with the arrangement of the photodiodes 4. Also, each photodiode 4 and
Transfer gates 6 are individually formed between the charge transfer sections of the CCD 5, and the signal charges accumulated in the photodiodes 4 are transferred to the CCD 5 when the transfer gates 6 are turned on. An output amplifier 7 is formed at the end of the CCD 5, and the signal charges transferred by the CCD unit 5 are amplified by the output amplifier 7 and output to the outside of the solid-state imaging device chip 1. Reference numeral 2 denotes charge input means provided at the first stage of the CCD 5 so that charges can be electrically injected into the CCD. The electric charge input means 2 electrically injects electric charge from outside into the CCD 5 except when in the imaging mode, and
5, to electrically check the output amplifier 7 and to calibrate them, or to test each transfer electrode constituting the CCD 5 at the stage of manufacturing the CCD 5.

FIG. 11 is a diagram showing the structure of the charge input means 2 in detail, where 10 is a charge input terminal, 8 and 9 are charge input control gates for controlling the amount of charge input from the charge input terminal 10,
11 and 12 are transfer electrodes of CCD5.

Next, the operation in the charge input mode will be described with reference to the drawings.

FIG. 12 (a) is a sectional view taken along the line CC 'in FIG. 11 in the charge input mode.
FIG. 3B shows a cross-sectional view of the portion and its potential, and FIG. 3B shows the waveform of a signal input to each terminal.

Clock pulses I, Φ1, Φ2 are input to the charge input terminal 10 and the signal input terminals of the transfer electrodes 11, 12, respectively, and the DC voltages VGIL, VG are applied to the signal input terminals of the charge input control gates 8, 9, respectively.
IH is applied.

First, at time t1, the charge input terminal 10 and the transfer electrode 12 are set to a high level, and the transfer electrode 11 is set to a low level.

From time t1 to t2, the input signal I of the charge input terminal 10
Changes from a high level to a low level, charges flow from the charge input terminal 10 into the potential wells below the input control gates 8, 9, and at time t3, the charge input terminal 10 goes high again, and the input charge ( Q ₀ ) is accumulated in a potential well below the input control gate 9.

Next, at time t4, “H” is applied to Φ1 and “L” is applied to Φ2, the transfer electrode 11 is at a high level, the transfer electrode 12 is at a low level, and the measured charge (Q ₀ ) is lower than the CCD transfer charge. Flows into the potential well.

 Next, the case of the imaging mode will be described.

FIG. 13 (a) shows the potential in the cross section taken along the line CC 'in FIG. 11 in the imaging mode, and FIG. 13 (b) shows the signal waveform inputted to each terminal.

Clock pulses Φ1 and Φ2 are input to the signal input terminals of the transfer electrodes 11 and 12, respectively, and DC voltages VGIL and VGIH are applied to the signal input terminals of the charge input control gates 8 and 9, respectively.

The transfer gate (TG) 6 is opened between the times t1 and t2, and the signal charges Q ₁ and Q ₂ detected by the light receiving elements 4-1 and 4-2 are placed in the potential wells under the corresponding transfer electrodes 11 respectively. Will be transferred.

Thereafter, at time t3, the signal φ1 of the transfer electrode 11 is set to “H” level, the signal φ2 of the transfer electrode 12 is set to “L” level,
Q ₁ and Q ₂ are transferred into the potential well below the transfer electrode 12 in the next stage. Thereafter, by repeating this, the signal charges are sequentially transferred in synchronization with the clock pulse.

[Problems to be solved by the invention]

Since the charge input unit 2 of the conventional linear image sensor is configured as described above, the light receiving element 4 of the charge input unit 2
There is a problem that the arrangement pitch of is larger than other parts.

That is, for example, assuming that the width of the transfer electrodes 11 and 12 is 8 μm,
The interval between adjacent light receiving elements (for example, 4-1 and 42) (in the figure,
When l1) is designed to be 16 μm, the distance between the light receiving elements 4-1 of the charge input section 2 (l2 in the figure) is such that the width of the charge input terminal is 4 μm and the width of the charge input control gates 8 and 9 is 3 μm each. , 5μ
In the case of m, 31 μm was required.

As described above, when the space of the charge input section 2 is large and the arrangement pitch of the light receiving elements in this section is large, the resolution is significantly reduced in the charge input section 2 and it is not possible to obtain a uniform resolution in the element. .

The present invention has been made in order to solve the above-described problem.When a charge input portion is provided in a first stage portion of a CCD, the arrangement pitch of light receiving elements corresponding to the charge input portion of the CCD is different from that of another portion. It is intended to obtain a solid-state imaging device that is the same as described above.

Further, according to the present invention, when the charge input section is provided in the first stage of the CCD, the arrangement pitch of the light receiving elements corresponding to the charge input section of the CCD can be made equal to that of other parts, and in the charge input mode. It is an object of the present invention to obtain a solid-state imaging device capable of driving the same using a high-precision bias power supply.

[Means for solving the problem]

A solid-state imaging device according to the present invention includes: a semiconductor substrate; a plurality of light receiving elements arranged in a row at a predetermined pitch on one main surface of the semiconductor substrate; and a light receiving element on a side of the row of light receiving elements. A transfer gate for controlling reading of signal charges detected by the light receiving element, which is disposed so that one end of the light receiving element is in contact with each of the elements; A signal charge of the light receiving element is read out by an on operation of the transfer gate, which is disposed so as to be in contact with the other end of the transfer gate corresponding to the element and to be in series contact with each other in the arrangement direction of the light receiving element. Device having a plurality of charge transfer portions for transferring the next charge to the next stage, and a first and a second device for controlling the amount of input charges, which are arranged on the extension of the charge-coupled device so as to be sequentially in contact with each other. And a charge input source disposed in contact with the first electrode for inputting charges from the outside, wherein the second electrode is a first-stage charge transfer unit of the charge-coupled device, and The second electrode is arranged so as to be in contact with the other end of the transfer gate corresponding to the light receiving element located at the start end of the row of light receiving elements, and the second electrode reads out the signal charge of the light receiving element by turning on the transfer gate. And a charge input means for transferring the charge to the charge-coupled device.

Further, a solid-state imaging device according to the present invention includes a semiconductor substrate, a plurality of light receiving elements arranged in a plurality of rows on one main surface of the semiconductor substrate, and a plurality of light receiving elements beside the light receiving elements in each row. A transfer gate for controlling the reading of the signal charge detected by the light receiving element, the transfer gate being provided so that one end thereof is in contact with each of the light receiving elements, and the other end of the transfer gate corresponding to each light receiving element in each column , And in series with each other along the direction in which the light receiving elements in each column are arranged. The signal charges of the light receiving elements are read out by the ON operation of the transfer gate, and are transferred to the next stage. A plurality of first charge-coupled devices having a plurality of charge transfer portions, and a last-stage charge transfer portion of the first charge-coupled device corresponding to the second and subsequent columns of the column of the light receiving elements. , One the disposed so as to contact each other in series in the direction of arrangement of the first charge-coupled device, the first
A second charge-coupled device having a plurality of charge transfer portions for receiving and transferring the signal charge of the charge-coupled device of the second charge-coupled device to the next stage; A first and a second electrode for controlling the amount of input electric charge, and a first electrode and a second electrode disposed in contact with the first electrode;
It consists of a charge input source for inputting charge from outside,
The second electrode is a first-stage charge transfer unit of the second charge-coupled device, and a first electrode corresponding to a first column of the column of the light-receiving devices.
And the second electrode receives the signal charge of the first charge-coupled device and transfers the signal charge to the second charge-coupled device. And charge input means.

Further, a solid-state imaging device according to the present invention includes a semiconductor substrate, a plurality of light receiving elements arranged in a row at a predetermined pitch on one main surface of the semiconductor substrate, and a plurality of light receiving elements beside the row of light receiving elements. A transfer gate for controlling the reading of the signal charge detected by the light receiving element, the transfer gate being disposed so that one end thereof is in contact with each of the light receiving elements; A signal charge of the light receiving element is turned on by the transfer gate being in contact with the other end of the transfer gate corresponding to the light receiving element to be connected, and being arranged in contact with each other in series along the arrangement direction of the light receiving element. A charge-coupled device having a plurality of charge transfer sections for reading and transferring the read-out signal to the next stage; and a charge-coupled device for controlling the amount of input charge, which is disposed on the extension of the charge-coupled device so as to be sequentially in contact with each other. The first electrode includes a first electrode to a third electrode, and a charge input source arranged to be in contact with a side of the first electrode opposite to the light receiving element for inputting charge from outside. The third electrode is arranged to be in contact with the other end of the transfer gate corresponding to the first stage charge transfer section of the charge coupled device and the light receiving element located at the start end of the columnar light receiving element, respectively, and the third electrode is connected to the transfer gate. Charge input means for reading out the signal charge of the light receiving element by the ON operation of the element and transferring the signal charge to the charge coupled element.

Further, a solid-state imaging device according to the present invention includes a semiconductor substrate, a plurality of light receiving elements arranged in a plurality of rows on one main surface of the semiconductor substrate, and a plurality of light receiving elements beside the light receiving elements in each row. A transfer gate for controlling the reading of the signal charge detected by the light receiving element, the transfer gate being provided so that one end thereof is in contact with each of the light receiving elements, and the other end of the transfer gate corresponding to each light receiving element in each column , And in series with each other along the direction in which the light receiving elements in each column are arranged. The signal charges of the light receiving elements are read out by the ON operation of the transfer gate, and are transferred to the next stage. A plurality of first charge-coupled devices having a plurality of charge transfer portions, and a last-stage charge transfer portion of the first charge-coupled device corresponding to the second and subsequent columns of the column of the light receiving elements. , One the disposed so as to contact each other in series in the direction of arrangement of the first charge-coupled device, the first
A second charge-coupled device having a plurality of charge transfer portions for receiving and transferring the signal charge of the charge-coupled device of the second charge-coupled device to the next stage; A first to a third electrode for controlling the amount of input electric charge, and an electric charge input from the outside which is disposed in contact with the first electrode on the side opposite to the light receiving element. A charge input source, wherein the third electrode is provided at the first stage of the second charge-coupled device, and at the last stage of the first charge-coupled device corresponding to the first column of the light receiving device. Charge input means arranged to be in contact with the charge transfer portions, respectively, and the third electrode is for receiving a signal charge of the first charge-coupled device and transferring the signal charge to the second charge-coupled device; It is provided with.

[Action]

In the present invention, the charge-coupled devices are arranged so as to correspond to the light-receiving devices located at the second and subsequent positions from the start end of the light-receiving devices arranged in a row at a predetermined pitch, and the charge input means extends on the extension of the charge-coupled devices. A charge input source, a first electrode, and a second electrode are arranged so as to be sequentially in contact with each other, and the second electrode is in contact with a first-stage charge transfer portion of the charge-coupled device, and the row-shaped light-receiving elements Is arranged so as to be in contact with the light receiving element located at the start end of the second electrode via the transfer gate. By changing the signal applied to the second electrode into a DC voltage and a clock pulse, the second electrode is changed to the input charge amount in the charge mode. In the imaging mode, it can operate as the first-stage charge transfer section of the charge-coupled device, and reads the signal charge of the light-receiving device located at the start end of the light-receiving device arranged in a row. The number of electrodes existing between the electrode for transferring the charge and the charge input source is reduced by one from the conventional one to one, and the charge input means is provided at the first stage of the charge coupled device without changing the arrangement pitch of the light receiving elements. Can be provided.

Also, in the present invention, the charge-coupled devices are arranged so as to correspond to the light-receiving devices located at the second and subsequent positions from the start end of the light-receiving devices arranged in a row at a predetermined pitch, and The first to third electrodes are arranged so as to be sequentially in contact with each other, the charge input source is arranged so as to be in contact with the side of the first electrode opposite to the light receiving element, and the third electrode is connected to the first stage of the charge-coupled device. Since it is arranged so as to be in contact with the charge transfer section and to be in contact with the light receiving element located at the start end of the column-shaped light receiving element via the transfer gate, the clock pulse is always applied to the third electrode, so that in the charge input mode, this is applied. In the operation mode, it can be operated as the first-stage charge transfer section of the charge-coupled device as an electrode for transferring the measured charge, and a high-precision bias power supply is used for the first and second electrodes. Since bets can, be a measurement of the input charge amount with high accuracy, Further, since the arrangement to pull outwardly a charge input source from the extension of the charge-coupled device,
Since the extension space of the charge coupled device is saved by the charge input source, the charge input means can be provided at the first stage of the charge coupled device without changing the arrangement pitch of the light receiving elements.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration of a solid-state imaging device according to a first embodiment of the present invention. A charge input means is provided at a central portion, and two CCDs are arranged in series on both sides thereof. In the figure, reference numeral 4 denotes a photoelectric conversion unit, and a plurality of light receiving elements 4-1, 4-2, 4-3,
4-4... 5 is a CCD for sequentially transferring the signal charges detected by the photoelectric conversion unit 4, 6 is a transfer gate for sending the signal charges detected by the photoelectric conversion unit 4 to the CCD 5 by its ON operation, and 10 is an electric charge to the CCD 5 from outside. Charge input terminals for injection, 11 and 12 are transfer electrodes of the CCD 5, Φ1 and Φ2 are input signals of the transfer electrodes 11 and 12, respectively, and 13 is a first charge input for controlling charges input from the charge input terminal 10. The control gate 14 is a dual-purpose gate having both functions of the second charge input control gate and the first-stage transfer electrode. The control gate 14 functions as the second input control gate in the charge input mode, and is the same as the transfer electrode 11 in the imaging mode. It works as a transfer gate.

Next, the operation will be described separately for the imaging mode of the charge input mode.

First, the case of the charge input mode will be described. As described above, in the charge input mode, the dual-purpose gate 14 functions as the second charge input control gate together with the first charge input control gate 13, and these are the same as the charge input control gate electrodes 8, 9 shown in the conventional example. Works.

FIG. 2A shows a cross-sectional structure taken along the line AA 'of FIG. 1 and its potential, and FIG. 2B shows a signal waveform inputted to each terminal.

A clock pulse is input to the charge input terminal 10 and the transfer electrodes 11 and 12, and the first charge input control gate 13 and the dual-purpose gate are used.
DC voltage is applied to 14. And this gate 13,14
The amount of the input charge is measured by the voltage difference applied to the, and is controlled to a desired value.

From time t1 becomes t2 and the charge from the charge input terminal 10 flows into the input control gate 13 and the combined gate 14 under the potential wells, charge input terminal 10 to become t3 becomes high level again, input charge Q ₀ which is metered in It is accumulated in a potential well below the dual-purpose gate 14.

Then charge Q ₀ time transfer electrodes 12 and becomes t4 goes high flows into the CCD transfer electrode 12 the potential well beneath.

As described above, charge input can be performed as in the conventional case.

 Next, the case of the imaging mode will be described.

In this case, a clock pulse having the same phase as that of the transfer electrode 11 is input to the dual-purpose gate 14, and a DC voltage is applied to the charge input control gate 13.

FIG. 3 (a) is a sectional view taken along the line AA 'of FIG. 1 and a diagram showing its potential, and FIG. 3 (b) shows a signal waveform inputted to each terminal.

Transfer gate TG12 opens between time t1 and t2,
The signal charges Q ₁ and Q ₂ of the light receiving elements 4-1 and 4-2 are transferred to the potential wells below the shared electrode 14 and the transfer electrode 11, respectively. Thereafter, the transfer electrodes 11 by applying a clock pulse, the combined electrode 14 low, the transfer electrode 12 as a high level, transfers the signal charge to Q ₁ under the combined electrode 14 below the transfer electrodes 12, transfer electrodes 11 below transferring charge Q ₂ to the potential well under the next stage transfer electrode. With such an operation, the signal charges are sequentially transferred in synchronization with the clock pulse, and the same operation as the conventional image sensor is performed.

In the present embodiment as described above, the second control for controlling the input charge amount is performed.
And the first-stage transfer electrode for transferring the signal charges are formed by the same electrode 14, so that the arrangement pitch of the light receiving elements of the charge input section is as follows with the conventional reference design.

That is, as in the conventional case, when the width of the transfer electrodes 11 and 12 is 8 μm and the interval between adjacent light receiving elements other than the charge input portion (11 in the drawing) is 16 μm, the charge input terminal 10 4 μm width, charge input control gate 13 and dual purpose gate 14
Are 3.5 μm and 5 μm, respectively, so that the distance between the light receiving elements 4-1 of the charge input section 2 (l2 in the figure) can also be formed to 16 μm.

Therefore, in the present embodiment, the space of the charge input section 2 can be reduced without changing the scale of the charge input terminal and the charge input control gate substantially from the conventional one, and the arrangement pitch of the light receiving elements corresponding to the charge input section can be reduced. Can be the same as the arrangement pitch of the light receiving elements in the portion.

As described above, according to the present embodiment, the charge input control electrode and the transfer electrode are configured by the same electrode 14,
By changing the input signal to be added thereto, this is operated as the second charge input control electrode in the charge input mode, and is operated as the transfer electrode in the imaging mode. Therefore, the space of the charge input section 2 can be reduced, and the charge can be reduced. Since the arrangement pitch of the light receiving elements in the portion corresponding to the input section can be made the same as the arrangement pitch of the light receiving elements in the other portions, the pattern design becomes extremely easy. Also, since there is no reduction in resolution at the charge input section, a uniform resolution can be obtained within the chip.

In the above embodiment, a one-dimensional solid-state imaging device has been described. However, the present invention is not limited to this, and is naturally applicable to a two-dimensional solid-state imaging device.

That is, FIG. 4 shows the configuration of the charge input section 2 of the above embodiment as 2
It is applied to horizontal CCD of three-dimensional solid-state imaging device,
FIG. 3A is an overall view thereof, and FIG. 3B is a view showing the vicinity of the charge input section in FIG. 3A in detail. In the figure, 1 is a solid-state image sensor chip, 2 is a charge input means, and 5a is a vertical CC.
D and 5b are horizontal CCDs, 6 is a transfer gate, 4 is a photoelectric conversion element, and the configuration of the charge input unit 2 is the same as that of the above embodiment except that the shared gate 14 is connected to the output terminal of the vertical CCD 5a. It is exactly the same as that shown in FIG.

In this configuration, the two-dimensional solid-state imaging device is divided at the center,
The signal charge detected by the light receiving element 4 is transferred to a transfer gate 6
And the signal charges transferred from the vertical CCD 5a are simultaneously read out by the two horizontal CCDs 5b.

Also in such a configuration, a dual-purpose gate 14 is provided in the charge input section 2 of the horizontal CCD 5b, and a direct-current voltage is applied to the charge input mode in the charge input mode to operate as a charge input control gate. It is preferable to operate as a transfer electrode by applying a clock pulse synchronized with 11, and as in the above embodiment, the space of the charge input section 2 can be reduced, and the arrangement pitch of the light receiving elements corresponding to this section can be reduced. The arrangement pitch of the light receiving elements corresponding to the above can be made the same, and a decrease in resolution due to the provision of the charge input section can be prevented.

FIG. 5 shows another configuration example of the two-dimensional solid-state imaging device. FIG. 5 shows a structure in which the two-dimensional image pickup device of FIG. 4 is further symmetrically provided on the upper part. Even in such a configuration, if the configuration of the charge input section 2 is the same as that of the above-described embodiment, all the light receiving elements 4 can be arranged at the same pitch without changing the arrangement pitch of the light receiving elements 4 and pattern formation. Is extremely easy, and the uniformity of the resolution within the chip can be achieved.

FIG. 6 shows the configuration of a solid-state imaging device according to a second embodiment of the present invention, and the configuration of the charge input section is different from that of the above-described embodiment of FIG.

In the figure, the same reference numerals as those in FIG.
Reference numerals 1 and 72 denote first and second charge input control gates for controlling the amount of charge input from the charge input terminal 10, and 73 serves as a third charge input control gate and is measured by the charge input control gates 71 and 72. It is a dual-purpose gate that transfers electric charges and acts as a first-stage transfer electrode, temporarily stores signal electric charges of pixels, and performs transfer.

First, the case of the charge input mode will be described. Seventh
FIG. 7A shows the potential of the cross section taken along the line BB 'in FIG. 6, and FIG. 7B shows the waveform diagram of the signal input to each terminal.

Clock pulses I, Φ1, Φ2, Φ2F are input to the charge input terminal 10, the transfer electrodes 11, 12, and the shared gate 73, respectively, and DC voltages VGIL, VGIH are applied to the charge input control gates 71, 72, respectively.

First, at time t1, a high-level signal is input to the charge input terminal 10 and the transfer electrode 11, and a low-level signal is input to the signal input terminals of the transfer electrode 12 and the shared gate 73.

From time t1 to t2, the level of the charge input terminal 10 decreases, and charges are transferred from the charge input terminal 10 to the input control gates 71 and 72.
It flows into the lower potential well.

Further, at time t3, the charge input terminal 10 goes high again, and the measured input charge (Q ₀ ) is stored only in the potential well below the input control gate 72.

Next, at time t4, the dual-purpose gate 73 becomes high level, and the charge (Q ₀ ) is transferred into the potential well below the CCD transfer electrode 11.

 Next, the case of the imaging mode will be described.

In this case, a clock pulse having the same phase as that of the transfer electrode 12 is input to the dual-purpose gate 73, and a DC voltage is applied to the charge input control gates 71 and 72 in advance.

FIG. 8A is a sectional view taken along the line BB 'in FIG. 6 and a diagram showing its potential, and FIG. 8B shows a signal waveform inputted to each terminal.

Transfer gate TG6 opens between time t1 and t2,
The signal charges Q ₁ and Q ₂ of the light receiving elements 4-1 and 4-2 are transferred into the potential wells below the shared electrode 73 and the transfer electrode 12, respectively.

Thereafter, at time t3, the transfer electrodes 12 by applying a clock pulse, low level shared electrodes 73, transfer electrodes 11 as a high level, transfers the signal charge to Q ₁ under the combined electrode 73 below the transfer electrodes 11, transferring the transfer electrodes 12 charges Q ₂ under the next stage of the transfer electrode 11 in the potential well under.

At time t4, the transfer electrode 12 and the dual-purpose electrode 73 are at a high level, the transfer electrode 11 is at a low level, and the signal charge Q ₁ Q ₂ under the transfer electrode 11 is transferred into a potential well under the next-stage transfer electrode 12. Is done.

With such an operation, the signal charges are sequentially transferred in synchronization with the clock pulse, and the signal detected by the light receiving element 4 is read out.

The arrangement pitch of the light receiving elements of the charge input section in this embodiment is as follows.

That is, as in the conventional case, when the width of the transfer electrodes 11 and 12 is 8 μm and the pitch of the light receiving elements other than the charge input section is 16 μm, for example, the width of the charge input terminal 10 is 4 μm and the charge input control gate 71 , 72 are set to 3.5 μm and 5 μm, respectively, and the width of the dual-purpose gate 73 is set to 5 μm, the interval between the light receiving elements 4-1 corresponding to the charge input section becomes 16 μm as in the above embodiment, and the charge input section Can be made the same as the arrangement pitch of the light receiving elements in the other portions.

Here, in the first embodiment, in the imaging mode, this operates as the first-stage transfer electrode, and in the charge input mode, it operates as the second charge input control gate. It was necessary to apply a pulse and apply a DC voltage in the charge input mode. For this reason, a clock pulse source is always connected to the dual-purpose gate 14, and a constant bias is generated using the clock pulse source when a DC voltage is applied. Therefore, it is difficult to increase the accuracy as a bias source.

On the other hand, in the second embodiment, one gate is further added as a third input charge control gate to the structure of the charge input section 2 of the first embodiment, so that the gate can be used in both the charge input mode and the drive mode. Since the dual-purpose gate 73 is configured to be driven only by the clock pulse, only the DC bias can be applied to the first and second charge input control gates 71 and 72 at all times. Input control gate 71, 72
Can be provided with a capacitor for stabilizing the potential, and a highly accurate bias source can be formed.

Further, in the second embodiment, the space of the charge input section 2 is increased by the addition of the dual-purpose gate 73.
Charge input terminal 10 so that the space becomes equivalent to that of the embodiment of FIG.
Is drawn out of the CCD5. Therefore, in this embodiment, similarly to the above-described embodiment, it is possible to provide the CCD with charge input means while maintaining the arrangement pitch and resolution of the light receiving elements uniformly within the chip.

That is, in this embodiment, in addition to the effect of the configuration of the first embodiment, there is no need to switch the signal in the dual-purpose gate, and there is an effect that a stable bias source can be formed in the charge input control gate.

Although the one-dimensional solid-state imaging device is described in the above embodiment, the configuration of the present invention is also applicable to a two-dimensional solid-state imaging device as described in the first embodiment. That is, FIG. 9 shows an embodiment in which the present invention is applied to a two-dimensional solid-state imaging device, and FIG.
FIG. 2B shows the details of the configuration of the charge input section shown in FIG. Also in this case, it is possible to provide the charge input means 2 in the first stage of the horizontal CCD 5b without changing the arrangement pitch of the light receiving elements, while keeping the specified design standard.

〔The invention's effect〕

As described above, according to the present invention, the charge-coupled devices are arranged so as to correspond to the light-receiving devices located at the second and subsequent positions from the start end of the light-receiving devices arranged in a row at a predetermined pitch, and A charge input source, a first electrode, and a second electrode constituting a charge input means are arranged on the extension so as to be sequentially in contact with each other, and the second electrode is in contact with a first-stage charge transfer section of the charge-coupled device. Since it is arranged so as to be in contact with the light receiving element located at the start end of the row of light receiving elements via a transfer gate, a signal applied to the second electrode is a DC voltage,
By changing to a clock pulse, the second electrode is
In the charge mode, it can be operated as an electrode for controlling the amount of input charge, and in the imaging mode, it can be operated as a first-stage charge transfer section of the charge-coupled device. The number of electrodes existing between the electrode for reading and transferring this and the charge input source is reduced by one from the conventional one to one, and the charge input means is provided at the first stage of the charge coupled element without changing the arrangement pitch of the light receiving elements. Thus, there is an effect that a high-performance solid-state imaging device capable of performing an electrical inspection while the charge-coupled device is operating while maintaining uniform resolution is obtained.

Further, according to the present invention, the charge-coupled devices are arranged so as to correspond to the light-receiving devices located at the second and subsequent positions from the start end of the light-receiving devices arranged in a row at a predetermined pitch, and The first to third electrodes are arranged so as to be sequentially in contact with each other, the charge input source is arranged so as to be in contact with the first electrode on the side opposite to the light receiving element, and the third electrode is connected to the first stage of the charge-coupled device. In this case, a clock pulse is always applied to the third electrode so as to be in contact with the charge transfer portion of the column and the light receiving element located at the beginning of the row of light receiving elements via a transfer gate. As an electrode to transfer the measured charge
In the operation mode, the charge-coupled device can be operated as the first-stage charge transfer section, and a high-precision bias power supply can be used for the first and second electrodes, so that the input charge amount can be measured with high accuracy. Is obtained. Further, since the charge input source is disposed so as to be drawn out from the extension of the charge-coupled device, the installation space on the extension of the charge-coupled device can be saved by the amount of the charge input source. A high-performance solid that can provide charge input means at the first stage of the charge-coupled device without changing the arrangement pitch of There is an effect that an imaging device can be obtained.

[Brief description of the drawings]

FIG. 1 is a plan view showing an input section of a one-dimensional solid-state imaging device in a solid-state imaging device according to a first embodiment of the present invention. FIG. 2 is a sectional view taken along the line AA 'of FIG. 1 in a charge input mode. FIG. 3 is a diagram showing a potential and a waveform of a signal input to each terminal, FIG.
FIG. 4 is a diagram showing the potential of the section taken along the line AA 'in FIG. 1 and the waveform of a signal input to each terminal in the imaging mode. FIG. FIG. 5 is a diagram showing an input unit of a two-dimensional solid-state imaging device, FIG. 5 is a diagram showing another example of a two-dimensional solid-state imaging device according to an embodiment of the solid-state imaging device according to the first invention, and FIG. FIG. 7 is a plan view showing an input section of a one-dimensional solid-state imaging device in the solid-state imaging device according to the second embodiment. FIG. 7 is a diagram showing a potential in a section taken along the line BB 'in FIG. FIG. 8 shows a waveform of a signal to be output, and FIG.
FIG. 9 is a diagram showing a potential of a cross section taken along line BB of FIG. 9 and a waveform of a signal input to each terminal. FIG. 9 shows an input unit of a two-dimensional solid-state imaging device in the solid-state imaging device according to the second embodiment of the present invention. FIG. 10, FIG. 10 is a plan view showing a conventional one-dimensional solid-state imaging device, FIG. 11 is a plan view showing the charge input section of FIG. 10 in detail, and FIG. FIG. 13 is a diagram showing potentials and signal waveforms input to respective terminals in the cross-sectional view taken along the line CC ′ in FIG. 11 in the charge input mode. FIG. It is a potential waveform of the C 'sectional view and a signal waveform diagram inputted to each terminal. In the figure, 1 is a solid-state image sensor chip, 2 is a charge input means, 3 is a semiconductor substrate, 4 is a photodiode (light receiving element), 5 is a CCD, 5a is a vertical CCD, 5b is a horizontal CCD, 6 is a transfer gate, 7 is an output amplifier, 10 is a charge input terminal,
11, 12 are transfer electrodes, 13 is a first charge input control gate, 14
Is a shared gate according to the first embodiment, 71 is a first charge input control gate, 72 is a second charge input control gate, and 73 is a second charge input control gate.
Is a dual-purpose gate according to the embodiment. In the drawings, the same reference numerals indicate the same or corresponding parts.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Yoshio Tange 2-4-1 Hamamatsucho, Minato-ku, Tokyo Inside the Space Development Corporation (72) Inventor Yuji Miyaji 2-4-1 Hamamatsucho, Minato-ku, Tokyo Within the Japan Space Development Agency (72) Inventor Tadashi Shiraishi 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Co., Ltd. LSI Research Institute (56) References JP-A-55-163952 (JP, A)

Claims (4)

(57) [Claims] 1. A semiconductor substrate, a plurality of light receiving elements arranged in a row at a predetermined pitch on one principal surface of the semiconductor substrate, and a plurality of light receiving elements beside the row of light receiving elements. A transfer gate for controlling reading of signal charge detected by the light receiving element, which is disposed so that one end thereof is in contact with the light receiving element; The signal charge of the light receiving element is read out by the ON operation of the transfer gate, which is arranged so as to be in contact with the other end of the transfer gate and in series with each other along the arrangement direction of the light receiving element. A charge-coupled device having a plurality of charge transfer portions for transferring, and first and second electrodes for controlling an input charge amount, which are arranged so as to be sequentially in contact with each other on an extension of the charge-coupled device; And said A charge input source arranged to be in contact with one of the electrodes and configured to input a charge from the outside, wherein the second electrode includes a charge transfer portion at a first stage of the charge-coupled device, and the light-receiving device in a row The second electrode is arranged so as to be in contact with the other end of the transfer gate corresponding to the light-receiving element located at the start end of the light-receiving element, and the second electrode reads out the signal charge of the light-receiving element by turning on the transfer gate, and transfers it to the charge-coupled device. A solid-state imaging device, comprising: 2. A semiconductor substrate; a plurality of light receiving elements arranged in a plurality of rows on one principal surface of the semiconductor substrate; and a plurality of light receiving elements beside each of the light receiving elements in each row. A transfer gate for controlling reading of signal charges detected by the light receiving element, the transfer gate being arranged so as to be in contact with one end thereof; and a transfer gate corresponding to each light receiving element in each of the columns, and A plurality of charge transfer units arranged in series with each other along the direction in which the light receiving elements of each column are in contact with each other, and for reading out signal charges of the light receiving elements by the on operation of the transfer gate and transferring the signal charges to the next stage; A plurality of first charge-coupled devices having: a first charge-coupled device, a first charge-coupled device corresponding to the second and subsequent columns of the column of the light-receiving devices, and Charge coupling A second charge-coupled device having a plurality of charge transfer units arranged in series in the arrangement direction of the devices so as to receive the signal charge of the first charge-coupled device and transfer the signal charge to the next stage; And a first and a second electrode for controlling an input charge amount, which are sequentially disposed on the extension of the second charge-coupled device so as to be in contact with each other, and are disposed so as to be in contact with the first electrode. And a charge input source for inputting charge from outside.
The first charge-coupled device of the second charge-coupled device;
And the second electrode is arranged so as to be in contact with the last charge transfer portion of the first charge-coupled device corresponding to the first column of the light-receiving device, and the second electrode is a signal charge of the first charge-coupled device. And a charge input means for transferring the received signal to the second charge-coupled device. 3. A semiconductor substrate, a plurality of light receiving elements arranged in a row at a predetermined pitch on one main surface of the semiconductor substrate, and a plurality of light receiving elements beside the row of light receiving elements. A transfer gate for controlling reading of signal charge detected by the light receiving element, which is disposed so that one end thereof is in contact with the light receiving element; The signal charge of the light receiving element is read out by the ON operation of the transfer gate, which is arranged so as to be in contact with the other end of the transfer gate and in series with each other along the arrangement direction of the light receiving element. A charge-coupled device having a plurality of charge transfer portions for transferring, a first to a third electrode for controlling an input charge amount, which are arranged so as to be sequentially in contact with each other on an extension of the charge-coupled device; And a charge input source arranged to be in contact with the first electrode on the side opposite to the light receiving element, for inputting charges from the outside, wherein the third electrode is a first stage of the charge-coupled device. The third electrode is arranged so as to be in contact with the other end of the transfer gate corresponding to the charge transfer section and the light receiving element located at the starting end of the column of light receiving elements, and the third electrode is turned on by the transfer gate. A charge input means for reading out the signal charges of the above and transferring the signal charges to the charge coupled device. 4. A semiconductor substrate; a plurality of light receiving elements arranged in a plurality of rows on one main surface of the semiconductor substrate; and a light receiving element on each side of the light receiving elements in each row. A transfer gate for controlling reading of signal charges detected by the light receiving element, the transfer gate being arranged so as to be in contact with one end thereof; and a transfer gate corresponding to each light receiving element in each of the columns, and A plurality of charge transfer units arranged in series with each other along the direction in which the light receiving elements of each column are in contact with each other, and for reading out signal charges of the light receiving elements by the on operation of the transfer gate and transferring the signal charges to the next stage; A plurality of first charge-coupled devices having: a first charge-coupled device, a first charge-coupled device corresponding to the second and subsequent columns of the column of the light-receiving devices, and Charge coupling A second charge-coupled device having a plurality of charge transfer units arranged in series in the arrangement direction of the devices so as to receive the signal charge of the first charge-coupled device and transfer the signal charge to the next stage; A first to a third electrode for controlling the amount of input charge, and a light-receiving element of the first electrode, the first and third electrodes being arranged so as to be sequentially in contact with each other on an extension of the second charge-coupled device; A charge input source arranged to be in contact with the opposite side for inputting charges from the outside, wherein the third electrode is a first-stage charge transfer portion of the second charge-coupled device, and the light-receiving device; And the third electrode receives the signal charge of the first charge-coupled device, and receives the signal charge of the first charge-coupled device. For transferring to the second charge-coupled device A solid-state imaging device comprising charge input means.