JP2519482B2 - Charge transfer device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge transfer device, and more particularly to a charge transfer device having a structure capable of improving output characteristics at a transfer end portion.

[Prior Art] FIG. 3 is a block diagram of a solid-state imaging device of an interline transfer system using a charge transfer device.

 The configuration will be described below with reference to the drawings.

A vertical transfer unit 23a formed of a charge coupled device (hereinafter referred to as a CCD) via transfer gates 22a to 22c to photodetection units 21a to 21c formed of photodiodes arranged in 3 columns x 4 rows.
~ 23c is connected. A horizontal transfer unit 25 composed of a CCD is connected to the transfer direction ends of the vertical transfer units 23a to 23c via interface units 24a to 24c, and an output terminal 27 is connected to the transfer direction ends via a preamplifier 26. It

 Next, the operation will be briefly described.

The optical signals input to the photo detectors 21a to 21c are converted into electrical signals there, and read to the vertical transfer units 23a to 23c one after another by turning on the transfer gates 22a to 22c. Vertical transfer unit 23a
To 23c, the signal charges read out are transferred by the charge transfer function and transferred through the interface parts 24a to 24c to the horizontal transfer part.
Read to 25. The signal charges read out to the horizontal transfer unit 25 are further transferred by the charge transfer function, the transfer charges are amplified into an electric signal by the preamplifier 26, and are sequentially taken out from the output terminal 27 as optical input information of the photodetection units 21a to 21c. Of.
Image processing is performed by continuously repeating the cycle of the series of conversion, transfer and output operations.

FIG. 4 is a diagram showing the relation between the cross section along the transfer direction and the potential of the CCD constituting the horizontal transfer portion of FIG. 3, and FIG. 5 shows the clock pulse applied to the transfer electrode. It is a timing chart figure.

The transfer operation of the CCD will be briefly described below with reference to FIGS.

First, in accordance with the clock pulse shown in FIG. 5, among the terminals connected to the transfer electrode 28 of the horizontal transfer section 25, a voltage of "HH" level is applied to φA ₁ and a voltage of "HH" level is applied to φA _{2 to} φA ₄ . When a voltage is applied, the potential well below the transfer electrode of the semiconductor substrate 1 is formed in the state shown at time t ₀ . At this time, the charges transferred by the vertical transfer units 23a to 23c
Q _A , Q _B , and Q _C are transferred to this potential well via the interface units 24a to 24c and temporarily stored. The accumulated charges are sequentially transferred in the direction of the preamplifier 26 by moving the potential well based on the clock pulse as shown at times t _{1 to} t ₃ . Thereafter, the charges transferred from the vertical transfer units 23a to 23c are sequentially transferred to the output side by repeating the same clock pulse.

FIG. 6 is a cross-sectional view showing the configuration around the output section of the horizontal transfer section in FIG. 3, and FIG. 7 is a timing chart diagram showing clock pulses applied to the respective sections.

The configuration and operation will be described below with reference to both drawings.

Transfer electrodes 2 and _{3 to which} terminals φA ₃ and φA ₄ as the final gate of the CCD are connected are formed above the main surface of the semiconductor substrate 1, and impurity regions 14 and 15 are formed on the main surface of the semiconductor substrate 1. It The gate electrode 4 is formed above the region between the region below the transfer electrode 3 and the impurity region 14, while the gate electrode 9 is formed above the region between the impurity region 14 and the impurity region 15.
Are formed to form a reset transistor. Further, a MOS transistor Q whose gate is connected to the impurity region 14 and a load resistor R are connected to form a preamplifier 26, and an output terminal 27 is provided at a contact point between the transistor Q and the load resistor R.
Connect.

In operation, at time t ₀₁ , terminal φA of gate electrode 3
The voltage level of ₄ becomes high level “H”. At this time, the signal charges to be read next are accumulated under the gate electrodes 2 and 3. In addition, the voltage level of the gate electrodes 2 and 3 is "H".
At the same time, the reset level φR becomes “H”, and the potential of the impurity region is set to the level of VR.

And the voltage φ of the gate electrode 9 of the reset transistor
When the level of R changes from “H” to “L”, the impurity region 14
Potential decreases due to capacitive coupling between the transfer electrode 9 and the impurity region 14, and at the same time, the level of the output D ₀ also decreases.

At time t ₀₂ (> t ₀₁ ), the voltage φR of the reset transistor electrode 9 is in the “L” state, and the impurity region 14 is in the floating state. After that, the voltage level of the transfer electrode 3 changes from "H" to "L". At time t ₀₃ (> t ₀₂ ), the voltage level of the transfer electrode 3 is in the “L” state, the signal charges accumulated below the transfer electrode 3 are read out to the impurity region 14, and the level of the output D ₀ is It changes according to the signal amount. That is, the potential change of the impurity region 14 is output to the outside through the preamplifier 26 as a source follower.

[Problems to be Solved by the Invention] In the conventional charge transfer device described above, the configuration around the output section is configured as described above. Where the impurity region
14 or the floating diffusion capacity
If the gain of C _FD and the source follower is G, the number of signal charges N _S
The output voltage V ₀ for V ₀ is V ₀ = G × q × N _S / C _FD . Here, q is the charge of the electron. Therefore V ₀ is
The smaller the C _{FD, the} larger it becomes. However, C _FD is 0.01 to 0.1 pF
It was difficult to make the size smaller than this from the viewpoint of fine processing technology. Therefore, since there is a limit to the reduction of the floating diffusion capacity, there is a problem that a sufficient output cannot be obtained for a minute amount of signal transferred from the charge coupled device.

The present invention has been made to solve the above problems, and provides a charge transfer device capable of amplifying and outputting charges output from a charge coupled device on the same substrate as the charge coupled device. With the goal.

[Means for Solving the Problems] In the charge transfer device according to the present invention, the second charge, which is larger than this charge amount, is separately supplied based on the charge amount of the first charge output from the charge coupled device. Then, it is stored once and then transferred. Based on the transferred amount of the second charge, it is amplified and taken out as an output signal.

[Operation] In the present invention, since the output voltage is taken out based on the second charge amount which is larger than the charge amount of the first charge, a large output signal is secured even if the first charge is very small. It

[Embodiment] FIG. 1 is a diagram showing a configuration around an output portion of a CCD showing an embodiment of the present invention and its relation to a potential, and FIG. 2 shows a clock pulse applied to its gate electrode. It is the timing chart figure shown.

The configuration and operation will be described below with reference to both drawings.

Impurity regions 10, 12, 1 are formed at predetermined positions on the main surface of the semiconductor substrate 1.
3,14,15 are formed. Gate electrodes 2 and _{3 to which} terminals φA ₃ and φA ₄ as the final gate of the CCD are connected are formed above the region on the left side of the impurity region 10, and the region between the region below the transfer electrode 3 and the impurity region 10 is formed. A gate electrode 4 to which a voltage VG ₀ is applied is formed above. Impurity region 10
A gate electrode 5 to which a voltage φR ₁ is applied is formed above the region between the impurity region 12 and the impurity region 12 to form a first reset transistor. Voltages VR ₁ and φI are applied to the impurity regions 12 and 13, respectively, and gate electrodes 6, 7 and 8 are formed above the region between the impurity regions 13 and 14. The gate electrode 6 is connected to the impurity region 10 so that they are always at the same potential, and φS is applied to the gate electrodes 7 and 8, respectively.
A voltage of T, φB is applied. A gate electrode 9 to which a voltage of φR ₂ is applied is formed above the region between the impurity regions 14 and 15, and a voltage of VR ₂ is applied to the impurity region 15 forming a second reset transistor. .

The output circuit uses a MOS between the power supply voltage V ₀ and the ground power supply.
Transistor Q and load resistor R are connected in series, the gate of transistor Q is connected to impurity region 14, and output voltage D ₀ is taken out from the connection point between transistor Q and load resistor R. The configuration of this output circuit is similar to that of the conventional device.

Next, the operation will be described. First, at time T ₁ , φ A ₄ is at “H” level and the signal charge Q _S1 is accumulated in the final gate of the CCD. At the same time, φR ₁ and φR ₂ are at “H” level,
The reset transistor is turned on and the impurity regions 10 and 14 are set to the levels of VR ₁ and VR ₂ , respectively (see FIG. 1 (b)). At time T ₂ , φR ₁ and φR ₂ are at the “L” level, and the impurity regions 10 and 14 are in a floating state (first
See FIG. (C)). At this time, the levels of the impurity regions 10 and 14 are slightly lowered due to capacitive coupling with the gate electrodes 5 and 9. Time T
_{At 3} , φ A ₄ becomes “L” level, the signal charge Q _S1 stored under the gate electrodes 2 and 3 is transferred to the first impurity region 10 over the barrier under the gate electrode 4, and The electric potential is changed (see FIG. 1 (d)). Since the gate electrode 6 is connected to the impurity region 10, it has the same potential change as that of the impurity region 10. Next, at time T ₄ , φI becomes “L” level, and charges are injected from the impurity region 13 serving as the source to the potential well below the gate electrode 7 through the gate electrode 6 (see FIG. 1E). At time T ₅ , φI becomes “H” level, so that the charge Q _S2 remains under the gate electrode 7 as much as the potential under the gate electrode 6 (see FIG. 1 (f)). At time T ₆ , φST becomes “L” level and φB becomes “H” level, so that signal charge Q _S2 under the gate electrode 7
Are transferred to the second impurity region 14, where the impurity region
The potential change occurring at 14 becomes the output voltage D ₀ through the output circuit as in the conventional case and is output to the outside (see FIG. 1 (g)).

Here, the charges transferred to the second impurity region 14 are determined by the area of the gate electrode 7 and the potential difference between the gate electrode 6 and the gate electrode 7, and the potential change of the gate electrode 6 is the first impurity region 10. Since it can be increased by decreasing the capacitance connected to the gate electrode 6, the area of the gate electrode 6 can be made as small as possible and the area of the gate electrode 7 can be made as large as possible to increase the degree of charge amplification.

Further, by appropriately selecting each clock and charge level, it is possible to output a value obtained by subtracting an arbitrary amount as the output voltage.

Although the output circuit using the one-stage source follower is used in the above embodiment, the same applies to the output circuit using the multi-stage source follower, and the detection circuit having another configuration is also applicable. It goes without saying that the same can be applied even if there is.

Further, in the above embodiment, the charge obtained by the potential of the gate electrode connected to the first impurity region is immediately transferred to the second impurity region, but a charge transfer means such as CCD is further inserted between them. Then, it is also possible to take out as an output voltage based on the transferred charges.

With reference to FIG. 1, the first charge injection means of claim 1 sets the gate electrodes 2 and 3 and the first charge storage means sets the impurity region 10 to the first reference potential setting. The second charge storage means is the impurity region 12 and the gate electrode 5, the first charge transfer means is the gate electrode 4, the second charge storage means is the gate electrode 7 and the semiconductor substrate region below the gate electrode 7. The charge injecting means is connected to the impurity region 13, the gate electrode 6, the wiring connecting the impurity region 10 and the gate electrode 6, and the wiring supplying the voltage φI to the impurity region 13, and the third charge storage means is connected to the impurity region 14. The second reference potential setting means is for the gate electrode 9 and the impurity region 15, the second charge transfer means is for the gate electrode 8, and the electric signal output means is for the MOS transistor Q, the load resistor R, and the MOS transistor Q. Wiring for connecting the gate electrode of the gate and the impurity region 14 and the MOS It corresponds to the output terminal connected to the connection point between the transistor Q and the load resistor R.

With reference to FIG. 1, the fourth charge accumulating means and the charge supplying means according to claim 2 are φI and φI, respectively.
To the impurity region 13, the first region is the semiconductor substrate region below the gate electrode 6, and the transfer electrode is
The potential equalizing means for the gate electrode 6 corresponds to a wiring connecting the gate electrode 6 and the impurity region 10.

With reference to FIG. 1, the second region in claim 3 corresponds to the semiconductor substrate region under the gate electrode 7, and the potential well forming means corresponds to the gate electrode 7.

Referring to FIG. 1, the first impurity region corresponds to the impurity region 10, the second impurity region corresponds to the impurity region 14, the third impurity region corresponds to the impurity region 13, and the third impurity region corresponds to the impurity region 10 of claim 4. To do.

With reference to FIG. 1, the first transistor of claim 5 is a first reset transistor (impurity region 1
0, consisting of the impurity region 12 and the gate electrode 5).

With reference to FIG. 1, the second transistor of claim 6 is a second reset transistor (impurity region 1
4, consisting of the impurity region 15 and the gate electrode 9).

With reference to FIG. 1, the third transistor of claim 7 is a MOS transistor Q, and the resistor is a load resistor R.
In addition, the wiring connecting the gate electrode of the third transistor and the second impurity region is a wiring connecting the gate electrode of the MOS transistor Q and the impurity region 14, and the output terminal is a MOS transistor.
It corresponds to the output terminal connected to the connection point of the transistor Q and the load resistor R.

[Effects of the Invention] As described above, according to the present invention, the second charge having a larger charge amount is generated based on the first charge output from the charge coupled device, and the output signal is extracted based on this. There is an effect that it becomes a charge transfer device with high charge detection sensitivity that can take out a large output signal even if the first charge is very small.

[Brief description of drawings]

FIG. 1 is a diagram showing the configuration around the output of a CCD showing one embodiment of the present invention and the relationship with its potential, and FIG. 2 is a timing chart showing the clock pulse applied to the gate electrode of FIG. FIG. 3 is a block diagram of a solid-state image pickup device of an interline transfer system using a general charge transfer device, and FIG. 4 constitutes the horizontal transfer unit of FIG.
FIG. 5 is a diagram showing the relationship between the cross section along the CCD transfer direction and the potential, FIG. 5 is a timing chart diagram showing clock pulses applied to the transfer electrodes in FIG. 4, and FIG. 6 is a horizontal diagram in FIG. FIG. 7 is a cross-sectional view showing the structure around the output part of the transfer part, and FIG. 7 is a timing chart showing clock pulses applied to the respective parts of FIG. In the figure, 1 is a semiconductor substrate, 2 to 9 are gate electrodes, and 10
-15 are impurity regions. In each drawing, the same reference numerals indicate the same or corresponding parts.

Claims (7)

(57) [Claims] 1. A semiconductor substrate having a charge transfer region, a first charge injecting means for injecting a first charge into the charge transfer region of the semiconductor substrate, and a first charge accumulating device for accumulating the charge formed in the semiconductor substrate. No. 1 charge storage means, first reference potential setting means for setting the potential of the first charge storage means to a first reference potential, and the first charge storage set to the first reference potential. First charge transfer means for transferring the first charge injected into the means by the first charge injection means, second charge storage means formed in the semiconductor substrate for storing charge, and The first reference potential is changed by the first charge transferred to the first charge storage means, and the second charge, which is larger than the charge amount of the first charge, is generated based on the changed potential. Second charge injection to inject into the second charge storage means A step, a third charge storage means formed on the semiconductor substrate for storing charges, and a second reference potential setting means for setting the potential of the third charge storage means to a second reference potential, Second charge transfer means for transferring the second charge injected into the second charge storage means to the third charge storage means set to the second reference potential; and the third charge The second reference potential is changed by the second charge transferred to the storage means, and an electric signal output means for outputting an electric signal based on the changed potential is provided.
Charge transfer device. 2. The second charge injecting means comprises a fourth charge accumulating means formed on the semiconductor substrate for accumulating charges, and the fourth charge accumulating means connected to the fourth charge accumulating means. A charge supply means for supplying charges to the storage means; a transfer electrode formed on the first region of the semiconductor substrate sandwiched between the fourth charge storage means and the second charge storage means; A first charge accumulating unit and a potential equalizing unit that makes the potentials of the transfer electrodes the same are provided, and the potential of the first region changes based on the potential of the transfer electrodes. The electric charge supplied to the fourth electric charge accumulating means is set to the second electric charge.
The charge transfer device according to claim 1, which transfers the charge to the charge storage means. 3. The second charge storage means includes a second region of the semiconductor substrate adjacent to the first region, and the second region.
3. The charge transfer device according to claim 2, further comprising: a potential well forming means for forming a potential well having a predetermined depth in the region. 4. The first charge storage means is a first impurity region formed in the semiconductor substrate, and the third charge storage means is a second impurity region formed in the semiconductor substrate. The charge transfer device according to claim 3, wherein the fourth charge storage means is a third impurity region formed in the semiconductor substrate. 5. The first reference potential setting means is the first reference potential setting means.
5. The charge transfer device according to claim 4, further comprising a first transistor having the impurity region as a source or drain region. 6. The second reference potential setting means is the second reference potential setting means.
6. The method according to claim 4 or 5, further comprising a second transistor having the impurity region as a source or drain region.
Charge transfer device according to the item. 7. The electric signal output means includes a third transistor and a resistor connected in series between a reference potential and a ground potential, a gate electrode of the third transistor, and the second impurity region. 7. The charge transfer device according to claim 6, further comprising: a wire connecting the output terminal and an output terminal connected to a connection point of the third transistor and the resistor.