JPH01107573A - Charge transfer device - Google Patents

Abstract

PURPOSE:To obtain a highly reliable charge transfer device, from which a large output signal can be taken out even if the amount of first charge is minute, by generating second charge having the large amount of charge based on the first charge, which is outputted from a charge coupled device, and taking out the output signal based on the charge. CONSTITUTION:Second charge, whose amount of charge is larger than the amount of first charge, which is outputted from a charge coupled device, is supplied otherwise and stored. Thereafter the second charge is transferred. The amount of charge of the transferred second charge is amplified, and the output signal is taken out. Since the output voltage is taken out based on the amount of the second charge, which is larger than the amount of the first charge, in this way, the large output signal is secured even if the amount of the first charge is minute. Thus, a highly reliable charge transfer device, in which the charge outputted from the charge coupled device is amplified on the same substrate for the charge coupled device and can be outputted, can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a charge transfer device, and more particularly to a charge transfer device having a structure capable of improving output characteristics at a transfer termination portion.

[Prior Art] FIG. 3 is a block diagram of a solid-state imaging device using an interline transfer method using a charge transfer device.

The configuration will be explained below with reference to the drawings.

Transfer gates 228 to 22 are provided to the photodetectors 21a to 21c, respectively, which are formed by photodiodes arranged in 3 columns and 4 rows.
Vertical transfer units 23a to 23c made of charge-coupled devices (hereinafter referred to as CCDs) are connected via C. Vertical transfer section 2
3a to 23c have an interface section 2 at the end in the transfer direction.
A horizontal transfer unit 25 made of a CCD is connected through 4a to 24c, and an output terminal 27 is connected to an end in the transfer direction via a preamplifier 26.

Next, its operation will be briefly explained.

The optical signals input to the photodetectors 21a to 21c are converted into electrical signals there, and are read out one after another to the vertical transfer units 23a to 23c by turning on the transfer gates 22a to 22c. The signal charges read out to the vertical transfer sections 23a to 23c are
Transferred by the charge transfer function to the interface section 24
The signals are read out to the horizontal transfer unit 25 via a to 24c. The signal charge read out to the horizontal transfer section 25 is further transferred by the charge transfer function, and the transferred charge is amplified into an electric signal by the preamplifier 26 and sent from the output terminal 27 one after another to the photodetection sections 21a to 21a.
It is extracted as optical input information of 21c. Image processing is performed by continuously repeating this cycle consisting of a series of conversion, transfer, and output operations.

Fig. 4 is a diagram showing the relationship between the cross section along the transfer direction of the COD constituting the horizontal transfer section of Fig. 3 and the potential, and Fig. 5 shows the clock pulse applied to the transfer electrode. It is a timing chart figure.

Hereinafter, the transfer operation of the CCD will be briefly explained with reference to both figures.

First, among the terminals connected to the transfer electrode 28 of the horizontal transfer section 25 according to the clock pulse shown in FIG.
When a voltage of "HH" level is applied to φA2 to φA4 and a voltage of "H" level is applied to φA2 to φA4, the potential well under the transfer electrode of the semiconductor substrate 1 changes at time t. It is formed in the state shown in . At this time, the charges Q^+ Qa l Qc transferred by the vertical transfer sections 23a to 23C are transferred to this potential well via the interface sections 24a to 24c and are temporarily stored. The stored charge is at time t
, ~t, by moving the potential well based on clock pulses, the potential well is sequentially transferred in the direction of the preamplifier 26. Thereafter, by repeating the same clock pulse, the charges transferred from the vertical transfer sections 23a to 23c are transferred one after another to the output side.

FIG. 6 is a sectional view showing the configuration around the output section of the horizontal transfer section in FIG. 3, and FIG. 7 is a timing chart showing clock pulses applied to each component.

The configuration and operation will be described below with reference to both figures.

A transfer electrode 2.3 is formed above the main surface of the semiconductor substrate 1 to which terminals φA3 and φA4 as the most exposed gates of the CCD are connected, and an impurity region 14 is formed on the main surface of the semiconductor substrate 1.
．． 15 is formed. A transfer electrode 4 is formed above the region between the region below the transfer electrode 3 and the impurity region 14, and -
A transfer electrode 9 is formed above the region between the hexagonal blunt region 14 and the impurity region 15 to form a reset transistor. Further, a MOS transistor Q whose gate is connected to the impurity region 14 and a load resistor R are connected to form a preamplifier 26, and an output terminal 27 is connected to a contact point between the transistor Q and the load resistor R.

As for the operation, at time to+, the terminal φ of the gate electrode 3
The voltage level of A4 becomes high level 'H'. At this time, signal charges to be read next are accumulated under gate electrode 2.3. Moreover, at the same time that the voltage level of the gate electrodes 2 and 3 becomes "H", the reset level φR becomes "H".
, and sets the potential of the impurity region to the level of VR.

Then, when the level of the voltage φR of the transfer electrode 9 of the reset transistor changes from "H" to "L", the impurity region 1
4 decreases due to capacitive coupling between transfer electrode 9 and impurity region 14, and is simultaneously output. level also decreases.

Time t. At 2 (>[.,), the voltage φR of the subtransistor electrode 9 is in the "L" state, and the impurity region 14 is in a floating state. Thereafter, the voltage level of the transfer electrode 3 changes from "'H" to "L". time【. s
(>tax), the voltage level of the transfer electrode 3 is in the "L" state, the signal charge accumulated below the transfer electrode 3 is read out to the impurity region 14, and the level of the output D0 changes according to the signal amount. and change. That is, potential changes in impurity region 14 are output to the outside through preamplifier 26 as a source follower.

[Problems to be Solved by the Invention] In a conventional charge transfer device such as the first generation, the configuration around the output section is configured as described above. Here, if the impurity region 14, that is, the floating diffusion, is c and the gain of the D% source follower is G, then the output voltage v0 for the number of signal charges N is Vg - GXqXN5 /'c,D. Here q is the charge of the electron. Therefore vo
becomes larger as CFo becomes smaller. However, CFD is 0.
It is about 0.01 to 0.19F, and it was difficult to make it smaller than this due to microfabrication technology.

Therefore, since there is a limit to reducing the capacitance of the floating diffusion, there is a problem in that it is not possible to obtain a sufficient output for the minute amount of signal transferred from the charge-coupled device.

This invention was made in order to solve the above-mentioned problems, and provides a charge transfer device that can amplify and output the charge output from a charge-coupled device on the same substrate as the charge-coupled device. With the goal.

[Means for solving the problem] The charge transfer device according to the present invention separately supplies a second charge larger than the first charge amount based on the charge amount of the first charge output from the charge-coupled device. This is stored once and then transferred. Based on the amount of the transferred second charge, this is amplified and taken out as an output signal.

[Function] In this invention, since the output voltage is extracted based on the second charge amount which is larger than the first charge amount, a large output signal is ensured even if the first charge is a very small amount. Ru.

[Example] Fig. 1 is a diagram showing the structure around the output section of a CCD and its relationship with potential, showing an example of the present invention, and Fig. 2 shows the relationship between the clock pulse applied to the transfer electrode and It is a timing chart figure shown.

The configuration and operation will be described below with reference to both figures.

Impurity regions 10 and 12 are formed at predetermined positions on the main surface of the semiconductor substrate 1.
．． 13, 14, and 15 are formed. Above and towards the left side of the impurity region 10 is a terminal φ as the final gate of the CCD.
Transfer electrodes 2 and 3 to which A and φA4 are connected are formed, and VG is formed above the region between the region below the transfer electrode 3 and the impurity region 10. A transfer electrode 4 is formed to which a voltage is applied.

A transfer electrode 5 to which a voltage φR1 is applied is formed on the upper edge of the region between the impurity region 10 and the impurity region 12, forming a first reset transistor. Voltages VR7 and φ■ are applied to the impurity regions 12 and 13, respectively, and a transfer electrode 6°7.8 is formed above the region between the impurity regions 13 and 14. The transfer electrode 6 is connected to the impurity region 10 and these are always at the same potential,
Voltages φST and φB are applied to the transfer electrodes 7.8, respectively. Above the region between the impurity region 14 and the impurity region 15 is a transfer electrode 9 to which a voltage φR2 is applied.
is formed and serves as a second reset transistor, and a voltage VR2 is applied to impurity region 15.

As an output circuit, MO is connected between the power supply voltage v0 and the ground power supply.
S transistor Q and load resistor R are connected in series,
The gate of the transistor Q is connected to the impurity region 14, and the output voltage D0 is applied from the connection point between the transistor Q and the load resistor R.
is taken out. The configuration of this output circuit is similar to that of the conventional device.

Next, the operation will be explained. First, at time T, φA4 is at "H" level and signal charge Qs+ is accumulated at the final gate of COD. At the same time, φRI+φR2 is at the "H@ level", the reset transistor is turned on, and the impurity regions 10.14 are set to the level of VR, VR2, respectively (see FIG. 1(b)). At time T2, φR4゜φR2 becomes “L” level and impurity region 10,
14 becomes a floating state (see Figure 1 (C))
. At this time, the level of the impurity region 10.14 is at the level of the transfer electrode 5.
, 9 decreases slightly due to capacitive coupling with .

At time T, φA4 becomes "L" level, and transfer electrodes 2.
The signal charge Qs+ stored under the transfer electrode 4 is transferred to the first impurity region 10 over the barrier under the transfer electrode 4, changing the potential of this portion (see FIG. 1(d)). Since the transfer electrode 6 is connected to the impurity region 10, the potential changes are the same as that of the impurity region 10. Next, at time T4, φ■
becomes the "L" level, and charges are injected from the impurity region 13 that becomes the source into the potential well under the transfer electrode 7 through the transfer electrode 6 (see FIG. 1(e)). At time Ts, φ■ becomes "H". level, so there is a charge QS2 under the transfer electrode 7 determined by the potential under the transfer electrode 6.
remains (see Figure 1(f)). At time TG, φST is “
Since φB becomes L level and H level, the signal charge QS2 under the transfer electrode 7 is transferred to the second impurity region 14, and the potential change generated in the impurity region 14 at this time is outputted through the output circuit as in the conventional case. The voltage becomes D0 and is output to the outside (see FIG. 1(g)).

Here, the charge transferred to the second impurity region 14 is determined by the area of the transfer electrode 7 and the potential difference between the transfer electrode 6 and the transfer electrode 7, but the change in the potential of the transfer electrode 6 is Since the area of the transfer electrode 6 can be increased by reducing the capacitance connected to the transfer electrode 6, the area of the transfer electrode 6 can be increased. By making the area of the transfer electrode 7 as small as possible and making the area of the transfer electrode 7 as large as possible, the degree of charge amplification can be increased.

Furthermore, by appropriately selecting each clock and the level of charge, it is possible to output an output voltage with an arbitrary amount subtracted.

In the above embodiment, an output circuit using a single stage source follower is used, but it can be similarly applied to an output circuit using a multi-stage source follower, and a detection circuit having other configurations may also be used. Needless to say, it can be applied in the same way.

Further, in the above embodiment, the charge obtained by the potential of the transfer electrode connected to the first impurity region is immediately transferred to the second impurity region, but in the meantime, a charge transfer means such as a CCD is further inserted. It is also possible to extract the output voltage based on the charge after transfer.

[Effects of the Invention] As explained above, the present invention generates a second charge with a larger amount of charge based on the first charge output from the charge-coupled device, and extracts an output signal based on this. 1st
This has the effect of providing a highly reliable charge transfer device that can obtain a large output signal even if the amount of charge is minute.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration around the output of a CCD showing an embodiment of the present invention and the relationship between its potential, and FIG. 2 is a timing chart showing clock pulses applied to the transfer electrodes in FIG. 1. Figure 3 is a block diagram of a solid-state imaging device using an interline transfer method using general charge transfer elements, and Figure 4 is a cross section along the transfer direction of the CCD that constitutes the horizontal transfer section in Figure 3. 5 is a timing chart showing the clock pulses applied to the transfer electrodes in FIG. 4, and FIG. 6 is the configuration around the output section of the horizontal transfer section in FIG. 3. FIG. 7 is a timing chart showing clock pulses applied to each component of FIG. 6. In the figure, 1 is a semiconductor substrate, 2 to 9 are transfer electrodes, and 10 is a semiconductor substrate.
15 is an impurity region. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (7)

[Claims] (1) A semiconductor substrate having a charge transfer region, a first charge injection means for injecting a first charge into the charge transfer region of the semiconductor substrate, and a first charge injection means for accumulating the charge formed in the semiconductor substrate. a charge storage means, a first reference potential setting means for setting the potential of the first charge storage means to a first reference potential, and a first charge storage means set to the first reference potential; a first charge transfer means for transferring the first charge injected by the first charge injection means; a second charge storage means formed on the semiconductor substrate for storing charge; The first charge transferred to the charge storage means of
a second charge in which the first reference potential is changed by the charge, and a second charge larger than the amount of charge of the first charge is injected into the second charge storage means based on the changed potential; an injection means, a third charge storage means formed on the semiconductor substrate for storing charge, and a second reference potential setting means for setting the potential of the third charge storage means to a second reference potential. , a second charge transfer means for transferring the second charge injected into the second charge storage means to the third charge storage means set to the second reference potential;
A charge transfer device comprising: an electric signal output means for changing the second reference potential by the second electric charge transferred to the electric charge storage means, and outputting an electric signal based on the changed electric potential. (2) The second charge injection means includes a fourth charge storage means formed on the semiconductor substrate for storing charge, and a fourth charge storage means connected to the fourth charge storage means. a transfer electrode formed on a first region of the semiconductor substrate sandwiched between the fourth charge storage means and the second charge storage means;
and a potential equalization means for making the potential of the transfer electrode the same, the potential of the first region changes based on the potential of the transfer electrode, and the potential of the first region is changed by the charge supply means. 4. The charge transfer device according to claim 1, wherein the charge supplied to the second charge storage means is transferred to the second charge storage means. (3) The second charge storage means includes a second region of the semiconductor substrate adjacent to the first region, and a potential well forming means for forming a potential well of a predetermined depth in the second region. A charge transfer device according to claim 2, comprising: (4) the first charge storage means is a first impurity region formed on the semiconductor substrate; the third charge storage means is a second impurity region formed on the semiconductor substrate; Claim 3, wherein the fourth charge storage means is a third impurity region formed in the semiconductor substrate.
The charge transfer device described in Section 1. (5) The charge transfer device according to claim 4, wherein the first reference potential setting means includes a first transistor whose source or drain region is the first impurity region. (6) The charge transfer device according to claim 4 or 5, wherein the second reference potential setting means includes a second transistor whose source or drain region is the second impurity region. (7) The electrical signal output means connects a third transistor and a resistor connected in series between a reference potential and a ground potential, and a gate electrode of the third transistor and the second impurity region. 7. The charge transfer device according to claim 6, comprising a wiring for connecting the third transistor and the resistor, and an output terminal connected to a connection point between the third transistor and the resistor.