JPH03179276A - Charge detection circuit - Google Patents

Abstract

PURPOSE:To obtain large max. signal quantity by connecting a plurality of nodes having second conductivity type impurity regions for detecting a signal in series through a MOS transistor and connecting source followers to the second conductivity impurity regions of the respective nodes. CONSTITUTION:The gate electrode 41 of the respective gate electrodes 41, 42 of the first and second resetting transistors resetting the first and second floating diffusions DF51, 52 forms a barrier of potential (P0) between DF51, 52. Both of DF51, 52 are the second conductivity type impurity regions and connected to the transistors Tr01, 02 of source followers. A figure (b) shows P0 at a time t1 and figures (c), (d) show potentials (P0) at the times of small and large signal quantities at a time t2 and signal charge Q is transmitted to a charge detection circuit by a clock of every kind and P0 under the electrode 41 is determined so as to become deeper than P0 under a gate electrode 3 and charge is detected only by the DF51 at the time of small signal quantity and the charge Q2 overflowing the DF51 is detected by the DF52 at the time of large signal quantity. By this constitution, large max. signal quantity is obtained while the sensitivity of the change detection circuit is kept high.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a charge detection circuit, and particularly to a charge detection circuit used as an output circuit of a semiconductor integrated circuit.

[Conventional technology]

Charge-coupled devices (hereinafter referred to as "CCDJ") in semiconductor integrated circuits have floating devices that perform charge-voltage changes.
A charge detection circuit called a diffusion amplifier is used.

FIG. 4(a) is an explanatory diagram showing a cross-sectional structure when this floating diffusion amplifier is used in an output circuit of a COD. In the figure, a final gate electrode 2 of a CCD and a potential barrier forming gate electrode 3 are arranged at predetermined locations on a semiconductor substrate 1 of a first conductivity type.

One of the drive clocks φH for charge transfer is connected to the gate electrode 2.
is applied, and a DC voltage VGO is applied to the gate electrode 3.

Then, a gate electrode 4 is placed in a region adjacent to the gate electrode 3.
and a second conductivity type high concentration impurity region 5.6.
An S transistor is formed.

A reset clock φR is applied to the gate electrode 4 of this MO3I-transistor, and by setting the reset clock φR to a high level, the MOS transistor is turned on. Further, a reset power supply voltage VR is applied to the impurity region 6.

Impurity region 5 is called a floating diffusion, and is connected to the gate of an output source follower transistor TrQ formed on the same semiconductor substrate 1. A source follower power supply voltage vO is applied to the drain of the transistor TrQ. Also, this transistor T
The source of rO is grounded through a load resistor RO,
A signal DO is output from the connection point between the source and the load resistor RO.

Next, the operation will be explained. FIGS. 4(b) to (dl) are explanatory diagrams showing the potential of each part of FIG. 4(al) at times corresponding to clock timings t1 to t3 in FIG. 5, respectively.

First, at time B in FIG. 5, drive clock φH (FIG. 5(
a)) is at a high level, and there is a fourth layer under the gate electrode 2.
As shown in Figure (b), a potential well is formed and signal charges Q are accumulated. At the same time, the reset clock φR (FIG. 5(b)) is at a high level, and the M
The OS transistor is turned on, and the voltages at the gates of impurity region 5 and the transistor TrO connected thereto are reset to the level of reset power supply voltage VR.

Next, at time t2 in FIG. 5, the reset clock φR becomes low level, and the gate electrode 4, the impurity region 5, and the formed MOS transistor are turned off (the fourth
(See figure (C)). When the reset clock φR changes from high level to low level, the potential of impurity region 5 decreases due to capacitive coupling between gate electrode 4 and impurity region 5. While the reset clock φR is at a low level, the node connected to the impurity region 5 is floating.

Next, when the driving clock φH becomes low level at time t3 in FIG. 5, the signal charge Q stored in the potential well under the gate electrode 2 is read out to the impurity region 5 (see FIG. ), the voltage at the node of impurity region 5 is changed, and this change in potential is outputted through the source follower circuit.

The output size Δ■ is as follows: ΔV==G-Q/CFD (1) where the floating diffusion node capacitance is Cy D % and the source follower gain is G. Since the gain of the source follower is usually about 0.7 to 0.9 and hardly changes, in order to increase Δ■ for the same signal amount Q, it is necessary to decrease the capacity ICF.

The larger ΔV is for the same signal IQ, the larger the charge-voltage conversion gain, which is advantageous from the viewpoint of S/N.

On the other hand, the maximum amount of charge that can be detected by the charge detection circuit is a signal that causes a potential change such that even when the signal charge is accumulated in the impurity region 5, the potential of the region does not exceed the channel potential under the gate electrode 3. This determines the maximum amount of charge that the capacitance CFD can detect. CFD
If an attempt is made to increase the charge-voltage conversion gain by decreasing , the potential change in the floating diffusion portion will increase, but the maximum detectable charge amount will decrease.

[Problem to be solved by the invention]

Figure 6 shows the amount of signal charge Q generated electrically and optically in the COD and the magnitude Δ of the output of the source follower transistor.
It is a graph showing the relationship with V.

As shown in the figure, the relationship between Q and ΔV is linear up to the output saturation level Do□8, which is determined by the CCD design and the circuit system of the source follower transistor. On the other hand, the output ΔV is in a saturated state and the output level is constant. Here, if the capacitance I Cr n is decreased and the output magnitude ΔV for the human charge IQ is increased as shown from Sa to sb in FIG. 6, and the charge-voltage conversion gain is increased, the maximum amount of charge is Q. a...
, to Qb may, and a small signal charge qs superimposed on the background cannot be detected.

The present invention has been made in view of these points, and its purpose is to provide a method for driving a charge detection circuit in which the maximum amount of charge that can be detected does not decrease even if the charge-voltage conversion gain is increased. It's about doing.

[Means to solve the problem]

In order to distantly achieve such an object, the present invention provides a plurality of nodes having impurity regions of the second conductivity type for signal detection.
They are connected in series via an OS transistor, and a source follower is connected to each impurity region of the second conductivity type.

[Effect]

The charge detection circuit according to the present invention first detects the charge in the first floating diffusion, and when the first floating diffusion is saturated and overflows, the overflow is detected in the second floating diffusion. By detecting the overflow and then sequentially detecting the overflow using floating diffusions connected one after another, the maximum amount of charge can be increased while maintaining high sensitivity.

〔Example〕

An embodiment of the charge detection circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 is an explanatory diagram showing one embodiment of a charge detection circuit according to the present invention. In FIG. 1(a), numerals 1 to 3 and 6 are the same as in FIG. 4. 41 is a gate electrode of a first reset transistor that resets the first floating diffusion;
and second floating diffusion 51 and 52
A potential barrier is formed between the two. 42 is a gate electrode of a second reset transistor that resets the second floating diffusion 52. Floating diffusion 51゜52 are both second
This is a conductive type impurity region. Trol, Tr02 is the first
．． Second floating diffusion 51.52
A source follower transistor, ROl, connected to
RO2 is the load resistance of the first and second source followers, DO
I, C02 is the 1st. a second source follower output signal;
vO is a common power supply voltage for source followers.

Next, the operation of the charge detection circuit shown in FIG. 1(a) will be described. FIG. 2 is a timing chart showing clock timings for explaining the operation of the charge detection circuit shown in FIG. 1(a).

Fig. 1(b) is an explanatory diagram showing the potential at time t1 in Fig. 2;
2 is an explanatory diagram showing the potential when the signal amount is small and when the signal amount is large in No. 2. FIG. At time t1, reset clocks φR1 and φR2 (Fig. 2(b), (C1)
are both at the rHJ level (VRIH, VR2H), and the floating diffusions 51 and 52 are reset to the level of voltage VR through the second and first reset transistors. At time t2, φR1, φR2
Ga r LJ Rehe Bv (VRI L, VR2L)
Then, COD final gate clock φH (Fig. 2(a)
)) becomes the "L" level, so the signal charge Q is transferred to the charge detection circuit (see FIG. 1 (C1, (d))).

At this time, VRIL is determined so that the potential under the gate electrode 41 is deeper than the potential under the gate electrode 3. When the signal amount is small, the signal charge Q is detected only by the first floating diffusion 51, as shown in FIG. 1 (C1).

When the signal amount increases and the first floating diffusion overflows, as shown in Figure 1 (
As shown in d), the overflowed charge Q2 is
Detected by floating diffusion. In this case, the sum of Ql detected by the first floating diffusion and C2 detected by the second floating diffusion becomes the total signal I#Q.

The transfer characteristic in this charge detection circuit is as shown in FIG. In FIG. 3, Dol (FIG. 2(d)) is the output signal of the first source follower, and DO2 (FIG. 2(e)) is the output signal of the second source follower.

In the above embodiment, the case where there are two floating diffusions has been described, but it is also possible to have a larger number of floating diffusions.

Further, in the above embodiment, the case where an n-type channel is used has been described, but a similar configuration can be realized using a p-type channel.

Further, in the above embodiment, the source follower has one stage and a resistor is used as the load, but the source follower may have multiple stages, and the load may be a transistor.

Further, in the above embodiments, a circuit provided on an I conductivity type semiconductor device has been described, but the circuit may have a well structure.

〔Effect of the invention〕

As explained above, the present invention has the effect of obtaining a large maximum signal amount while keeping the sensitivity of the charge detection circuit high by detecting charges using a plurality of floating diffusions connected in series. be.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing an embodiment of the charge detection circuit according to the present invention and the potential of each part of the embodiment, and FIG. 2 is a timing diagram showing the driving clock timing of the charge detection circuit of FIG. 1(a). , FIG. 3 is a graph showing the relationship between the signal charge amount and the output voltage in the charge detection circuit of FIG. Figure 5 is similar to Figure 4 (a
) is a timing diagram showing the drive clock timing of the charge detection circuit, and FIG. 6 is a graph showing the relationship between the signal charge amount and the output voltage in the charge detection circuit. 1... Semiconductor substrate, 2... CCD final gate electrode,
3... Potential barrier forming gate electrode, 6... Impurity region, 41.42... Gate electrode, 51.52... Floating diffusion, Trol, Tr02.
...Transistor, ROl, RO2...Load resistance.

Claims (1)

[Claims] In a charge detection circuit that detects signal charges from a CCD formed on a semiconductor substrate of a first conductivity type, a plurality of nodes having impurity regions of a second conductivity type for signal detection are connected to a MOS transistor.
connected in series via transistors, connecting a source follower to each second conductivity type impurity region, and transferring a signal to the next stage node when the potential of the series connected nodes reaches a saturation level; A charge detection circuit featuring: