JPH04262575A - Solid state image sensor - Google Patents

Abstract

PURPOSE:To mount charge input units at all places of charge coupled elements, to make an array of all photodetectors uniform and to provide excellent resolution by connecting the input units to the coupled elements through transfer gates to be disposed. CONSTITUTION:A plurality of photodiodes (photodetectors) 4 for constituting a photoelectric converter are arranged in one row on a semiconductor substrate 3, and two CCDs (charge coupled elements) 5 are formed in parallel with the photodiodes 4. Charge input units 8 are provided at the end of the array of the photodiodes 4 through transfer gates 6 to be able to electrically inject charge. The units 8 are connected to the elements 5 through the gates 6 to be arranged, the units 8 are provided at the ends (output amplifier 7 side) of pixel row which scarcely affect influence to the array of the photodetectors 4, and a pitch of the pixels is made uniform.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention relates to a solid-state imaging device.
In particular, charge coupled devices (Charge Coupled D
The present invention relates to the structure of a charge input section of a CCD (hereinafter referred to as a CCD).

0002

[Prior Art] Generally, in a linear image sensor, signal charges of a plurality of light receiving elements arranged one-dimensionally are transferred to a single CCD.
A reading method using . In recent years, there has been a growing demand for higher resolution, and the number of light-receiving elements has also tended to increase accordingly. However, as the number of light-receiving elements increases, the number of CCD stages increases, resulting in problems such as deterioration of overall transfer efficiency and increase in data rate.One way to solve these problems is to A method has been considered in which the light receiving element is divided and the signal is read out using two CCDs arranged in series.

More specifically, in FIG. 6, reference numeral 3 denotes a semiconductor substrate, on which a plurality of photodiodes (light receiving elements) 4 constituting a photoelectric conversion section are arranged in a row. Two Cs parallel to the array of diode 4
CD5 is formed. Further, a transfer gate 6 is individually formed between each photodiode 4 and the charge transfer section of the CCD 5, and the signal charge accumulated in the photodiode 4 is transferred to the CCD 5 by the ON operation of the transfer gate 6. ing. Further, an output amplifier 7 is formed at the terminal end of the CCD 5, and the signal charges transferred by the CCD section 5 are amplified by the output amplifier 7 and output to the outside of the solid-state image sensor chip 1.

Further, reference numeral 2 denotes a charge input section provided at the first stage of the CCD 5, which is designed to be able to electrically inject charges into the CCD 5. This charge input section 2 electrically injects charge into the CCD 5 from the outside when not in the imaging mode, and
It is used to electrically check and calibrate the CD 5 and output amplifier 7, or to test each transfer electrode constituting the CCD 5 during the manufacturing stage of the CCD 5.

FIG. 7 is a diagram showing in detail the structure of the charge input section 2 and its surroundings, in which numeral 10 denotes a charge input terminal;
, 9 are charge input control gates for controlling the amount of charge input from the charge input terminal 10, and 11 and 12 are transfer electrodes of the CCD 5, to which clocks Φ1 and Φ2 are input, respectively.

Next, the operation in the charge input mode will be explained with reference to the drawings. Figure 8(a) is Figure 7 in charge input mode.
A cross-sectional view at the CC' section and its potential are shown, and FIG. Clock pulses I, Φ1, Φ are applied to the charge input terminal 10 and the signal input terminals of the transfer electrodes 11 and 12, respectively.
2 is input, and DC voltages VGIL and VGIH are applied to the signal input terminals of charge input control gates 8 and 9.

First, at time t1, charge input terminal 1
0, it is assumed that the transfer electrode 12 is set to a high level and the transfer electrode 11 is set to a low level.

When time t1 changes to t2, the input signal I at the charge input terminal 10 changes from a high level to a low level, and charges flow from the charge input terminal 10 into the potential wells below the input control gates 8 and 9. Further, at time t3, the charge input terminal 10 becomes high level again, and the metered input charge (Q0) is accumulated in the potential well below the input control gate 9.

Next, at time t4, "H" is applied to Φ1,
"L" is applied to Φ2, transfer electrode 11 becomes high level, transfer electrode 12 becomes low level, and the measured charge (Q0
) flows into the potential well below the CCD transfer electrode 11.

Next, the case in the imaging mode will be explained. FIG. 9(a) shows the potential in the section taken along the line CC' in FIG. 7 in the imaging mode, and FIG. 9(b) shows the signal waveforms input to each terminal. As in the charge input mode, the clock pulses I, Φ1, Φ2 are input to the charge input terminal 10 and the signal input terminals of the transfer electrodes 11 and 12, respectively, and the DC voltage VGIL is input to the signal input terminals of the charge input control gates 8 and 9. , VGIH are applied.

The transfer gate (TG) 6 opens between time t1 and time t2, and the signal charges Q1 and Q2 detected by the light receiving elements 4-1 and 4-2 are transferred into the potential wells under the corresponding transfer electrodes 11. will be forwarded to.

Thereafter, at time t3, the clock signal Φ1 of the transfer electrode 11 is set to "L" level, the signal Φ2 of the transfer electrode 12 is set to "H" level, and the signal charges Q1 and Q2 are transferred to the potential well below the transfer electrode 12 of the next stage. Transfer within. Thereafter, a clock is supplied to the electrodes 11 and 12 in the same manner, and the signal charge is synchronized with the clock pulse, and the output amplifier 7
Transfer it to the side.

[0013]

[Problem to be Solved by the Invention] Since the conventional linear image sensor is constructed as described above, the arrangement pitch of the light receiving elements 4 at the target position with the charge input section 2 as the center is different from the arrangement pitch in other parts. The problem was that it was larger than the original.

That is, for example, if the width of the transfer electrodes 11 and 12 is 8 μm, adjacent light receiving elements (for example, 4-1 and 4-4)
-2) (in the figure, L1) is designed to be 16 μm, the interval between the light receiving elements 4-1 of the charge input section 2 (in the figure,
L2) was required to be 28 μm when the width of the charge input terminal 10 was 4 μm and the widths of the charge input control gates 8 and 9 were 3 μm and 5 μm, respectively. In this way, when the space of the charge input section 2 is large and the arrangement pitch of the light receiving elements in this section becomes large, the resolution of the charge input section 2 decreases significantly, making it impossible to obtain uniform resolution within the device. .

The present invention has been made to solve the above-mentioned problems, and aims to provide a solid-state imaging device in which charge can be easily input to a CCD and the arrangement pitch of all light-receiving elements is uniform. purpose.

[0016]

[Means for Solving the Problems] In a solid-state imaging device according to the present invention, a charge input section for electrically inputting charges to a charge-coupled device is connected to the charge-coupled device via a transfer gate. It was designed to do so.

Further, the operation of the transfer gate connected to the charge input section is synchronized with the operation of the transfer gate connected to the light receiving element, so that charge is input to the charge-coupled device by turning it on.

[0018]

[Operation] In this invention, the charge input section is connected to the charge coupled device via the transfer gate, so the charge input section can be installed at any location on the charge coupled device, and all light reception is possible. The arrangement pitch of elements can be made uniform.

Furthermore, since the operation of the transfer gate connected to the charge input section is synchronized with the operation of the transfer gate connected to the light receiving element, and charge is input to the charge-coupled device when turned on, it is possible to It is also possible to input charge electrically.

[0020]

Embodiment FIG. 1 is a plan view of a solid-state imaging device according to an embodiment of the present invention. In the figure, 3 is a semiconductor substrate;
A plurality of photodiodes (light-receiving elements) 4 constituting a photoelectric conversion section are formed on top of the photodiode 4 arranged in a line, and two CCDs 5 are formed parallel to the arrangement of the photodiodes 4. In addition, each photodiode 4 and CCD 5
A transfer gate 6 is separately formed between the photodiode 4 and the charge transfer section, and the signal charges accumulated in the photodiode 4 are transferred to the CCD 5 by the ON operation of the transfer gate 6. Further, an output amplifier 7 is formed at the terminal end of the CCD 5, and the signal charges transferred by the CCD 5 are amplified by the output amplifier 7 and output to the outside of the solid-state image sensor chip 1. Further, a charge input section 8 is provided at the end of the array of photodiodes 4 via a transfer gate 6, so that charges can be electrically injected.

Next, the operation will be explained. The signal charges accumulated in the photodiode 4 and the charge input section 8 are simultaneously transferred to the CCD 5 in synchronization with a clock pulse applied to the transfer gate 6. The charges transferred to the CCD 5 are sequentially transferred to the output amplifier 7 and output to the outside.

The operation of reading out charges from the charge input section 8 and pixels will be explained using FIGS. 2 and 3. First, the operation of the charge input section 8 will be explained. FIG. 2 is an enlarged view of the charge input section 8 in FIG. 1. In the figure, 23 is a charge input source, 21 and 22 are charge input control gates for electrically controlling the amount of input charge, and 6 is a charge input control. gate 21,
A transfer gate 22 controls the transfer of the measured charge to the CCD 5, and 11 and 12 are transfer electrodes of the CCD 5. Further, FIG. 3(a) shows the AA' cross section in FIG. 2 and its potential, and FIG. 3(b) shows a waveform diagram of signals input to each terminal.

Charge input terminal 23, transfer gate 6
, transfer electrodes 12 are provided with clock pulses ΦI and ΦT, respectively.
It is assumed that G and Φ2 are input, and DC voltages VGIL and VGIH are applied to charge input control gates 21 and 22.

First, at time t1, the charge input terminals 23,
A high level signal is input to the transfer electrode 12, and a low level signal is input to the transfer gate 6.

Then, from time t1 to t2, the level of the charge input terminal 23 decreases, and charges flow from the charge input terminal 23 into the potential well below the charge input control gates 21 and 22.

Further, at time t3, charge input terminal 2
3 goes high again and the metered input charge is stored only in the potential well below the input control gate 21.

Next, at time t4, the transfer gate 6 becomes high level, and the measured input charge is transferred into the potential well below the CCD transfer electrode 12.

Next, the operation of reading signal charges from pixels will be explained. FIG. 4(a) shows the BB' cross section and potential in FIG. 2, and FIG. 4(b) shows a waveform diagram of signals input to each terminal.

At time t5, a high level signal is input to transfer gate 6 and transfer electrode 12.

Then, from time t5 to t6, the transfer gate 6 becomes low level, a transfer pulse is applied to the transfer electrode 12, and the photodiode 4 enters the signal accumulation state as shown at time t7.

At time t8, a high level signal is again input to the transfer gate 6, and the signal charge accumulated in the photodiode 4 is transferred into the potential well below the CCD transfer electrode 12.

According to this embodiment, the charge input section 8 is connected to the charge-coupled device 5 via the transfer gate 6, so that the charge input section 8 does not affect the arrangement of the light receiving elements 4. End of pixel row (output amplifier 7 side)
Therefore, the pixel pitch is uniform and the pattern layout is easy.

Furthermore, since the charge input is performed in synchronization with the clock pulse of the transfer gate 6, charge input is possible even in the imaging mode, and mode switching between the input mode and the imaging mode for charge input is unnecessary.

[0034]Although the above embodiment has been described with respect to a one-dimensional solid-state imaging device, the present invention is not limited thereto, and can also be applied to a two-dimensional solid-state imaging device. To explain in detail using FIG. 5, FIG. 5(a) shows the overall view, and FIG. 5(b) shows the vicinity of the charge input part in FIG. 5 in detail. The same reference numerals as in FIG. 2 indicate the same or equivalent parts, 5a is a vertical CCD, 5b is a horizontal CCD, and the above figure except that the charge input section 8 is connected to the vertical CCD 5a via the transfer gate 6. This is exactly the same as shown in 1.

In this configuration, the two-dimensional solid-state image sensor is divided in the center, the signal charge detected by the light receiving element 4 is transferred to the vertical CCD 5a via the transfer gate 6, and the signal charge transferred from the vertical CCD 5a is two horizontal C
They are read out simultaneously by the CD5b. Even in such a configuration, by inputting a clock pulse to the charge input source 23 and the transfer gate 6 and applying a DC voltage to the input control gates 21 and 22, the vertical CCD 5a can be controlled in synchronization with the clock pulse of the transfer gate 6. Charge input can be performed, and since the charge input section 8 is provided outside the pixel region 9, the arrangement pitch of the light receiving elements 4 can be made uniform.

In the above embodiment, the charge input section 8 (vertical CCD 5a on which the charge input source 23 is arranged) is connected to the charge coupled device 5.
Although two devices are shown on the output amplifier 7 side of the (horizontal CCD 5b), the arrangement position and number of these devices are not limited to this. It is also possible to have a configuration in which a number of them are provided.

[0037]

As described above, according to the solid-state imaging device of the present invention, the charge input section is arranged to be connected to the charge coupled device via the transfer gate, so that the charge input section is connected to the charge coupled device through the transfer gate. It can be installed anywhere on the element, and the arrangement pitch of all the light receiving elements can be made uniform, and as a result, a solid-state imaging device with excellent resolution can be obtained.

Furthermore, since the operation of the transfer gate connected to the charge input section is synchronized with the operation of the transfer gate connected to the light receiving element, and charge is input to the charge-coupled device when turned on, it is possible to Also, it is possible to obtain a high-performance solid-state imaging device that can perform electrical inspection by electrically inputting charges.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is an enlarged view of a charge input section of a solid-state imaging device according to an embodiment of the present invention.

FIG. 3 is a diagram showing the potential of the AA' cross section in FIG. 2 and the waveform of a signal input to each terminal.

FIG. 4 is a diagram showing the potential of the BB' cross section in FIG. 2 and the waveform of a signal input to each terminal.

FIG. 5 is a plan view and an enlarged view of a charge input section of a two-dimensional solid-state imaging device according to an application example of the present invention.

FIG. 6 is a plan view showing a conventional solid-state imaging device.

FIG. 7 is a diagram showing details of a charge input section of a conventional solid-state imaging device.

[Figure 8] Figure 7 in charge input mode of a conventional solid-state imaging device
FIG. 2 is a potential diagram of a cross section taken along line CC' in FIG.

9A and 9B are a potential diagram of a cross section taken along the line CC' in FIG. 7 and a signal waveform diagram input to each terminal in an imaging mode of a conventional solid-state imaging device.

[Explanation of symbols]

1 Solid-state image sensor chip 3
Semiconductor substrate 4 Photodetector 5 CCD 6 Transfer gate 7
Output amplifier 8 Charge input section 21, 22 Charge input control gate 23 Charge input source

Claims (2)

[Claims] 1. A plurality of light-receiving elements, a transfer gate that controls readout of signal charges detected by the light-receiving elements, a charge-coupled device that sequentially transfers the signal charges of the light-receiving elements via the transfer gates, A solid-state imaging device having a charge input section that electrically inputs a predetermined potential to a charge-coupled device, characterized in that the charge input section is connected to the charge-coupled device via a transfer gate. Imaging device. 2. The solid-state imaging device according to claim 1, wherein the transfer gate connected to the charge input section operates in synchronization with the transfer gate connected to the light receiving element.