JPS61294962A - Linear color sensor - Google Patents

Abstract

PURPOSE:To obtain a serial color signal by sending photoelectric converting signals corresponding to a photodiode array having a 3-primary color filter on its surface and the 3-primary colors constituting one picture element to a CCD shift register while arranging the signals in a prescribed order. CONSTITUTION:An output signal of a red signal photodiode RPn is fed to the n-th stage FHS 2 of the CCD 2 receiving a clock signal phi1 among 3 photodiodes BPn, GPn, RPn constituting one color picture element. Further, an output signal of the green signal photodiode GPn is fed to the (n-1)-th stage of the CCD 1 and the output signal of the blue signal photodiode BPn is fed to the (n-2)-th stage of the CCD 2. Then the red signal is fed to the (n-3)-th stage of the CCD 1, the green signal is fed to the (n-4)-th stage of the CCD 2 and the blue signal is fed to the (n-5)-th stage of the CCD 1, and the procedures above are repeated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a one-dimensional color sensor, and, for example, to a technique that is effective when applied to a one-dimensional color sensor using a COD (charge transfer device).

[Background technology]

Photosensors are known that convert image signals photoelectrically converted by a photodiode array into serial image signals using a COD (charge transfer device) analog shift register and output them. Engineering, rec, tronics 1 pages 140-15
(see 7).

It is conceivable to obtain color signals by arranging the above-mentioned -dimensional photo sensors in parallel and providing color filters for the three primary colors, red, edge, and blue, respectively.
However, in this case, as the width of the chip constituting each -dimensional sensor is increased to about 1.0-1.5 tm, three primary color signals at the same location (lis) cannot be obtained at the same time. , there is a problem that post-processing of the signal is required.

[Purpose of the invention]

An object of the present invention is to provide a color-ffi system with a simple configuration.
The object of the present invention is to provide a one-dimensional color sensor that can form a color image.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a photodiode array each having color filters of three primary colors provided on its surface, and -i! The photoelectric conversion signals corresponding to the three primary colors constituting the element are arranged in a fixed order and transferred to the CCD shift register, thereby allowing color signals to be obtained serially from the CCD shift register.

[Embodiment 1] FIG. 1 shows a block diagram of an embodiment of the present invention.

Each circuit block in the figure is formed on a semiconductor substrate 1 (II) using a known semiconductor integrated circuit manufacturing technique. Although not particularly limited, in this example, photodiodes are arranged in three rows on the semiconductor substrate. arranged,
Configure a photodiode array. The photodiodes in each row are irradiated with light to be photoelectrically converted through color filters of red (R), green (G), and blue (B), each of which constitutes one of the three primary colors. Although not particularly limited, each color filter is formed directly on each photodiode by coating type techniques of dyeable transparent coatings such as gelatin, photoetching techniques, and dyeing techniques.

According to this embodiment, two analog CCD arrays are used for three photodiode arrays located close to each other.
Shift registers CCDI and CCD2 are provided.

The two CCD shift registers CCD1 and CCD2 are
Each of them is composed of a known two-phase CCD shift register, and is driven by timing signals φ1 and φ2 having mutually different phases.

Thus, in each CCD shift register, a 1-pint shift stage is adjacent to two half-bit shift stages adjacent to each other, that is, a half-pit shift stage driven by the timing signal φ1 or φ2, and a half-bit shift stage driven by the timing signal φ1 or φ2. A half-bit shift stage driven by the timing signal φ2 or φ1.

The outputs of the two shift registers need to be combined into one in order to finally obtain one serial photoelectric conversion signal, in other words, one serial color signal. Although not particularly limited, according to this embodiment, the outputs of the two shift registers CCD1 and CCD2 are shared and then supplied to a common amplifier circuit A. The two shift registers CCD1 and CCD2 are configured to output signals at mutually different timings. Note that the shift register CCDI includes B, the last half-bit shift stage, and F driven by the timing signal φ2.
Similarly, shift register CCD2, which is provided between H31 and the input of amplifier circuit A and has a gate portion (not shown) driven by timing signal φ1, includes a half-bit shift stage FH32 driven by timing signal φ1 and an amplifier circuit. The timing signal φ is provided between the input of
It has a gate section (not shown) driven by 2. In response, shift register CCD1 outputs a photoelectric conversion signal in synchronization with timing signal φ1, and shift register CCD2 outputs a photoelectric conversion signal in synchronization with timing signal φ2.

According to this example, three adjacent photodiodes in a three photodiode array are considered to constitute one color pixel.

That is, photodiodes BPI, GPl and RPl are connected to the first color ii! Consists of 1 element, BF2, GP2
and RP2 constitute the second color pixel. Similarly, B P n % G P n and RP n constitute the final color pixel.

A timing signal φt is provided between the two shift registers CCD I and CCD2 and the three photodiode arrays.
Transfer gate MOSFET switch controlled by g
QT is provided. Each transfer gate MO5FETQT
The combination pattern of three photodiode arrays and two shift registers CCD1 and CCD2 coupled through is based on the condition that three color signals for each color pixel are sequentially output from two shift registers CCDI and CCD2. is set. Although not particularly limited, the output order of each of the three color signals constituting one color pixel is fixed in order to facilitate video signal processing in a video signal processing device (not shown). According to this embodiment, the red signal is output first, the R signal is output next, and the green signal is output last.

In the two-phase CCD shift register CCDI or CCD2, in order to prevent color signal destruction during transfer, the subsequent half-bit shift stage adjacent to one half-bit shift stage in which the color signal is held may be left empty. Needed. In other words, one bit of shift stage is required for one color signal. Therefore, three 1-bit shift stages are required for the three color signals of one color Wi element. According to this example, the above bonding pattern is:
It is also set under the condition that the number of shift stages of each shift register is minimized. Specifically, a single-color pixel corresponds to one half of each of the shift registers CCDI and CCD2, or in other words, to three half bit shift stages of each of the shift registers CCDI and CCD2.

A combined pattern consists of a plurality of unit patterns that have the same configuration. As will become clear from the explanation that follows, each unit pattern is set for two color pixels each and one bit shift stage of each 31Wi of shift registers CCDI and CCD2.

That is, of the photodiode array, for example, 3 (1f
photodiode B P n SG P n and RPn
Among them, the output signal of the photodiode RPn forming the red signal is supplied to the final stage, ie, the n-th stage FH32 of the lower stage COD shift register CCD2 to which the clock signal φ1 is supplied via the transfer gate MOS FETQT. Further, the output signal of the photodiode GPn forming the line signal is transferred to the upper stage COD shift register C to which the clock signal φ1 is supplied via the transfer gate MO5FETQT.
It is supplied to the 1n-1st stage of CDI. Further, the output signal of the photodiode BPn forming the blue signal is supplied to the n-2nd stage of the lower stage COD shift register CCD2 to which the clock signal φ1 is supplied via the transfer gate MO3FETQT.

Next, three photodiodes BPn-1, GPn-1 and RP constituting the second color pixel from the right end of the drawing
Among n-1, red (photodiode RP forming No. 8)
The output signal of n-1 is the transfer gate MOSFETQT
The clock signal φ1 is supplied to the n-3rd stage of the upper stage COD shift register CCD1 through which the clock signal φ1 is supplied. Further, the output signal of the photodiode GPn-1 forming the green signal is transferred to the lower stage COD shift register CC to which the clock signal φ1 is supplied via the transfer gate MO3FETQT.
It is supplied to the n-4th stage of D2. Furthermore, the output signal of the photodiode B P n −1 forming the blue signal is
Clock signal φ1 via transfer gate MO3FETQT
is supplied to the n-5th stage of the upper stage COD shift register CCD1.

By repeating the same configuration (unit pattern) with the above two-power color pixels as one set, the output signal of each photodiode is transferred to the upper and lower COD shift registers C.
The signals are supplied to CDI and CCD2, respectively.

FIG. 3 is a timing diagram of the timing signals φtg, φ1, φ2 supplied to the color sensor of the embodiment and the serial color signal obtained therefrom.

Each timing signal is generated by a timing generation circuit (not shown) that receives a periodic pulse signal or clock signal such as that obtained from an oscillation circuit. - As shown in FIGS. 3B and 3C, the timing signals φ1 and φ2 are set to high level and low level, respectively, at the sensing operation start timing or time tQsttn, and the transfer of the color signal is started. They are set to low level and high level at the desired timing or time t2, respectively.

These timing signals φ1 and φ2 are transmitted from time t2 to t
During the period up to m, in other words, during the transfer period, the high level and low level are complementarily set at a period determined by the pulse signal or clock signal.

As shown in FIG. 3A, the transfer timing signal φtg is set to a high level at time t1 after time 10, that is, at the transfer timing.

Depending on the timing signal, the sensor operates as follows.

When the transfer timing signal φtg is set to high level at time t1, all transfer gates MO5
FETQT is turned on.

As a result, pixel signals are taken in in the order of red, blue, and edge from each even-numbered half-bit shift stage of the lower stage COD shift register CCD2, that is, every other half-bit shift stage from the right (last stage side) in FIG. Also, the upper stage COD shift register C
Pixel signals of green, red, and blue are taken in in the order of green, red, and blue into each odd-numbered half-bit shift stage of the CDI, that is, every other shift stage from the one vacant right (last stage side) in FIG. That is, the color signals formed by the three photodiode arrays, each in the form of a charge, are transferred to the shift register CC
Of the half-bit shift stages in D1 and CCD2, it is transferred or preset to each half-bit shift stage driven by timing signal φ1.

Next, at a timing t2 after the transfer timing signal φtg is set to a low level, in other words, at a timing after the pixel signal has been supplied to each shift register, the timing signal φ2 is shown in FIG. 3C. When set to high level as shown above, the pixel signals preset in the respective shift registers are transferred to the respective half-bit shift stages driven by the timing signal φ2. At time t2-, the pixel signal formed by the photodiode RPn, that is, the red signal, is output from the shift register CCD2. In response, a pixel signal having a level proportional to the red light level as shown in the third diagram is output to the output terminal OUT of the sense amplifier circuit A.

At time t3, when the timing signal φ1 is set to high level as shown in FIG. 3B, at time t3, both l#48 in each shift register are shifted again. A pixel signal formed by photodiode GPn is output from shift register CCD1. Accordingly, from the sense amplifier circuit A, the diode G
A pixel signal having a level proportional to the level of the green light applied to Pn is output.

At time t4, when the timing signal φ2 is set to high level again, each pixel signal in each shift register is shifted again. At this time t4, the ji amplification signal is output from the shift register C0D2 formed by the photodiode BPn. Accordingly, the sensing amplifier circuit A
, a pixel signal having a level proportional to the level of the blue light irradiated to the diode BPn is output.

Thereafter, red, green, and blue pixel signals corresponding to each color pixel are sequentially supplied to the sense amplifier circuit A by the same operation.

That is, timing signals φ1 and φ are generated complementary to each other.
2, the lower and upper COD shift registers C0
Since the D2 and CGD I outputs are output alternately, the three primary color signals constituting each pixel are output as serial color signals in a repeating pattern of red, edge, and blue.

[Embodiment 2] FIG. 2 shows a block diagram of another embodiment of the present invention.

In this example, although not particularly limited, the photodiomids are arranged in two rows. The photodiode rows on the upper stage are connected to the C on the upper stage through respective transfer gate MOSFETs.
It is connected to each odd-numbered half-bit shift stage of the OD shift register CCD1.

The lower photodiode rows each have a transfer gate MO.
Lower stage CCD shift register CCD via 3FET
2 to each even-numbered half-bit shift stage. The photodiode is individually provided with the following color filters. That is, of the following three photodiodes that make up one pixel at the left end, the leftmost photodiode in the upper row is filtered with blue (B), and the leftmost photodiode in the lower row is filtered with green (G). . In addition, the second photodiode in the upper row is red (R).
can be filtered. Of the following three photodiodes constituting the second pixel, the second photodiode in the lower row is filtered with blue (B), and the third photodiode in the upper row is filtered with green CG'. ) can be filtered.

Further, a red (R) filter is applied to the third photodiode in the lower row. By repeating the same configuration (pattern) with two pixels as one set, each photodiode is provided with an individual color filter. As a result, similarly to the embodiment shown in FIG. The pixel signals are taken in in this order and output serially in synchronization with the high level of the clock signal φ1. On the other hand, the upper stage COD shift register CCDI
Pixel signals of green, red, and blue are taken in in the order of green, red, and blue from the odd-numbered stages, that is, from the right (last stage side) where one is vacant, and are output to the silua in synchronization with the high level of the clock signal φ2. Therefore, similarly to the embodiment shown in FIG. 1, the color signals constituting one pixel are serially output in the order of red, green, and blue using the clock signals φ1 and φ2.

〔effect〕

(l) The color signal is transferred from the CCD shift register to the CCD shift register while maintaining high resolution through an extremely RFI configuration in which the signals of the three photodiodes that make up the Kalani signal for one pixel are transferred to the CCD shift register in a fixed order. The effect is that it is possible to output the data serially.

(2) By arranging photodiodes in three rows, placing CCD shift registers above and below them, and setting the transfer path according to the transfer order of the CCD shift registers, the color signal for each pixel is serially transmitted. can be formed into In this case, since it is sufficient to provide a common color filter for each column, it is possible to easily set the color filters.

(3) The photodiode transfer path can be simplified by regularly transferring the signals from the photodiode array to the CCD shift register and by providing individual color filters for each photodiode according to the transfer order of the CCD shift register. This effect can be obtained.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without getting the gist of the invention. Nor. For example, a color filter can be formed integrally on a semiconductor substrate using photo-etching technology, or it can be formed in a predetermined pattern and then attached to the semiconductor substrate. Good too. Further, the CCD shift registers may be laid out in a meandering manner, and the pitch in the transfer direction may be substantially reduced to arrange the photodiodes at a high density.

By doing so, the resolution can be further increased.

Furthermore, by dividing the CCD shift registers arranged in a column into a plurality of sets and selectively supplying a shift clock signal to each set, the CCD shift registers are selectively operated in a fixed order for each divided set. It may also be something that allows you to do it. By doing so, the number of transfer stages of pixel signals to be transferred is reduced, thereby improving transfer efficiency, and the input capacitance of the shift clock terminal is also divided, resulting in high-speed operation.

[Application field]

The present invention can be widely used as a -dimensional color sensor, for example, in color facsimiles, color scanners, etc.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of this invention. FIG. 2 is a block diagram showing another embodiment of this invention. FIG. 3 is a timing diagram for explaining an example of its operation. It is. CCDI, CCD2...CCD shift register, A...
sense amplifier circuit

Claims (1)

[Claims] One pixel is composed of a photodiode array to which light is irradiated via color filters of one or three colors, and a CCD shift register to which a photoelectric conversion signal formed by the photodiode array is supplied. A CCD shift register that includes a transfer gate MOSFET that transfers photoelectric conversion signals corresponding to three colors to the CCD shift register in a predetermined order, and serially outputs the transferred pixel signals in accordance with a two-phase clock signal. A one-dimensional color sensor characterized by: 2. The one-dimensional color sensor according to claim 1, wherein the photodiode array is provided between a pair of CCD shift registers arranged in parallel.