JPS60163564A - Solid-state image sensor - Google Patents

Abstract

PURPOSE:To simplify the control with simple constitution by impressing a multi- phase clock pulse to plural gate electrodes for electric charge storage in a unit sensor chip arranged to one column in a prescribed order and impressing to othe column in opposite order. CONSTITUTION:The unit sensor chip is constituted in the method forming a biased potential barrier toward a photosensing section 1 in a substrate under electric charge storage gate electrodes 16-19. Plural unit sensor chips 2-5 are arranged in zigzag and in parallel with two columns 2, 4 and 3, 5. Multi-phase cock pulse is impressed to the electrodes 16-19 in the unit sensor chip of one column, e.g., 2, 4 in a prescribed order. The electrodes 16-19 in the unit sensor chip arranged to the other column, e.g., 3, 5, are impressed with the multi-phase clock pulse in opposite order to that of the columns 2, 4.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION The present invention relates to a solid state image sensor, particularly of the contact type, in a charge-coupled configuration.

[Technical background of the invention]

FIG. 1 is a plan view showing the configuration of a general contact type COD linear image sensor. This image sensor includes unit sensor chips 2 to 5 each having a photosensitive section 1 formed by linearly arranging a plurality of photosensitive pixels each made of, for example, a pn junction photodiode, on a substrate 6 made of, for example, ceramics. They are arranged in two rows in a staggered manner.

In an image sensor having such a configuration, the document whose optical pattern is to be read is sequentially moved in the Y direction in the figure, and the four optical turns are captured onto the sensor by a one-to-one equal-magnification imaging optical system. An image is formed to generate a signal charge in each photosensitive section 1 of each unit sensor chip 2 to 5 in accordance with the respective amount of light.

Furthermore, by reading and scanning this signal charge multiple times in the X direction in the figure, an electrical signal corresponding to the optical pattern for each scanning line is obtained.

By the way, in such an image sensor, in order to prevent reading of the optical pattern in the X direction from falling off, the unit sensor chips f2 to f5 are arranged in two rows in a staggered manner as shown in the figure, so that a portion of each photosensitive section 1 overlaps. has been done. For this reason,
The unit sensor chips 2, 4 and the unit sensor chips f3, 5 read out signals corresponding to optical patterns on mutually different scanning lines on the document. Therefore, optical 1 on a certain scan line? When the turn signal is read out by the unit sensor chips 2 and 4, it is necessary to hold the signals from the unit sensor chips f2 and 4 until the optical turn on this scanning line reaches the unit sensor chip 3.5. be. In the conventional image sensor, an external storage circuit is provided to hold this signal, and the signals read from the unit sensors 2 and 4 are sequentially stored in this storage circuit, and the signals read from the unit sensors 2 and 4 are sequentially stored in the storage circuit.
The stored signals on the scanning lines corresponding to the signals read out from 5 are read out from the storage circuit and subjected to signal processing to obtain signals corresponding to the optical patterns on each scanning line.

[Problems with background technology]

The conventional solid-state image sensor as described above requires an external memory circuit, and it is also conceivable to integrate this memory circuit within the unit sensors 2 and 4, for example. However, if the memory circuit is configured in the unit sensor chip f2.4, the configurations of the unit sensor chip f2.4 and the unit sensor chip f3.5 are different, and two types of unit sensor chips are required, which increases the manufacturing cost of the image sensor. This brings about a drawback. Furthermore, conventional image sensors have the disadvantage that the control required for processing to cause the storage circuit to store and read signals is complicated.

[Purpose of the invention]

This invention was made in consideration of the above-mentioned circumstances, and its purpose is to reduce the manufacturing cost by eliminating the need to provide an external memory circuit and consisting of only one type of unit sensor chip. The object of the present invention is to provide a solid-state image sensor that can be easily controlled.

[Summary of the invention]

In order to achieve the above object, the present invention includes one unit sensor, a photosensitive section formed by arranging a plurality of photosensitive pixels in a straight line, and a signal charge obtained from this photosensitive section that is sequentially transferred in a predetermined direction. a transfer register, a plurality of charge storage dart electrodes provided between the photosensitive section and the transfer register, each controlled by a multiphase clock pulse; A plurality of unit sensor chips are arranged in parallel in two rows in a staggered manner, and a plurality of charge storage darts in the unit sensor chips are arranged in one row. By sequentially applying the multi-phase clock pulses to the electrodes starting from the side closest to the transfer V register, signal charges corresponding to the light intensity and pattern on multiple scanning lines are stored for each charge storage within one cycle period of the clock pulses. The multiphase clock pulses are sequentially applied to the plurality of charge storage dart electrodes in the unit sensor tyranno arranged in the other column by moving the gate electrode by one position below the photosensitive section. By doing so, the signal charge corresponding to the optical pattern on one scanning line is transferred to the bottom of the charge storage dirt electrode near the transfer register through the bottom of the plurality of charge storage dirt electrodes within one cycle period of this clock signal. I have to.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. The solid-state image sensor according to the present invention is, for example, the contact type COD! shown in FIG. In constructing the J near image sensor, each of the unit sensor chips 2 to 5 is constructed as shown in the plan view of FIG. 2 and the sectional view of FIG. 3 taken along the line A-A'. This unit sensor chip uses, for example, a p-type silicon substrate 11, and on its surface region, a plurality of n+m+ regions 13, which together with the p-type silicon substrate 11 constitute a photosensitive pixel 12 consisting of a pn junction photodiode, are linearly arranged. ing. That is, as shown in FIG. 2, a plurality of photosensitive pixels 12 are arranged in a straight line to constitute the photosensitive section 1. A barrier electrode 14 is provided adjacent to the photosensitive portion 1, a storage electrode 15 is provided adjacent to the barrier electrode 14, and four storage electrodes 16 to 19 are provided adjacent to the storage electrode 15. . A shift electrode 20 is provided adjacent to the one memory electrode 19 . The barrier electrode 14, the storage electrode 15, the four memory electrodes 16 to 19, and the shift electrode 20 each have a control terminal 2.
1 to 27 are provided, and these electrodes are connected to the control terminal 2.
The signal charge generated in each photosensitive pixel 12 of the photosensitive section 1 is controlled by a constant DC voltage or clock pulse applied to the electrodes 1 to 27, and the signal charge generated in each photosensitive pixel 12 of the photosensitive section 1 is controlled by a potential well formed in the substrate 11 under each of the electrodes. Then, it is transferred to below the shift electrode 20. A readout CC adjacent to the shift electrode 20
A D register 30 is provided. This CCD register 30 is equipped with a plurality of transfer electrodes 35 to which any of the four-phase clock pulses applied to the control terminals 31 to 34 is supplied, and is configured according to the method of applying the four-phase clock pulse φa-1d. Then, the signal charges transferred from below the shift electrode 20 are sequentially transferred in the direction of Xl or the direction of X2 in the figure. Charge detection sections 36 and 37 for detecting signal charges and converting them into electrical signals such as voltage are provided at the front and rear ends of the CCD register 30.
The electrical signal converted at 6.37 is output from the output terminal 38.39. As shown in FIG.
This is a dirt electrode embedded in a silicon oxide film 41 provided on the substrate 1.

In the surface area of the substrate 11 corresponding to the four memory electrodes 16 to 19, high concentration p+ type regions 46 to 49 are provided only on the die region 13 side. Furthermore, a light shielding film 50 made of aluminum or the like is provided on the entire surface of the silicon oxide film 41, leaving only the position corresponding to the molded area 13. Although not shown, the barrier electrode 14, the storage electrode 15, the memory electrodes 16 to 19,
The potential well formed in the shift electrode 20 is
Each photosensitive pixel is separated by means such as a high-density area provided in 1.

4 unit sensor chips with the configuration shown in Figures 2 and 3.
When the image sensor shown in FIG.
The length is set to three times the length of the photosensitive pixel indicated by the dimensions in FIG.

In addition, in FIG. 1, the clear electrode 14 and the storage electrode 15 of the two unit sensor chips 2 and 4 arranged in one row are
Constant DC voltages V1 and V2 with different values are applied to the control terminals 21 and 22 of the memory electrodes 16 to 19, and four-phase voltages as shown in the timing chart of FIG. Clock Tsurus φm l-$m
4 is applied sequentially from the electrode 19, and a shift/solus φ as shown in FIG. 4 is applied to the control terminal 27 of the shift electrode 200. In addition, in the above two units (2) and sensor chips 2 and 4, four-phase clock pulses φa to φd are connected to the control terminals 31 and 30 so that the signal charges are transferred in the direction of X□ in FIG. 2 in the CCD register 30. ~3
4. In FIG. 1, the barrier electrodes 14 and the control terminals 21 and 22 of the storage electrodes 15 of the two unit sensor chips 3 and 5 arranged in the other column are connected to the same constant voltage as the one of the two unit sensor chips 762 and 4. A DC voltage of ■1°■ is applied, and four-phase clock pulses φm19m4 as shown in FIG. The control terminal 27 of No. 20 is also connected to a shift (as shown in FIG. 4) A? A pulse φ□ is applied. In addition, in the two unit sensor chips 3.5, the four-phase clock pulses φa to φd are connected to the control terminals 31 to φd so that the signal charge is transferred in the direction of X2 in FIG. 2 in the CCD register 30.
34. Here, the value of the DC voltage 1 is set smaller than the low level voltage vL of the clock pulses φm1 to φm4 in FIG. 4, and the value of the DC voltage V is set to φm.
The low level voltage vL of 1-4m4 is also set large.

Next, we will explain the operation of the apparatus configured as described above.
move sequentially in the direction. At this time, in each photosensitive section 1 of each unit sensor chip 2 to 5, a signal charge is generated according to the amount of light at that time.

5(,) to (C) are diagrams showing the potential states of the two unit sensor chips 2 and 4 in FIG. 1 at each time. FIG. 5(a) shows the timing at time t1 in FIG. At time t, the signal charge generated under the gauge region 13 exceeds the constant potential barrier 61 generated under the barrier electrode 15 and the constant potential well generated under the storage electrode 15. A signal charge Q4 corresponding to the optical signal on the current scan line is accumulated in this well 62. Further, at this time, the clock pulse φml-4m4 is set to a voltage ① larger than O, and potential wells 63 to 66 are formed below the p1 storage electrodes 16 to 19. In addition, each memory electrode 16 to 1
Since cod-shaped regions 46 to 49 are provided in the surface region of the substrate 11 below 9, t? Potential barriers (potential barriers) 67 to 70 are formed, and the signal charge Q5 before the -scanning line, the signal charge Q2 before two scanning lines, and the signal charge Q1 before three scanning lines are separated by these potential barriers 67 to 70. It is pre-stored in potential wells 63-65.

FIG. 5(b) shows the timing at time t2 in FIG. 4 when the clock pulse φm1 is set to the high voltage 8. At this time t2, the storage electrode 19 is brought to a high voltage, so the potential well 66 and the barrier 70 below this electrode move downward in the figure as a whole. Then, the signal charge Q1 that has been stored in the adjacent potential well 65 flows into the potential well 66 below this electrode 19. Below, clock/4'rusφmfifφn1llφm
4 is sequentially applied to a high voltage ■□, the signal charges Q, ~Q accumulated in the potential wells 64 to 62
4 is transferred into adjacent potential wells 65-63.

FIG. 5(,) shows time t in FIG. 4 when the clock pulse φm4 is set to a high voltage vH and then set to a low voltage vL again.
This is from the time of . At time t3, each of the signal charges Q4 to Q has moved to the right by one potential well, compared to the time t1. That is, in these two unit sensor chips 2 and 4, each signal charge increases by 1 per cycle of clock pulses φm1 to φm4.
move by one potential well.

Thereafter, when the shift pulse φSH is set to a high voltage vH at time t in FIG. The signal charge Q1 that has been stored passes under the shift electrode and moves under the transfer electrode 35 of the CCD register 30.

Such movement of the signal charges occurs in parallel to the signal charges obtained by all the photosensitive pixels 12 in the photosensitive section 1.

The signal No. 2 charges that have moved below each transfer electrode 35 are then transferred to C
are sequentially transferred in the direction of the X direction within the CD register 30,
The charge detection section 37 converts the signal into an electrical signal and outputs it from the output terminal 39. In other words, the above unit sensor chip 2゜4
The electrical signal from is delayed by three scanning lines.

By the way, as mentioned above, since the distance between the photosensitive parts of the unit sensor 2.3 is three times the length L of the photosensitive pixel, the signal charge read in a certain cycle with the unit sensor tick f2 or f4. is deposited in the potential well 66 under the storage electrode 19, the scanning line position of the document corresponding to this signal charge is determined by the unit sensor chips 3, 5.
reaches the photosensitive section 1. At this time, each unit sensor search, f
In the photosensitive section 1 of 3.5, signal charges are generated according to the amount of light at that time.

FIGS. 6(a) and 6(b) are diagrams showing the potential states of the two unit sensor chips 3 and 5 at each time. FIG. 6 (=) is at time t1 in FIG. At this time t1, as in the case of the two unit sensor chips 7 degrees 2 and 4, the signal charge generated under the meter area 13 exceeds the constant potential barrier 61 generated under the barrier electrode 14 and accumulates. Flows into a constant potential well 62 occurring under the electrode 15,
A signal charge QU' corresponding to the optical signal on the current scanning line is accumulated in this well 62. After that, the four-phase clock pulses φm, to φm4 are sequentially set to a high voltage V, thereby causing a signal charge QU' to be accumulated in the well 62. , since wells and barriers with a potential equivalent to that occurring under the storage electrode 19 in FIG. 5(b) are sequentially formed under the storage electrodes 16 to 19, this corresponds to time t3 in FIG. In FIG. 6(b), the signal charge Q
□' is connected to the memory electrode 19 through three potential wells.
It is stored in the lower potential well 66. That is, in these two unit sensor chips 3 and 5, the signal charge obtained in each photosensitive pixel moves to below the storage electrode 19 during one cycle period of clock pulses φm□ to φm4. After this, when the shift pulse φ8H is set to a high voltage of 9 at time t4 in FIG.
The signal charges Q,' stored therein pass under the shift electrode and move under the transfer electrode 35 of the COD register 30.

Such movement of the signal charges occurs in parallel to the signal charges obtained by all the photosensitive pixels 12 in the photosensitive section 1.

The signal charges that have moved below each transfer electrode 35 are then transferred to the CC
It is sequentially transferred in the direction of X2 within the D register 30, converted into an electrical signal by the charge detection section 36, and outputted from the output terminal 38. That is, the electrical signals from the unit sensor chips 3 and 5 are output without being delayed by even one scanning line.

By the way, in two unit sensor chips 3.5, n
``During one cycle period in which the signal charge generated under the mold region 13 moves and is accumulated under the storage electrode 19, the signal charge accumulated under the storage electrode 18 in the other two unit sensor chips f2 and 4 moves to the storage electrode 19. Moved and accumulated under 19.

Then, when the shift pulse φ is set to a high voltage vH,
Two unit sensors 76at, s and 2, respectively
The signal charge under each storage electrode 19 of 4 is stored in each COD register 3.
Transferred to 0. For this reason, two unit sensor chips 3
, 5 and the electrical signals output from the two unit sensor chips 2 and 4 correspond to optical signals on the same scanning line of the original. Therefore, after this, from the four unit sensor chips 2 to 5 arranged as shown in FIG. output via

As described above, according to the above embodiment, a signal corresponding to an optical pattern can be obtained without providing an external storage circuit. Also, unit sensor tick 7',? , 4 and 3.
Comparing the noise component due to dark current generated in 5 and 5, the noise component generated in unit sensor chip 7° 2° 4 is - time required for scanning Tint, photosensitive pixel 12, barrier electrode 1
If the dark current generated under 4 and storage electrode 15 is 1, and the dark current generated under storage electrodes 16 to 19 is I2 to 2, then Tint(II +Iz +Is +Ia +Is
). On the other hand, since the unit sensor steps 3 and 5 read out the dark current under all the memory electrodes 16 to 19 in one scan, the generated noise component is Tint(11
+"x + Is + Ia + Is). That is, the noise components due to the dark current generated in the unit cell/satches f2, 4 and 3, 5 are the same.

Therefore, the output signals of the sensor chips 2 to 5 are always balanced including noise components, which is advantageous for subsequent signal processing. Furthermore, according to the above embodiment,
Since all of the unit sensor chips 2 to 5 can have the same configuration and there is no need to prepare two different types of chips, the manufacturing cost can be reduced. In addition, each memory electrode 16 to 16 in the unit sensor chips 2, 4 and 3, 5
19 uses the same clock pulse, chips f2, 4 and f3, 5 can be driven by simply changing the pulse wiring, thereby simplifying the control.

It goes without saying that this invention is not limited to the first embodiment described above, and that various modifications are possible. For example, in the above embodiment, each unit sensor chip is provided with four memory electrodes.
It is preferable to select at least (m+1) of these in accordance with the distance between the photosensitive parts of the two rows of unit sensor steps in the Y direction, and for the required number of delayed scanning lines m.

Further, in the above embodiment, potential barriers 67 to 70 for separating potential wells 63 to 66 formed in each storage electrode 16 to 19 are provided in the surface area of the substrate 11.
+ One-type regions 46 to 4 provided only on the side of the mold region 13
9, this may be realized by changing the thickness of the silicon oxide film 4 or by providing an n-type region in a region of the substrate 11 that is not the potential barrier 67 to 70. Furthermore, memory electrodes 16 to 19
We have explained the case where it appears as a single electrode, but this is also a so-called 2-phase CC by connecting different electrodes together.
It may be configured similarly to the electrode D. In addition, the memory electrode 16
.about.19 and CCD register 30 may be provided with embedded channels. Furthermore, although the case where the CCD register 30 is provided with charge detection sections 36 and 37 at both ends has been described, these may be provided only on one side. However, in this case, it is necessary to prepare two types of unit sensor chips whose charge detection sections are on opposite sides.

〔Effect of the invention〕

As explained above, according to the present invention, there is no need to provide an external memory circuit, and the manufacturing cost can be reduced by using only one type of unit sensor chip, and control can be easily performed. It is possible to provide a solid-state image sensor that can

[Brief explanation of the drawing]

Fig. 1 is a plan view of a general contact type COD IJ near image sensor, Fig. 2 is a plan view showing one unit sensor chip according to the present invention, and Fig. 3 is a plan view taken along line A-A' in Fig. 2. 4 is a timing chart showing control signals used in the unit sensor chip shown in FIG. 2, and FIGS. 5 and 6 are potential diagrams for explaining the operation of the unit sensor chip shown in FIG. 2, respectively. FIG. DESCRIPTION OF SYMBOLS 1... Photosensitive part, 2-5... Unit sensor chip, 11
...p-type silicon substrate, 12...photosensitive pixel, 13.
... Cod-shaped region, 14 ... Barrier electrode, 15 ... Storage electrode, 16 to 19 ... Memory electrode, 20 ... Shift electrode, 30 ... CCD register, 36.37 ... Charge Detection unit, 46-49...p+ type territory applicant patent attorney Takehiko Suzue Figure 3 Figure 4 t+ t2t3t4 Figure 5

Claims (3)

[Claims] (1) A photosensitive section consisting of a plurality of photosensitive pixels arranged in a straight line,
A transfer register that sequentially transfers signal charges obtained by the photosensitive section in a predetermined direction, and a plurality of charge storage dirt electrodes provided between the photosensitive section and the transfer register, each controlled by each multiphase clock pulse. , one unit sensor chip is constructed by means of forming potential barriers biased toward the photosensitive section in the substrate under each of the charge storage dirt electrodes, and a plurality of unit sensor chips are arranged in a staggered manner.
The multiphase clock pulses are applied in a certain order to the plurality of charge storage dirt electrodes in the unit sensor chips arranged in one column, and the plurality of charge storage dirt electrodes are arranged in parallel to the other column. A solid-state image sensor characterized in that the multiphase clock pulses are applied to the plurality of charge storage ff-) electrodes in the unit sensor chips arranged in columns in the opposite order to the above. . (2) The distance between the photosensitive parts of the two unit sensor chips arranged in the one and the other columns is set to m times the length of the photosensitive pixel (m is an integer), and The solid-state image sensor according to claim 1, wherein the number of dart electrodes is at least (m+1). (3) The solid-state image sensor according to claim 1, wherein the transfer register is oriented in the direction of charge transfer.