JPS58180060A - Charge coupled device - Google Patents

Abstract

PURPOSE:To enable to operate the charge coupled device at a high speed even when input capacitance is large by a method wherein only the final stage gate of transfer gates is made to use insidely generated timing. CONSTITUTION:The final gate phi1L of the charge transfer electrodes is made to differ from the usual device, and the waveform is formed on a semiconductor substrate to be supplied to the gate electrode phi1L. The timing margins of signals phiR, phi1 are not necessitated because the falling of the signal phi1L is formed using timing of the signal phiR. Because the signal phi1 is supplied only to the final stage gate, load capacitance is small, gentle falling line of the signal phi1 can be made steep at the signal phi1L, and delay time up to times t1-t4 can be shortened extremely.

Description

[Detailed Description of the Invention] Currently, charge-coupled devices are used as optical sensors in facsimiles, T
・■・It is used in many fields such as cameras and measurements. In particular, the demand for high-speed operation has been increasing recently. However, in a charge-coupled device, the transfer channel region is entirely formed of a gate electrode, and the input capacitance of the main clock system is much larger than that of a conventional semiconductor device. Therefore, since the input capacitance is large, the raw input waveform within the semiconductor device becomes a constraint for high-speed operation. We have investigated the reason why high-speed operation is not achieved due to the input waveform sloppiness, and have invented a charge-coupled device that is not affected by the input waveform sloppiness.

SUMMARY OF THE INVENTION An object of the present invention is to provide a charge-coupled device that can operate at high speed despite having a large input capacitance.

A feature of the present invention is that a large number of gate electrodes are repeatedly arranged on a semiconductor substrate via thin insulators, and each electrode is connected to a plurality of clock supply lines at regular intervals to transfer signal charges. In a charge-coupled device, a charge-coupled device is supplied from a driver newly formed on a semiconductor substrate using timings of the same phase among the plurality of clock supply lines, limited to the gate electrode at the final stage of the repeating electrodes. It is in.

First, a general charge detection operation of a charge coupled device will be explained with reference to FIG. FIG. 1(a) shows a cross-sectional view of a charge detection section of a charge coupled device. An impurity layer 2 of the same conductivity type as the semiconductor substrate 1 for charge transfer and an impurity layer 3 of the opposite conductivity type to the impurity layer for a barrier are formed in the semiconductor substrate 1. Next, a brief explanation will be given using the potential well of l/X1 diagram (b). First, the potential relationship in which the charge Q is stored in the final stage electrode φIL for charge transfer is shown at time t1. Time t! Then, at time 1 and charge transfer electrode φ2. The phase relationship of φIL is reversed, and therefore the relative relationship of potential depths is also reversed. That is, the gate electrode φI
The potential well below L is deep during load storage, but transfer to the charge detection unit 5 begins when the potential well below the gate electrode becomes shallower than the potential well below the output gate VOG. .

Now, using Fig. 2, we will explain in detail the delay until the charge under the final gate reaches the charge detection section 5 through the output gate. Reset tO~t1゜Then, at t2, the potential of the final gate φxL (in the case of Fig. 3, the timing of φIL is the conventional type and is the same as φ1) begins to fall and becomes the same level as the output gate potential.From ts to the above-mentioned The charge under the gate begins to flow to the charge detection section and ends at time t4, and the output is held until t5 when the next reset begins. 1o
One cycle is completed at -i5. To do fast operation here (.

It is necessary to make the time of ~is as short as possible.

-1 Considering the post-processing of the output signal, the output holding time is 14 to 1
It is preferable that the period of 5 minutes be as long as possible. That is, it is necessary to make the time from t0 to t4 as short as possible.

Each time period from 1O to i4 will be considered. First to~~
11 is the time to reset the charge detection unit 5, which varies depending on the device design, but is usually 10 n1llc to 3 Q Hm.
A minimum of about c is required. Further, for tl- to 3, a margin of about 1Qnsec to 30Bsec is required between the reset pulse and the timing at which φl starts shifting.

Further, the period between t2 and t13 is the rounding of the clock waveform φ1, which becomes large especially when the input capacitance is large as in a charge-coupled device. This time varies depending on the input capacity, but generally 59QfRC
Some objects require several hundred ns11c. Between t3 and t4, the charge is φ in Figure 1111 (11)
The time required to transfer the charge from the bottom of the IL gate to the bottom of the VOG gate to the charge detection section, usually 20 n11ec~
It takes about 5 Q n1jec.

As mentioned above, the time from tO to t4 is l Q Q H8
1X: to several hundred nspci [L
vinegar. The present invention enables high-speed operation by significantly improving the delay between 1l and i2, which is the timing margin between φB and φ1, and the delay between t2 and t3 due to the rounding of the waveform of φ1. .

Next, the present invention will be explained in detail with reference to FIG. 3. First, the final gate φIL of the charge transfer electrode is
The waveform shown in the figure is formed on the semiconductor substrate to form the gate electrode φIL.
supply to. An example of a logic circuit that forms the waveform is shown in FIG. It is obvious in the art that what is possible with this logic circuit formed using the timings of φR and φ41 will not be described in detail.

Now, in the method shown in Figure 3, φ in the conventional type shown in Figure 2 is
The timing margins of R and -1 are not required because the falling edge of φIL is formed using the timing of φR. Moreover, since the slow fall of φl is supplied only to the final stage gate in φIL, the load capacitance is small and it is possible to make the fall steep. In this way, in the present invention, the delay time up to 1f-i4 can be extremely shortened.

An embodiment of the present invention has been described above, and the purpose of the present invention is to use internally generated timing that is different from that of other transfer gates only for the last stage of transfer gates. Although this was done using the timing of the wire φR, it goes without saying that the timing tube may also be used for the fall of φ1, for example.

[Brief explanation of drawings]

FIG. 1(a) is a sectional view of the detection section of the charge coupled device. FIG. 1(b) is a diagram illustrating the charge transfer operation of the charge transfer device using a potential well. FIG. 2 is a diagram illustrating each timing of an output waveform of a conventional charge-coupled device. FIG. 3 is a diagram illustrating each timing of the output waveform of the charge-coupled device 3 of the present invention.02 FIG. 4 is a diagram showing a logic circuit according to an embodiment of the present invention. In the figure, 1... is a conductor substrate, and 2 and 3 are impurity layers. B Figure 1 (Grade 1 Figure 1 (b) Figure 2 11 t+ 13t4 Go 3 Zusenen 4

Claims (1)

[Claims] In a charge-coupled device that transfers signal charge, a large number of gate electrodes are repeatedly arranged on a semiconductor substrate via thin insulating films, and each electrode is connected to a plurality of clock supply lines at a constant period, thereby transferring signal charges. A charge-coupled device characterized in that p is supplied only to the last stage gate electrode of the return electrode from a driver newly formed on a semiconductor substrate using the timing of an in-phase line among the plurality of clock supply lines.