JPS58180060A - Charge coupled device - Google Patents
Charge coupled deviceInfo
- Publication number
- JPS58180060A JPS58180060A JP57063140A JP6314082A JPS58180060A JP S58180060 A JPS58180060 A JP S58180060A JP 57063140 A JP57063140 A JP 57063140A JP 6314082 A JP6314082 A JP 6314082A JP S58180060 A JPS58180060 A JP S58180060A
- Authority
- JP
- Japan
- Prior art keywords
- charge
- signal
- coupled device
- timing
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012546 transfer Methods 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 abstract description 2
- 238000001514 detection method Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 239000012535 impurity Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 235000021419 vinegar Nutrition 0.000 description 1
- 239000000052 vinegar Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/762—Charge transfer devices
- H01L29/765—Charge-coupled devices
- H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
- H01L29/76816—Output structures
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】
現在電荷結合素子は光センサーとしてファクシミリ、T
・■・カメラ、および計測等多方面に渡り使用されてい
る。特に最近高速動作の要望が強まシつつめる。しかる
に、電荷結合素子は、転送チャンネル領域が全てゲート
電極で形成されるものであシ、メインクロック系の入力
容量は従来の半導体装置に比べ非常に大きい。従って高
速動作を行う上で前記入力容量が大きい為に入力波形の
半導体装置内でのなま)が制約となる。我々は前記入力
波形のなまシが高速動作に及ばず原因を究明し、前記入
力波形のなま〕に影譬されない電荷結合装置を発明する
に至った。[Detailed Description of the Invention] Currently, charge-coupled devices are used as optical sensors in facsimiles, T
・■・It is used in many fields such as cameras and measurements. In particular, the demand for high-speed operation has been increasing recently. However, in a charge-coupled device, the transfer channel region is entirely formed of a gate electrode, and the input capacitance of the main clock system is much larger than that of a conventional semiconductor device. Therefore, since the input capacitance is large, the raw input waveform within the semiconductor device becomes a constraint for high-speed operation. We have investigated the reason why high-speed operation is not achieved due to the input waveform sloppiness, and have invented a charge-coupled device that is not affected by the input waveform sloppiness.
本発明は入力容量が大きいにもかかわらず高速動作を可
能とする電荷結合装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a charge-coupled device that can operate at high speed despite having a large input capacitance.
本発明の特徴は、半導体基板上に薄い絶縁jIを介して
ゲート電極を多数〈り返し配置し、それぞれの電極が一
定の周期でそれぞれ複数から成るクロック供給線に結線
され、信号電荷を転送する電荷結合素子において、前記
くp返し電極の最終段のゲート電極に限シ前記複数から
成るクロック供給線のうち同相−のタイミングを用いて
新たに半導体基板上で形成したドライバーから供給する
電荷結合装置にある。A feature of the present invention is that a large number of gate electrodes are repeatedly arranged on a semiconductor substrate via thin insulators, and each electrode is connected to a plurality of clock supply lines at regular intervals to transfer signal charges. In a charge-coupled device, a charge-coupled device is supplied from a driver newly formed on a semiconductor substrate using timings of the same phase among the plurality of clock supply lines, limited to the gate electrode at the final stage of the repeating electrodes. It is in.
まず電荷結合装置の一般的な電荷検出動作を第1図を用
いて説明する。第1図(a)に電荷結合装置の電荷検出
部の断面図を示す。半導体基板lに堀込み電荷転送用の
半導体基板1と同導電型の不純物層2およびバリヤー用
に前記不純物層と反対導電型の不純物層3が形成される
。次にl/X1図(b)の電位の井戸を用いて簡単に説
明する
まず電荷転送の最終段電極φILに電荷Qが蓄えられて
いる電位関係を時刻t1で示す。時刻t!では時刻1と
電荷転送電極φ2.φILの位相関係は逆になり従って
電位の深さの相対関係も逆になる。即ちゲート電極φI
L下の電位の井戸at荷蓄槓時においては深いが、電荷
検出部5へ転送するには前記ゲート電極下の電位の井戸
がアウトプットゲートvOG下の電位の井戸より浅くな
った時点で始まる。First, a general charge detection operation of a charge coupled device will be explained with reference to FIG. FIG. 1(a) shows a cross-sectional view of a charge detection section of a charge coupled device. An impurity layer 2 of the same conductivity type as the semiconductor substrate 1 for charge transfer and an impurity layer 3 of the opposite conductivity type to the impurity layer for a barrier are formed in the semiconductor substrate 1. Next, a brief explanation will be given using the potential well of l/X1 diagram (b). First, the potential relationship in which the charge Q is stored in the final stage electrode φIL for charge transfer is shown at time t1. Time t! Then, at time 1 and charge transfer electrode φ2. The phase relationship of φIL is reversed, and therefore the relative relationship of potential depths is also reversed. That is, the gate electrode φI
The potential well below L is deep during load storage, but transfer to the charge detection unit 5 begins when the potential well below the gate electrode becomes shallower than the potential well below the output gate VOG. .
さて第2図を用いて最終ゲート下の電荷がアウトプット
ゲートを通って電荷検出部5へ到達するまでの遅れにつ
いて詳しく説明する0
に電荷検出部5をリセットゲートφRを介して一定の電
位にリセットするtO〜t1゜その後t2で最終ケート
φxL(第3図の場合はφILのタイミングは従来
型でφ1と同じとする)の電位が下がりはじめアウトプ
ットゲートの電位と同じレベルになる tsから前記ゲ
ート下の電荷は電荷検出部へ流れはじめ時刻t4で終シ
、次のリセットが始まるt5迄出力は保持される。1o
−i5で1サイクルが完了する。ここで高速動作を行う
には(。Now, using Fig. 2, we will explain in detail the delay until the charge under the final gate reaches the charge detection section 5 through the output gate. Reset tO~t1゜Then, at t2, the potential of the final gate φxL (in the case of Fig. 3, the timing of φIL is the conventional type and is the same as φ1) begins to fall and becomes the same level as the output gate potential.From ts to the above-mentioned The charge under the gate begins to flow to the charge detection section and ends at time t4, and the output is held until t5 when the next reset begins. 1o
One cycle is completed at -i5. To do fast operation here (.
〜is の時刻をできるだけ短くする必要がある。It is necessary to make the time of ~is as short as possible.
−1出力信号の後処理を考えると出力保持時間14〜1
5間はできるだけ長い方が好ましい。即ちt0〜t4の
時間をできるだけ短くする必要がある。-1 Considering the post-processing of the output signal, the output holding time is 14 to 1
It is preferable that the period of 5 minutes be as long as possible. That is, it is necessary to make the time from t0 to t4 as short as possible.
1O−i4迄の各時間について検討する。まずto〜〜
11間は電荷検出部5をリセットする時間でテバイス設
計によjシ異るが通常10 n1llc〜3 Q Hm
c程度は最低必要とされる。またtl−を3間はリセッ
トパルスとφl下がシ始めるタイミングのマージンでや
はり1Qnsec〜30Bsec程度は必要とされる。Each time period from 1O to i4 will be considered. First to~~
11 is the time to reset the charge detection unit 5, which varies depending on the device design, but is usually 10 n1llc to 3 Q Hm.
A minimum of about c is required. Further, for tl- to 3, a margin of about 1Qnsec to 30Bsec is required between the reset pulse and the timing at which φl starts shifting.
又t2〜13間はクロック波形φ1のなまりで特に電荷
結合装置のように入力容量が大きい場合には大きくなる
。この時間は入力容量により異るが一般に59QfRC
からものによっては数100ns11c要すものがある
。t3〜t4間は電荷が1111図(11)においてφ
ILゲート下からVOGゲート下を介して電荷検出部へ
転送するに要する時間であ多、通常20 n11ec〜
5 Q n1jec程度要する。Further, the period between t2 and t13 is the rounding of the clock waveform φ1, which becomes large especially when the input capacitance is large as in a charge-coupled device. This time varies depending on the input capacity, but generally 59QfRC
Some objects require several hundred ns11c. Between t3 and t4, the charge is φ in Figure 1111 (11)
The time required to transfer the charge from the bottom of the IL gate to the bottom of the VOG gate to the charge detection section, usually 20 n11ec~
It takes about 5 Q n1jec.
以上述べたようにtO〜t4の時間はl Q Q H8
1X:からデバイスによっては数100nspci[L
す。本発明は前記10〜14間の遅れでφBとφ1のタ
イミングマージンである1l−i2間およびφ1の波形
のなまりによる遅れt2〜t3間を大幅に改善して高速
動作を可能とするものである。As mentioned above, the time from tO to t4 is l Q Q H8
1X: to several hundred nspci [L
vinegar. The present invention enables high-speed operation by significantly improving the delay between 1l and i2, which is the timing margin between φB and φ1, and the delay between t2 and t3 due to the rounding of the waveform of φ1. .
次に第3図を用いて本発明の詳細な説明するOまず電荷
転送電極の最終ゲートφILを従来の装置とは異り第3
図に示す波形を半導体基板上で形成いゲート電極φIL
に供給する。該波形を形成する論理回路の一例を第4図
に示す。φRおよびφ41のタイミングを用いて形成す
る本論理回路で可能であることは当業界では自明である
から詳しくは述べない。Next, the present invention will be explained in detail with reference to FIG. 3. First, the final gate φIL of the charge transfer electrode is
The waveform shown in the figure is formed on the semiconductor substrate to form the gate electrode φIL.
supply to. An example of a logic circuit that forms the waveform is shown in FIG. It is obvious in the art that what is possible with this logic circuit formed using the timings of φR and φ41 will not be described in detail.
さて第3図の方式においては従来型の第2図におけるφ
Rおよび−1のタイミングマージンは、φILの立下が
シはφRのタイミングを用いて形成するから必要としな
い。又φlの立ち下がりのなまシはφILにおいては最
終段ゲートだけに供給するものであるから負荷容量が小
さく急峻にすることが可能となる。このようにして本発
明においては1f−i4迄の遅れ時間を極めて短くする
ことができる。Now, in the method shown in Figure 3, φ in the conventional type shown in Figure 2 is
The timing margins of R and -1 are not required because the falling edge of φIL is formed using the timing of φR. Moreover, since the slow fall of φl is supplied only to the final stage gate in φIL, the load capacitance is small and it is possible to make the fall steep. In this way, in the present invention, the delay time up to 1f-i4 can be extremely shortened.
以上本発明の一実施例について述べたが本発明の目的は
転送ゲートの最終段のゲートだけ他の転送ゲートとは異
シ内部発生タイミングを用いることにあり、前記実施例
においてはφILの立ち下がヤ金φRのタイミングを用
いて行ったが、例えばφ1の立ち下がシタイミング管用
いても良いことはいうまでもない。An embodiment of the present invention has been described above, and the purpose of the present invention is to use internally generated timing that is different from that of other transfer gates only for the last stage of transfer gates. Although this was done using the timing of the wire φR, it goes without saying that the timing tube may also be used for the fall of φ1, for example.
第1図(a)は電荷結合装置の検出部の断面図である。
第1図(b)は電荷転送装置の電荷転送動作を電位の井
戸を用いて説明した図である。第2図は従来型電荷結合
装置の出力波形の各タイミングを説明した図である。第
3図は本発明の電荷結合装置 3の出力波形の各
タイミングを説明した図である0 2第4図は本
発明の一実施例による論理回路を示す図である。
尚、図において1・・・・・・牛導体基板、2,3は不
純物層である。
B
第1 図(勾
第 1 図(b)
第2図
11
t+ 13t4
郷3図
幣4図FIG. 1(a) is a sectional view of the detection section of the charge coupled device. FIG. 1(b) is a diagram illustrating the charge transfer operation of the charge transfer device using a potential well. FIG. 2 is a diagram illustrating each timing of an output waveform of a conventional charge-coupled device. FIG. 3 is a diagram illustrating each timing of the output waveform of the charge-coupled device 3 of the present invention.02 FIG. 4 is a diagram showing a logic circuit according to an embodiment of the present invention. In the figure, 1... is a conductor substrate, and 2 and 3 are impurity layers. B Figure 1 (Grade 1 Figure 1 (b) Figure 2 11 t+ 13t4 Go 3 Zusenen 4
Claims (1)
り返し配置し、それぞれの電極が一定の周期でそれぞれ
複数から成るクロック供給線に結線され、信号電荷を転
送する電荷結合素子において、前記く夛返し電極の最終
段のゲート電極に限p、前記複数から成るクロック供給
線のうち同相線のタイミングを用いて新たに半導体基板
上で形成したドライバーから供給することを特徴とする
電荷結合装置。In a charge-coupled device that transfers signal charge, a large number of gate electrodes are repeatedly arranged on a semiconductor substrate via thin insulating films, and each electrode is connected to a plurality of clock supply lines at a constant period, thereby transferring signal charges. A charge-coupled device characterized in that p is supplied only to the last stage gate electrode of the return electrode from a driver newly formed on a semiconductor substrate using the timing of an in-phase line among the plurality of clock supply lines.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57063140A JPS58180060A (en) | 1982-04-15 | 1982-04-15 | Charge coupled device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57063140A JPS58180060A (en) | 1982-04-15 | 1982-04-15 | Charge coupled device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58180060A true JPS58180060A (en) | 1983-10-21 |
JPH024141B2 JPH024141B2 (en) | 1990-01-26 |
Family
ID=13220652
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57063140A Granted JPS58180060A (en) | 1982-04-15 | 1982-04-15 | Charge coupled device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58180060A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62190876A (en) * | 1986-02-18 | 1987-08-21 | Matsushita Electronics Corp | Charge transfer device |
JPS63296276A (en) * | 1987-05-27 | 1988-12-02 | Nec Corp | Method of driving charge transfer device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS503789A (en) * | 1973-05-15 | 1975-01-16 | ||
JPS5619666A (en) * | 1979-07-27 | 1981-02-24 | Nec Corp | Driving means of charge coupled element |
-
1982
- 1982-04-15 JP JP57063140A patent/JPS58180060A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS503789A (en) * | 1973-05-15 | 1975-01-16 | ||
JPS5619666A (en) * | 1979-07-27 | 1981-02-24 | Nec Corp | Driving means of charge coupled element |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62190876A (en) * | 1986-02-18 | 1987-08-21 | Matsushita Electronics Corp | Charge transfer device |
JPS63296276A (en) * | 1987-05-27 | 1988-12-02 | Nec Corp | Method of driving charge transfer device |
Also Published As
Publication number | Publication date |
---|---|
JPH024141B2 (en) | 1990-01-26 |
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