JPH024141B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION At present, charge-coupled devices are used as optical sensors in a wide range of applications such as facsimiles, TV cameras, and measurement. In particular, the demand for high-speed operation has been increasing recently. However, in a charge-coupled device, the transfer channel region is entirely formed of the gate electrode, and the input capacitance of the main clock system is much larger than that of conventional semiconductor devices. Therefore, since the input capacitance is large, the rounding of the input waveform within the semiconductor device becomes a constraint for high-speed operation. We have investigated the cause of the effect of the input waveform rounding on high-speed operation, and have invented a charge-coupled device that is not affected by the input waveform roundness.

First, a general charge detection operation of a charge coupled device will be explained with reference to FIG. FIG. 1a shows a cross-sectional view of the charge detection section of the charge-coupled device. An impurity layer 2 of a conductivity type opposite to that of the semiconductor substrate 1 for charge transfer is embedded in a semiconductor substrate 1, and an impurity layer 3 of a conductivity type opposite to the impurity layer is formed for a barrier. Next, a brief explanation will be given using the potential well shown in FIG. 1b.

Each gate electrode receives a clock pulse φ ₁ of opposite phase,
φ ₂ is applied alternately to cause charge to be transferred under the gate electrode. FIG. 1b shows the potential relationship at time T _A when the clock pulse φ ₁ is applied to the final gate electrode and the charge Q is stored. At time T _B , the phase relationship between time T _A and clock pulses φ ₂ and φ ₁ is reversed, and therefore the relative relationship between the depths of the potentials under the gate electrodes to which these clock pulses φ ₂ and φ ₁ are applied is also reversed. In other words, the potential well under the final gate electrode _φ1 is deep during charge accumulation, but the potential well under the final gate electrode φ1 is
Transfer to VOG begins when the potential well below the gate electrode becomes shallower than the potential well below the output gate VOG.

Now, with reference to FIG. 2, the delay until the charge under the final gate electrode reaches the charge detection section 5 through the output gate will be explained in detail.

First, while the charge is stored under the final gate electrode to which the clock pulse φ ₁ is applied, the charge detection unit 5 is reset to a constant potential via the reset gate electrode to which the reset pulse φ _R is applied _.
t1 . After that, at _t2 , the potential of the clock pulse _φ1 begins to drop and becomes the same level as the output gate potential.At _t3 , the charge under the final gate electrode begins to flow to the charge detection section, ending at time _t4 , and the next reset begins at t3. Output is maintained until ₅ . One cycle is completed from _t0 to _t5 . In order to perform high-speed operation here, it is necessary to make the time from t ₀ to _{t 5} as short as possible. On the other hand, considering the post-processing of the output signal, it is preferable that the output holding time t ₄ to t ₅ be as long as possible. That is, it is necessary to make the time from t ₀ to _{t 4} as short as possible. Verification is performed at each time from t ₀ to _{t 4} . First, the time period between t ₀ and t ₁ is the time required to reset the charge detection section 5, and although it varies depending on the device design, a minimum of about 10 nsec to 30 nsec is usually required. Further, between _t1 and _t2, a margin of about 10nsec to 30nsec is required between the reset pulse and the timing at which the clock pulse _φ1 starts to fall. or
Between _t2 and _t3 , the waveform of the clock pulse _φ1 is rounded, which becomes large especially when the input capacitance is large, such as in a charge-coupled device. This time varies depending on the input capacity, but generally it takes from 50 nsec to several 100 nsec depending on the type. The period between _t3 and _t4 is the time required for the charge to be transferred from under the final gate electrode to which the clock pulse _φ1 is applied to the charge detection section via the output gate VOG in Figure 1a, and is usually
It takes about 20n sec to 50n sec.

As mentioned above, the time from t ₀ to _{t 4} takes from 100 ns to several 100 ns depending on the device.

In contrast, the present invention eliminates the delay between t ₁ and _{t 2} which is the timing margin between φ _R and φ ₁ and the delay between t ₂ and _t 3 due to the rounding of the waveform of φ ₁ among the delays between t ₀ and t ₄ . The object of the present invention is to provide a charge-coupled device that is significantly improved and can operate at high speed despite having a large input capacitance.

According to the present invention, a large number of gate electrodes are repeatedly arranged on a semiconductor substrate with thin insulating films interposed therebetween, and a clock pulse is supplied to each electrode so that charges are transferred from the semiconductor substrate under the gate electrode to the charge detection section. In a charge-coupled device in which the charge transferred to the charge detection section is removed from the charge detection section by a reset pulse, the charge detection section of the gate electrode closest to the charge detection section includes:
A charge-coupled device is provided in which a pulse is provided whose rising edge is synchronized with the clock pulse and whose falling edge is synchronized with the trailing edge of the reset pulse.

Next, the operation of the present invention will be explained using FIG.

First, unlike conventional devices, the clock pulse φ _1L applied to the final gate electrode of the charge transfer electrode is
The waveform shown in the figure is formed on a semiconductor substrate and supplied to the final gate electrode. An example of a logic circuit that forms the waveform is shown in FIG. A clock pulse φ ₁ is supplied to the clock terminal CK of the flip-flop, while a signal corresponding to the fall of the reset pulse φ R is applied to the reset terminal _R of the flip-flop. A signal corresponding to this falling edge is formed as a short pulse in synchronization with the trailing edge of the reset pulse by an integrating circuit including a resistor and a capacitor, an inverter, and an AND gate. As a result, the clock pulse obtained at the output terminal Q of the flip-flop has a waveform whose rising edge is determined by the clock pulse _φ1 and whose falling edge is determined by the falling edge of the reset pulse _φR . Since the obtained clock pulse is applied to the final gate electrode separately from other gate electrodes, the capacitance of the signal supply system is only that of the final gate electrode, which is extremely small, and the resulting steep waveform is It will remain as is.

Now _, in the system shown in FIG. 3 _, the timing margin corresponding to the reset pulse φ _R and clock pulse φ _1L in the conventional type shown in FIG. It becomes zero. Furthermore, since the clock pulse φ _1L is supplied only to the final gate electrode, the fall of the clock pulse φ ₁ can be made steep because the load capacitance is small. In this way, in the present invention, the delay time from _t1 to _t4 can be extremely shortened.

[Brief explanation of drawings]

FIG. 1a is a cross-sectional view of the detection section of the charge-coupled device. FIG. 1b is a diagram illustrating the charge transfer operation of the charge transfer device using a potential well. FIG. 2 is a diagram illustrating each timing of an output waveform of a conventional charge-coupled device. FIG. 3 is a diagram illustrating each timing of the output waveform of the charge coupled device of the present invention.
FIG. 4 is a diagram showing a logic circuit according to an embodiment of the present invention. In the figure, 1...semiconductor substrate, 2, 3...
This is an impurity layer.

Claims (1)

[Claims] 1. A large number of gate electrodes are repeatedly arranged on a semiconductor substrate with a thin insulating film interposed therebetween, and a clock pulse is supplied to each electrode so that charges are transferred from the semiconductor substrate under the gate electrode to a charge detection section of the semiconductor substrate. In the charge-coupled device, the charge transferred to the charge detection section is removed from the charge detection section by a reset pulse. is synchronized with the clock pulse, and a pulse whose falling edge is synchronized with the trailing edge of the reset pulse is generated and applied independently of the clock pulses applied to other gate electrodes. Charge coupled device.