JPH03169027A - Drive of charge transfer device and integrated circuit - Google Patents

Abstract

PURPOSE:To lower the output voltage of a CCD charge transfer device by a method wherein a pulse which is changed between a first voltage level whose polarity is the same as that of a power-supply voltage or which is at a ground level and a second voltage level whose polarity is different from that of the power-supply voltage is applied to either a second gate electrode or a third gate electrode or to both gate electrodes. CONSTITUTION:A P1 pulse is given to gate electrodes 10, 13 from a timing generator 14 via a node 31; a P2 pulse is given to gate electrodes 9, 12; a PO pulse is given to gate electrodes 8, 11; a PR pulse is given to a gate electrode 6; signal charge under the gate electrode 11 passes under a gate electrode 7 and is output to a diffusion layer 4. At this time, the potential of the diffusion layer 4 is sampled and held via a source follower of NMOS transistors 18, 37, and is output to an output terminal 30. The threshold voltage of the NMOS transistor 37 may be OV or higher; even an NMOS transistor whose constitution is the same as that of NOMS transistors in other peripheral circuits operates as a source follower. Thereby, the output voltage of a CCD can be lowered.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to a charge transfer device (Ch
arge Coupled Device below, CCD
(abbreviated as)).

[Conventional technology]

2. Description of the Related Art Conventionally, a floating diffusion layer amplification method (FDA method) has been known as a charge detection method in an output section of a CCD. The operation will be explained using FIG. 2.

FIG. 2(a) shows a vertical cross-sectional view of the output section of the CCD and the output circuit, and FIG. 2(b) and (C) show the above CCD.
The internal potentials of the output parts C and D, and FIG. In FIG. 2 (&), l is a semiconductor substrate whose conductivity type is P type.

2 is a buried channel layer. Reference numeral 3 denotes a portion within the buried channel layer 2 that lowers the internal potential than the other portions and mainly prevents reverse flow of charges, and is present under the gate electrode of the second polysilicon layer. 4 and 5 are diffusion layers whose conductivity type is N type; 7-
9 is the gate electrode of the second polysilicon layer, 11, 12.3
8 is the gate electrode of the first polysilicon layer, 17 and 18 are N
MOS transistor (N-channel insulated gate field effect transistor), 19 is a sample and hold circuit, 20
3 indicates an output buffer, and 30 indicates an output terminal. In addition, nodes 24 to 29 indicate terminals, respectively. NMOS transistor 1 is connected to terminal 24.
8 is applied, a P2 pulse is applied to terminal 25, a P1 pulse is applied to terminal 26, a DC voltage VOG is applied to terminal 27, a PR pulse is applied to terminal 28, and a DC voltage is applied to terminal 29. A reset voltage is applied to each.

The internal potential of the CCD output section at time t=t1 in FIG. 2(d) is shown in FIG. 2(b), and the signal charge is sent below the last gate electrode 1l of the transfer section. At this time, the PR pulse applied to the gate electrode 38 becomes high level, and the potential of the diffusion layer 4 becomes equal to the reset voltage of the diffusion layer 5. After this, the P pulse becomes low level, and the diffusion layer 4 is separated from the diffusion layer 5. Then, at time t=t2, the Pl pulses applied to the gate electrodes 8 and 11 become low level, so that
The signal charge under the gate electrode ll is equal to the output gate voltage V00
Beyond the potential barrier under the gate electrode 7 to which is applied,
It is output to the diffusion layer 4. The potential from the diffusion layer 4 at this time is sampled by the sample hold 19 of the output circuit and output to the output terminal 30. As described above, the signal charge of the CCD is output as a signal voltage.

When attempting to lower the fi source voltage of an integrated circuit including a COD using this method, the following problems arise.

That is, as can be seen from (c) in FIG. 2, which shows the internal potential at time t=t2, in order for the signal charge to be completely output, the pulse applied to the gate electrode 1l must be at a low level. The internal potential under the gate electrode 7 must be higher than the internal potential under the gate electrode 11 when O■,
Furthermore, the voltage before the diffusion layer 4 receives the signal charge, that is, the reset voltage applied to the diffusion layer 5 must also be higher. Here, if the internal potential when the gate electrode 11 is O■ is, for example, 6■, then the gate electrode 7
The lower internal potential needs to be about 7■, and the reset voltage about 9■. Therefore, if the power supply voltage is set to 5V, it becomes impossible to output signal charges. Further, the value of the internal potential when the gate electrode 1l is 0■ is determined by the transfer efficiency of the CCD, and cannot be unnecessarily lowered.

The invention disclosed in JP-A-61-263271 is
One method for solving the above problem is to use a boosted power supply for the reset voltage. In other words,
As a reset voltage, a voltage higher than the electromagnetic voltage is generated to enable the output of signal charges.

[Problems to be Solved by the Invention] In an example in which the above-mentioned conventional technique is used and a boosted voltage of 9V is used as the reset voltage, the output of the COD, that is, the voltage at the node 2l in FIG. The internal potential below the gate electrode 7 is between 7V. This high voltage of 7 to 9 V must be amplified in the output circuit. In the source follower consisting of NMOS transistors 17 and 18 in the first stage of the output circuit, the power supply voltage (node 22) is 5.
, and the threshold voltage of NMOS transistor l7 is
If it is set to 1■, the operation of the NMOS transistor 17 will be in a non-saturation region.

This is because the conditions for the MOS transistor to operate in the saturation region are (gate-source voltage) - (threshold voltage) ≦ (drain-source voltage), and in the NMOS transistor 17, (V (node 2 1 )-V(node 23))-V(L threshold)≦{V
(Node 2 2) - V (Node 23)}, so the threshold voltage for operation in the saturation region is V (L threshold ≧ V (Node 21) - V (Node 22)). , up to the highest voltage (9V) at node 21, the threshold voltage is required to be 4. In other words, the NMOS transistor 17 in the first stage of the output circuit has a special threshold voltage of 4. In order to make this NMOS transistor, the number of photomasks and manufacturing steps increase, which increases the cost.Also, it is necessary to reset the power supply voltage of the NMOS source follower in the first stage of this output circuit. Similar to voltage, it is difficult to generate with a step-up power supply because the current consumption is
This is because while the reset voltage is less than several μA, the voltage for the source follower exceeds several tens of μA, making the boosting power supply circuit large-scale and requiring an extremely large area within the same integrated circuit.

An object of the present invention is to reduce the power supply voltage of an integrated circuit including a CCD without having to configure a MOS transistor connected to the output of the COD differently from other peripheral circuits.

[Means to solve the problem]

In order to achieve the above object, a method for driving a charge transfer device according to the present invention includes, as a signal charge output section, a diffusion layer having a conductivity type different from that of a semiconductor substrate, a first gate electrode adjacent to the diffusion layer, and a first gate electrode adjacent to the diffusion layer. A method for driving a charge transfer device including a second gate electrode adjacent to the first gate electrode and a third gate electrode adjacent to the second gate electrode, the method comprising:
and a first voltage level having the same polarity as the power supply voltage or the ground level on either or both of the third gate electrodes,
A pulse that changes between the power supply voltage and a second voltage level of a different polarity is applied.

According to another aspect, the method for driving a charge transfer device according to the present invention includes, as a signal charge output section, a diffusion layer having a conductivity type different from that of the semiconductor substrate, a first gate electrode adjacent to the diffusion layer, and a first gate electrode adjacent to the diffusion layer. a second gate electrode adjacent to the gate electrode of l;
A method for driving a charge transfer device including a third gate electrode adjacent to the second gate electrode, wherein the pulse amplitude is applied to either or both of the second and third gate electrodes. A pulse whose lower voltage level is a negative voltage level lower than the ground voltage of the positive power supply voltage is used.

Further, the integrated circuit according to the present invention includes, as a signal charge output section, a diffusion layer having a conductivity type different from that of the semiconductor substrate, a lth gate electrode adjacent to the diffusion layer, and a second gate electrode adjacent to the lth gate electrode. and a third gate electrode adjacent to the second gate electrode, the charge transfer device operates with a single power supply, and an electric charge is applied to either or both of the second and third gate electrodes. and a pulse generating circuit that generates a pulse that changes between a first voltage level having the same polarity as the power supply voltage or the ground level and a second voltage level having a different polarity from the power supply voltage. be.

While the conventional pulse shown in FIG. 3(a) had an amplitude from a voltage level (+10V) with the same polarity as the power supply voltage to the ground level (Ov), the pulse according to the present invention has an amplitude of, for example, the same polarity as the power supply voltage (+10V) to the ground level (Ov). As shown in Figures (b) and (C), the first voltage level (+5■ or 0■) has the same polarity as the power supply voltage or the ground level, and the second voltage level (+5■ or 0■) has a different polarity from the power supply voltage. -5V).

[For production]

Generally, by applying a negative voltage to the gate, the internal potential under the gate becomes lower than the internal potential under the gate in the ground voltage state. FIG. 4 shows an example of the relationship between the voltage applied to the gate and the internal potential.

The horizontal axis shows the gate voltage, and the vertical axis shows the internal potential.

Conventionally, a positive voltage from OV was applied to the gate, but in the present invention, a negative voltage is applied to the gate to lower the internal potential. In Figure 4, the internal potential is
Even if an excessively negative voltage is applied to the gate, the voltage will only drop to near O■, which is sufficient for the range of use of the present invention.

As a result of the above, even if the potential of the diffusion layer is low when there is no signal charge, and the internal potential under the first gate electrode is low, the signal charge is transferred to the bottom of the second gate electrode. The signal charge overcomes the potential barrier under the first gate electrode and is output to the diffusion layer. Therefore, since the potential of the diffusion layer when there is no signal charge can be lowered, the output voltage from the COD can be lowered.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
Figure (a) is a vertical cross-sectional view of the output section of the COD and its COD.
A portion of peripheral circuitry within an integrated circuit including D is shown. This integrated circuit is fooled by a single 5V power supply. Same figure (b)
．． (C) shows the internal potential corresponding to the CCD output section in (a) of the same figure.

FIG. 4(d) is a waveform diagram of the drive pulse. Figure 1 (a
) is an implanted barrier type CCD with two-phase drive.

In FIG. 1(a), 1 is a P-type semiconductor substrate. 2
is an N-type semiconductor layer and forms a charge transfer channel of the buried channel COD. 3 is P in the N-type semiconductor layer 2.
It is a thin N-type semiconductor layer mixed with type impurities, and its main function is to form a potential barrier and prevent reverse flow of charges. 4 and 5 are N-type diffusion layers, 4 is an output diffusion layer, and 5 is a diffusion layer for supplying a reset potential to the output diffusion layer 4. Further, 6 to 10 are gate electrodes made of a second polysilicon layer, 11 to 13 are gate electrodes made of a first polysilicon layer, 14 is a timing generator that generates each pulse necessary for driving the CCD, etc., and 15 is a A negative voltage pulse generator generates a pulse having an amplitude up to a negative potential, 19 is a sample and hold (S/H) circuit, and 20 is an output buffer. Further, 18.37 is an NMOS transistor (N-channel insulated gate field effect transistor), which forms a source follower.

30 is a terminal to the outside of the integrated circuit including the COD, from which a delayed signal is output. 24 is a terminal to which a bias voltage is applied to the current source MOSh transistor 18 of the source follower. 22, 23. 31 to 36 are respectively,
Showing nodes.

A PL pulse, which is a transfer pulse indicated as PL in FIG. 1(d), is applied to the gate electrode 10.13 from a timing generator via a node 31. Similarly, the P2 pulse is applied to the gate electrodes 9 and 12, and the P2 pulse is applied to the gate electrodes 8 and 1.
The PO pulse is applied to the gate electrode 6, and the P.O pulse is applied to the gate electrode 6. The pulse is
each is given. Gate electrode 7 is at ground potential.

A Ps/H pulse is given to the sample hold circuit 19, and when the Ps/H pulse is at a high level,
The signal voltage is sampled, and when it is low level, the sampled signal voltage is held. Figure l (
The internal potential of the output section of the CCD at time t=ti in d) is shown in FIG. 4(b). The vertical axis in FIG. 2B indicates the internal potential, and the lower the direction, the higher the internal potential. However, for electrons, which are transferred charges, the energy is lower in the downward direction. Therefore, the charge moves downward. t=t
1, the P2 pulse is at a low level O■, so the voltages of the gate electrodes 9 and 12 are O■.

However, its internal potential is a certain value because it is a buried channel COD. For example, the internal potential under the gate electrode 12 of the first polysilicon layer is 5■, and the internal potential under the gate electrode 9 of the second polysilicon layer is slightly lower, about 3■ because of the thin N-type semiconductor layer 3. Suppose that At this time P
Since the O pulse is at the high level 5■, the internal potential under the gate electrodes 8 and 11 is high. Therefore,
The signal charge that had been transferred to the bottom of gate electrode 2 overcomes the potential barrier below gate electrode 8 and reaches gate electrode 1.
It is stored under l. At this time, the potential of the diffusion layer 4 is P,
Since the pulse is at a high level of 5V, the internal potential under the gate electrode 6 becomes high and becomes equal to the potential of the diffusion layer 5. The potential of the diffusion layer 5 is the power supply voltage, which is exactly 5. After this, the PR pulse becomes a low level OV, and the internal potential under the gate electrode 6 becomes about 3V because of the thin N-type semiconductor layer 3. As the internal potential under the gate electrode 6 becomes as low as 3■, the diffusion layer 4 and the diffusion layer 5
to cut off the gap between At time t=t2, the P1 pulse is at low level and the P2 pulse is at high level, so at time t
= tl, the signal charge that was under the gate electrode 13 is transferred to the bottom of the gate electrode 12. Also, the PO pulse becomes a low level of about -4V, and the internal potential under the gate electrodes 8 and 11 is as follows. The internal potential under the grounded gate electrode 7 becomes lower than 3V. As a result, the gate electrode 11
The lower signal charge passes under the gate electrode 7 and is output to the diffusion layer 4. The potential of the diffusion layer 4 at this time is sampled and held via the source follower of the NMOS transistor 18.37, and output to the output terminal 30. The potential of the diffusion layer 4 is 5V even when there is no signal charge, that is, when it is at its highest. Therefore, the source follower composed of the NMOS transistors 18 and 37 in the first stage of the output circuit operates well. This is because the NMOS transistor 37 satisfies the following conditions for operating in the saturation region. That is, the condition for the saturation region is that the drain-source voltage is greater than the gate-source voltage minus the threshold voltage. Applying this to the NMOS transistor 37 and rearranging the threshold voltage, we get the following. The threshold voltage of NMOS transistor 37 is greater than the voltage at node 36 minus the voltage at node 22. The highest voltage of the node 36, that is, the highest voltage of the diffusion layer 4, is 5V as described above, and the voltage of the node 22 is also 5V, which is the power supply voltage. Therefore, N.M.O.
The threshold voltage of the S transistor 37 may be OV or more,
Same NM as the NMOS transistor configuration of other peripheral circuits
Even OS transistors work well as source followers.

As described above, in this example, the output voltage of the COD can be lowered. Therefore, NM of the source follower in the first stage of the output circuit
There is no need to make the threshold voltage of the OSh transistor particularly high, and it is sufficient to use the same NMOS transistor configuration as the NMOS transistors in other peripheral circuits.

This example is an implanted barrier type two-phase drive C
Although the case where the present invention is applied to OD has been described, the present invention is not limited thereto.

FIG. 5 shows another embodiment. Figure 5(a) shows the COD
1 shows a vertical cross-sectional view of an output section of the device and part of peripheral circuits in the integrated circuit including its COD. It should be noted that this integrated circuit is driven by a 5-inch single power supply.

Figures (b) and (C) show the internal potentials corresponding to the COD output section in Figure (a). In addition, FIG. 4(d) shows the timing of the drive pulse. The times t=tl and t=t2 during the timing of the drive pulse are shown in (b) and (C) in the same figure.
This corresponds to the diagram of the internal potential of the COD output section, respectively. In FIG. 5(a), the same reference numerals as in FIG. 1(a) indicate the same parts.

In FIG. 5(a), reference numeral 39 indicates a boosting power supply circuit, 40 indicates an N-type semiconductor layer forming a charge transfer channel of the buried channel CCD, and 4l indicates an N-type semiconductor layer thinner than the N-type semiconductor layer 40. In FIG. The difference from FIG. 1 is that the impurity concentration of the semiconductor layers 40 and 41 is different, and the internal potential when O
The voltage under the gate electrode 9 of l is 4V, and the voltage under the gate electrode 12 is 6■
And each is getting higher. Therefore, the voltage applied to the diffusion layer 5 is set to be the output of the booster power supply circuit, which is approximately 1 µ higher than the power supply voltage. As a result, the output voltage from the CCD increases by about 1. However, similar to the example in Figure 1, NM
The OS transistor 37 operates in the saturation region. 1st
In the example shown, the threshold of the NMOS transistor {llN!
The voltage was O■ or higher.

In this example, since the voltage at the node 36 is 1■ higher, the threshold voltage of the NMOS transistor 37 is required to be 1■ or more. The threshold voltage of the NMOSh transistor 37 has a value of about IV or more because the source voltage is higher than the back gate voltage. Other examples,
The same applies even if the threshold value of the NMOS transistor 18 whose back gate voltage and source voltage are equal is about 0.7V. Even if the NMOS transistor 37 deviates slightly from the saturation region when the output voltage is high and the signal charge is small, the output characteristics of CCDs have poor linearity when the signal charge is small, so they cannot be used up to that voltage. There is no impact so there is no impact.

In addition, when the voltage of the gate electrode 6 changes from a high level to a low level and disconnects the diffusion layer 4 and the diffusion layer 5, including the example shown in FIG. 1, the voltage of the diffusion layer 4 slightly decreases due to clock feedthrough. It ends up.

The voltage of the diffusion layer 5 is determined including that amount and the signal charge. Naturally, the voltage drop in the diffusion layer 4 due to this clock feedthrough has nothing to do with the signal. Therefore, even if the lower part of the gate electrode 6 is in a conductive state and the voltage from the boosted power source of the diffusion layer 5 is output to the output node 36 of the CCD, and the NMOS transistor 37 is no longer saturated, a signal voltage is still output. Sometimes it is enough to reach a saturated state.

As mentioned above, when a boost power supply circuit is used in the output section of a COD, the voltage can be lowered, so the NMOS transistor of the source follower in the first stage of the output circuit can have the same configuration as the NMOS transistors of other peripheral circuits. can do.

An example of the negative voltage pulse generator used in the present invention will be explained using FIG. 6. Figure 6(a) is a circuit diagram;
b) shows the voltage waveform of each node. Figure 6(a)
As in FIG. 1(a), 14 is a timing generator, 42.43 is a PMOS transistor, and 44
are capacitors, 45 to 47 are inverters, and 48 and 49 are NAND gates 50 to 52, respectively, nodes. 53
is an output terminal and is connected to the output gate of the CCD.

VDD is a power supply voltage of 5V. At time t=tl shown in FIG. 6(b), the node 50 is OV and the node 51
is 5■, so PMOSh transistor 42 is on, 43
is off, and the output terminal 53 has a power supply voltage of 5V. After this, the node 50 becomes 5■, and the PMOSh transistor 42 is turned off. When the node 5l becomes OV, the voltage at the output terminal 53 decreases as a current flows through the PMOS transistor 43. And PMOS
The threshold voltage of the transistor is lowered to, for example, lV. At this time, since the voltage at the node 52 is 5.times., a charge of 4 V is stored in the capacitor 44. After this, the voltage at the node 52 changes from 5■ to O■. Since the capacitor 44 has a charge of 4 .mu., -4V is outputted to the output terminal 53. Then, node 51 is 5v again.
Therefore, the node 50 becomes 0■, the PMOS transistor 42 is on, the PMOS transistor 43 is off, and a voltage of 5V is output to the output terminal 53.

Since the above circuit can be realized within the same integrated circuit as the COD, by applying the present invention, the number of external components of the integrated circuit does not increase. Note that the above circuit is an example of a negative voltage pulse generator, and the present invention is not limited to the above circuit.

Another embodiment of the present invention will be described with reference to FIGS. 7 and 8. FIG. 7(a) shows a vertical cross-sectional view of the output section of the COD and a part of the peripheral circuitry in the integrated circuit including the COD. Note that this integrated circuit is driven by a single 5-inch power supply as in the other examples. (b) to (g) in the same figure show the internal potentials corresponding to the COD output section in (&) in the same figure. Also,
FIG. 8 shows the timing of drive pulses. The times t=tl to 6 during the timing of the drive pulse are respectively,
This corresponds to the diagrams of the internal potential of the COD output section in FIGS. 7(b) to (g). In Fig. 7(a), Fig. 1(a) and 5
Components with the same reference numerals as those in Figure (a) indicate the same parts.

(Margin below) In FIG. 7(a), 55 is a P-type semiconductor substrate.

56 is an N-type semiconductor layer with a buried channel COD
form a charge transfer channel.

57 is the same N-type semiconductor layer as the N-type semiconductor layer 56 described above. 58 and 59 are N-type diffusion layers, 58 is an output diffusion layer, and 59 is a diffusion layer for supplying a reset potential, in this example, a power supply voltage of 5V to the breakdown layer 58. 60 to 67 are gate electrodes, 68 is a timing generator, 69 is a negative voltage pulse generator, and 70 to 76 are nodes. At the node 70 which is the output of the timing generator 68, the P1 pulse shown as P1 in FIG.
has a P2 pulse, node 72 has a P3 pulse, node 74 has a P.pulse, and node 35 to sample and hold circuit 19 has a P.3 pulse. /H pulses are output respectively. Node 7, which is the output of negative voltage pulse generator 69
3, a PO pulse indicated as PO in FIG. 8 is output. The internal potential of the output section of the COD at time t=t1 in FIG. 8 is as shown in FIG. 7(b). Same figure (
The vertical axis in b) indicates the internal potential, and the lower the potential, the higher the potential. For the lump of signal charge transferred from the left side of the figure, the PO pulse applied to the gate electrode 64 is 5V, the P1 pulse applied to the gate electrode 63 is O■, and the P3 pulse applied to the gate electrode 65 is also 0■. , in the potential well below gate electrode 64. When time t=t2, the P3 pulse becomes 5V, and the internal potential under the gate electrode 65 becomes high.

Then, the signal charge under the gate electrode 64 is transferred to the gate electrode 64.
Expands to below 5. Furthermore, since the PO pulse is gradually decreasing, the signal charge moves from below the gate electrode 64 to below the gate electrode 65. Since the PR pulse is 5■, the internal potential under the gate electrode 67 becomes high, and the potential of the diffusion layer 58 becomes equal to the reset potential (5V) of the diffusion layer 59. At time t=t3, all of the signal charges under the gate electrode 64 have moved to under the gate electrode 65. Then, the internal potential under the gate electrode 64 further decreases as the PO pulse decreases to a negative potential. At time t=t4, P
Since the R pulse becomes O■, a potential barrier is created under the gate electrode 67, and the diffusion layer 58 is separated from the diffusion layer 59, resulting in a floating state. Additionally, the P3 pulse gradually decreases.

When time t=t5, P3 pulse becomes O■, so
The internal potential under the gate electrode 65 becomes equal to the internal potential of the gate electrode 66 connected to the ground potential. Since the PO pulse is at a negative potential, the internal potential under the gate electrode 64 is lower than the internal potentials of the gate electrodes 65 and 66. Therefore, the signal charges existing under the gate electrode 65 pass under the gate electrode 66 and flow into the diffusion layer 58. And P. Since the /H pulse is 5V, the sample and hold circuit 19 detects the NMOS from the diffusion layer 58.
Outputs the voltage through the source follower by transistor 37.18. Then, the sample hold circuit 19
．． When the /H pulse becomes OV, the voltage immediately before that is held.

At t=t6, the PO pulse becomes 5V, and the gate electrode 6
4, the next signal charge below the gate electrode 63 enters. Thereafter, the operation from time t=tl is repeated.

Here, the maximum amount of charge output to the diffusion layer 58 is the amount that changes the potential of the diffusion layer 58 from approximately the reset potential to the internal potential of the gate electrode 66. In this example, if the internal potential of the grounded gate electrode is 3■, the reset potential is 5V, so the range in which the potential of the diffusion layer 58 can be changed is 2■. If the internal potential of the grounded gate electrode is higher, for example 4■, the reset potential can be set to a slightly boosted voltage as shown in the example of Fig. 5, so that the above voltage range can be obtained. good. In this example, as well as the examples shown in FIGS. 1 and 5, the output voltage of the COD (node 76
The voltage is so low that it is not necessary to use a special MOS transistor in the first stage of the output circuit.

In order for the charge under the gate electrode 65 to enter the diffusion layer 58 at time t=t5 without flowing backward, the gate electrode 66 at this time must be
It is necessary that the internal potential below the gate electrode 64 be sufficiently higher than the internal potential below the gate electrode 64.

If the present invention is not applied, the internal potential under the gate electrode 64 becomes the internal potential under the gate electrode at the ground potential. Therefore, it is necessary to apply a certain amount of voltage to the gate electrode 66 to raise the internal potential. And the reset potential needs to be raised accordingly, and of course the COD
The output voltage of will also increase. Therefore, a special NMOS transistor with a large threshold voltage must be used as the NMOS transistor 37.

In the examples shown in Figures 1, 5, and 7, the gate electrodes (for example, 66 in Figure 7) immediately before the output diffusion layer (for example, 58 in Figure 7) are all set to the ground potential. This is not intended to limit the invention. A slight voltage may be applied if necessary.

〔Effect of the invention〕

According to the present invention, since the output voltage of the COD can be lowered,
The power supply voltage of the integrated circuit including the COD can be lowered while the MOS transistor connected to the output of the COD has the same configuration as other peripheral circuits. Since the MOS transistor connected to the output of the COD is not special, it is possible to reduce manufacturing process costs for integrated circuits including the COD.

[Brief explanation of the drawing]

FIG. 1 is a vertical cross-sectional view, peripheral circuit block diagram, internal potential diagram, and pulse waveform diagram of a CCD output section according to an embodiment of the present invention, and FIG. 2 is a vertical cross-sectional view and peripheral circuit block diagram of a conventional COD output section. Figure 3 is an explanatory diagram showing an example of a pulse waveform, and Figure 4 is an internal potential diagram and a pulse waveform diagram.
Graph showing the relationship between the gate voltage and internal potential of D, fifth
The figure shows a vertical cross-sectional view, a peripheral circuit block diagram, an internal potential diagram, and a pulse waveform diagram of a COD output section of another embodiment,
FIG. 6 is a circuit diagram showing an example of a negative voltage pulse generator and a voltage waveform diagram of each node, and FIG. 7 is a COD of another embodiment.
A vertical cross-sectional view, a peripheral circuit block diagram, and an internal potential diagram of the output section, and FIG. 8 is a pulse waveform diagram of each part of FIG. 7. DESCRIPTION OF SYMBOLS 1... P-type semiconductor substrate, 2... N-type semiconductor layer, 3...
・Thin N-type semiconductor layer, 6 to 13 ・Gate electrode, 1
4... Timing generator, 15... Negative voltage pulse generator, 18, 37... NMOS transistor,
19... Sampling hold circuit, 20... Output buffer. 11 t2 t C/ τ2 r Muscle 3 Punishment 4 Concave i=it Octopus 6 Mouth t

Claims (1)

[Claims] 1. As a signal charge output section, a diffusion layer having a conductivity type different from that of the semiconductor substrate, and a first gate electrode adjacent to the diffusion layer;
A method for driving a charge transfer device including a second gate electrode adjacent to the first gate electrode and a third gate electrode adjacent to the second gate electrode, the method comprising: A pulse that changes between a first voltage level having the same polarity as the power supply voltage or the ground level and a second voltage level having a different polarity from the power supply voltage is applied to one or both of the gate electrodes. A method for driving a charge transfer device. 2. As a signal charge output section, a diffusion layer having a conductivity type different from that of the semiconductor substrate, and a first gate electrode adjacent to the diffusion layer;
A method for driving a charge transfer device including a second gate electrode adjacent to the first gate electrode and a third gate electrode adjacent to the second gate electrode, the method comprising: A charge transfer device characterized in that a pulse whose lower voltage level of the pulse amplitude is a negative voltage level lower than a ground voltage of a positive power supply voltage is used as a pulse applied to one or both of the gate electrodes. input method. 3. As a signal charge output section, a diffusion layer having a conductivity type different from that of the semiconductor substrate, and a first gate electrode adjacent to the diffusion layer;
a charge transfer device that operates on a single power source and includes a second gate electrode adjacent to the first gate electrode and a third gate electrode adjacent to the second gate electrode; As a pulse applied to one or both of the gate electrodes of No. 3, a pulse that changes between a first voltage level having the same polarity as the power supply voltage or a ground level and a second voltage level having a different polarity from the power supply voltage is applied. An integrated circuit characterized by comprising a pulse generation circuit that generates a pulse.