JPH01283519A - Liquid crystal display device - Google Patents

Liquid crystal display device

Info

Publication number
JPH01283519A
JPH01283519A JP63113150A JP11315088A JPH01283519A JP H01283519 A JPH01283519 A JP H01283519A JP 63113150 A JP63113150 A JP 63113150A JP 11315088 A JP11315088 A JP 11315088A JP H01283519 A JPH01283519 A JP H01283519A
Authority
JP
Japan
Prior art keywords
film
insulating film
electrode
layer
intersection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63113150A
Other languages
Japanese (ja)
Inventor
Kazuo Ikegami
池上 和男
Shozo Oura
大浦 昌三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP63113150A priority Critical patent/JPH01283519A/en
Publication of JPH01283519A publication Critical patent/JPH01283519A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136213Storage capacitors associated with the pixel electrode
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136259Repairing; Defects
    • G02F1/136263Line defects

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Liquid Crystal (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)

Abstract

PURPOSE:To prevent signal wiring and an auxiliary capacitor from being short- circuited by leaving a semiconductor film, metal, and metal oxide on an insulating film at the intersection of the signal wiring and auxiliary capacitor and compensating a defect in the insulating film, and widening a layer interval. CONSTITUTION:A layer for protecting the insulating film such as the semiconductor film, metal, and metal oxide film is provided at the intersection of an auxiliary capacity electrode 5 and a drain electrode 1. Then, if the insulating film has a projection, pinhole, or dust, an amorphous silicon film 2, ITO film 6, or Cr film 7 is left on a 2nd layer insulating film 4 or in the intermediate layer between a 1st layer insulating film 3 and the 2nd layer insulating film 4. The thin insulating film at the intersection of the auxiliary capacity electrode 5 and drain electrode 1 is not etched, the defect in the insulating film is compensated by the intervention of the conductive film 8, and the layer interval between two kinds of conductors increases. Consequently, a short circuit is prevented from being generated at the intersection of the auxiliary compensating electrode 5 and drain electrode 1.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は薄膜トランジスタ(TPT)またはMIM装置
をスイッチング素子として用いたアクティブマトリクス
型の液晶表示装置に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to an active matrix liquid crystal display device using a thin film transistor (TPT) or an MIM device as a switching element.

(財)従来の技術 アクティブマトリクス型の液晶表示装置は三洋電機技報
voi16.No、2.1984(二示されているよう
C二複数本のゲートラインとそれらC二直交する複数本
のドレインライン及びそれらの交点(:TFTY形成し
、表示電極と’I’FTを結合した基板(二対内電極が
相対し、その間(:液晶を挾み込む形をとっている0ま
九、従来の技術は各絵素1:FRTま九はMIMと液晶
の持つ電気容量以外(二、第2図に)のような補助容量
電極(5)が付けられているO これらの補助容量で表示電極と対向電極との間ζ;挾ま
っている液晶2通して流れるリーク電流及びスイッチン
グ素子(TPT、MIM)のオフ時のリーク電流C二よ
る印加電圧の低下を補償するので、この容量C二より液
晶に印加される1圧保持を向上させ、また液晶表示装置
を駆動する駆動回路の消費電力を下げている。
(Incorporated) Conventional technology active matrix type liquid crystal display device is Sanyo Electric Technical Report vo16. No. 2.1984 (2) As shown, C2 multiple gate lines, C2 orthogonal drain lines and their intersections (:TFTY were formed, and the display electrode and 'I'FT were connected. The substrate (two pairs of inner electrodes face each other, and the liquid crystal is sandwiched between them). In the conventional technology, each picture element 1: Auxiliary capacitance electrodes (5) such as those shown in Fig. 2) are attached to these auxiliary capacitances between the display electrode and the counter electrode. Since it compensates for the drop in applied voltage due to the leakage current C2 when the TPT, MIM) is off, this capacitor C2 improves the maintenance of the 1 voltage applied to the liquid crystal, and also reduces the consumption of the drive circuit that drives the liquid crystal display device. Power is being lowered.

一方、第2図(ト))(:示すようl:、 T F T
基板で補助容量電極(5)とドレイン電極(11は第−
層絶縁膜(3)及び第二層絶縁膜(4)を介して交差し
ており、蒸着ま念はO’/Dで一旦形成されてい次金属
及び金属酸化物はエツチングされるのが通常である。他
方、画質を向上させる友め、面積あたりの画素数を増し
配線幅を小さくして配線の段差を縮小させる必要がある
On the other hand, as shown in Figure 2 (G)
On the substrate, the auxiliary capacitance electrode (5) and the drain electrode (11 are the -th
The layer insulating film (3) and the second layer insulating film (4) intersect with each other, and the metal and metal oxide are usually etched once they are formed in O'/D. be. On the other hand, in order to improve image quality, it is necessary to increase the number of pixels per area, reduce the wiring width, and reduce the level difference in wiring.

このため、数百Aの絶縁膜が用いられることがあυ、絶
縁膜の欠陥や膜形成前の浦助容it表面及び膜付は装置
中の塵埃により補助容量電極(5)とドレイン電標(1
)との間のショートが発生する確率が高い。従来では1
0万個の交点に対して、数十点単位のショートが生じて
いた。
For this reason, an insulating film of several hundred amperes is sometimes used, and defects in the insulating film and dust on the surface of the Urasuke IT before film formation and on the film may cause the auxiliary capacitance electrode (5) and the drain voltage. (1
) is likely to occur. Conventionally, 1
For 00,000 intersection points, short circuits occurred in dozens of points.

ところでドレイン、ソースの下層の絶縁性の高いアモル
ファスシリコン膜(2]をゲートとドレインの交点に第
2図CA)の如く残して、ゲートとドレインとの間のシ
ョート?防止する発明は既C二存在する。(実願昭60
−40617号参照〕(ハ)発明が解決しようとする課
題 従来の技術C:おいては、ショート防止の九め(:二種
の導電体の間に絶縁性の高い物質を挾むと共セ導電性の
高い物質を除去してい九。そして、第1図俤)のアそル
ファスシリコン膜(2)をエツチングする際C;第二層
絶縁膜+41(:埋まった塵が取れて第−層絶縁膜(3
)Cニビンホールができるか、その絶縁性を損なうほど
薄くなり、その上Cニドレイ/を極(1)が形成されて
ショートが生じていt。
By the way, is it possible to create a short circuit between the gate and drain by leaving the highly insulating amorphous silicon film (2) below the drain and source at the intersection of the gate and drain as shown in Figure 2 (CA)? There are already two inventions that prevent this. (Jitsugan 1986
-40617] (C) Problems to be Solved by the Invention Conventional technology C Then, when etching the amorphous silicon film (2) shown in Figure 1 (Fig. 1), the buried dust is removed and the - Membrane (3
) A hole is formed or the insulation becomes thin enough to impair its insulation properties, and on top of that, a short circuit occurs due to the formation of a pole (1) on the C hole.

この発明はこの点?解決し、挾む物質を特定せず、二種
の導電体の層間隔を大きくシ、引いては層間のショー)
Y確実に防止すること全目的とじ九ものである。
Is this the point of this invention? The solution is to increase the interlayer spacing between the two types of conductors without specifying the intervening substance, which may lead to an increase in the gap between the layers.)
The overall purpose is to ensure prevention.

に)課題を解決する九めの手段 本発明はアクティブマトリクス液晶表示装置【二おいて
、補助容量と信号配線とのショートを防ぐためのもので
、第1図に)のよう(二捕助容量電極(5)とドレイン
電極:極(1)の交差する部分(二手導体膜又は金属又
は金属酸化膜などの絶縁膜を保護するための層を設ける
ことを特徴とするものである。
Ninth Means for Solving the Problems The present invention is directed to an active matrix liquid crystal display device (see Figure 1) for preventing short-circuits between storage capacitors and signal wiring. Electrode (5) and drain electrode: This is characterized by providing a layer for protecting the intersecting portion of the electrode (1) (a two-handed conductor film or an insulating film such as a metal or metal oxide film).

(ホ)作 用 本発明では絶縁膜(二突起やピンホールやゴミがある場
合、それぞれ第1図CB)、(0)の如く第二層絶縁膜
(4)の上部又は第−層絶縁膜(3)と第二層絶縁膜(
4)との中間層にアモルファスシリコン1i1i121
.  I TO膜(6)又はQr膜(7)などを残して
おくことにより、補助容量電極(51とドレイン電極(
1)との交点の薄い絶縁膜がエツチングされず、導1!
膜(8)の介在により絶縁膜の欠陥が補償され、補助容
量電極(5)とドレイン電極(11との交点でのショー
トが発生しないものである。
(e) Function In the present invention, the insulating film (if there are two protrusions, pinholes, or dust, respectively, CB in FIG. 1), the upper part of the second layer insulating film (4) or the first layer insulating film as shown in (0) (3) and the second layer insulating film (
4) Amorphous silicon 1i1i121 in the intermediate layer with
.. By leaving the ITO film (6) or the Qr film (7), the auxiliary capacitance electrode (51) and the drain electrode (
The thin insulating film at the intersection with 1) is not etched and the conductor 1!
The presence of the film (8) compensates for defects in the insulating film, and no short circuit occurs at the intersection of the auxiliary capacitance electrode (5) and the drain electrode (11).

(へ)実施例 第1図cA)(:本発明の一実施例のTPTを用いた液
晶表示装置の平面図、第1図の)及び(0口:補助容量
電極(5)とドレイン電極(11の交点の断面図を示す
(to) Example Fig. 1 cA) (: Plan view of a liquid crystal display device using TPT according to an embodiment of the present invention, Fig. 1) 11 is a cross-sectional view of the intersection.

ここでは半導体膜としてアモルファスシリコン膜421
 (a −S i) 、金属としてO”股(71、金属
酸化物としてITO膜(6)ヲ用いる場合を説明する。
Here, an amorphous silicon film 421 is used as a semiconductor film.
(a-S i) A case will be described in which an O'' film (71) is used as the metal and an ITO film (6) is used as the metal oxide.

半導体薄膜(SL−3i)(2+を残す場合?第1図C
B)l=示す。
Semiconductor thin film (SL-3i) (When leaving 2+? Figure 1C
B) l=indicated.

ノーダガラスま九はホウケイ酸ガラス基板:;補助容量
電極(5)をITO(600A) 、第−層絶縁膜(3
)を81N! (800A) 、ゲート電極gQr膜(
71(1200A) 、表示電極’&ITO膜(61(
600A)の屓で形成後、P−OVD装置C二より第二
層絶縁膜(4)を5INx (600A)で、半導体薄
膜9ea −S i(2+500 AS峨極コンタクト
用半導体薄膜&n−a−8i (200A)で同時【;
形成し、a−81(21及びn −5L−31をチャネ
ル部とドレイン電極(11とゲート電極の交差部の他1
:、ドレイン電極(1)(AI!(2000A)と補助
容量電極(5)CITO)の交点にも残して、それ以外
のa−81(21及びn−a−8i″4r−エツチング
する。
The auxiliary capacitance electrode (5) is made of ITO (600A), and the third layer insulation film (3) is made of borosilicate glass substrate.
) for 81N! (800A), gate electrode gQr film (
71 (1200A), display electrode'& ITO film (61 (
After forming the second layer insulating film (4) with 5INx (600A) using P-OVD device C2, the semiconductor thin film 9ea-S i (2+500 AS semiconductor thin film for electrode contact &n-a-8i) is formed. (200A) at the same time [;
A-81 (21) and n-5L-31 are connected to the channel part and the drain electrode (11 and the intersection of the gate electrode and 1
:, leaving it at the intersection of the drain electrode (1) (AI! (2000A) and the auxiliary capacitance electrode (5) CITO), and etching the other a-81 (21 and na-8i''4r-etch).

その後ドレイン電極(11を形成したところ、絶縁層厚
程度の埃や欠陥C:よるショートがなくなった。
After that, when a drain electrode (11) was formed, short circuits due to dust and defects C: as thick as the insulating layer disappeared.

尚、n−a−8iがない場合C二も適用できるのはいう
までもない。
It goes without saying that C2 can also be applied in the absence of na-a-8i.

金属又は金属酸化膜を残す場合を第1図(Q)C示す0 補助容量電極(5)をrToで形成したガラス基板上(
:第−層絶縁膜(3)を形成後、ゲート電極をOr膜(
7)でかつ表示電極をI’l’O膜(6)で膜付けし、
エツチング(:よるパターン形成時C:同時Cニドレイ
ン電極(1)と補助容量電極(5)の交差部(:もゲー
ト電極材料のo r PAf7) (金!:A)又は表
示電極材料ノI TOff!+61 (金属酸化#、′
I) w残し、その後、P−eVD装置により第二層絶
縁膜(4)半導体薄膜を同時に形成し、ドレイン(1極
(11とソース電極を形成したところ、補助容′fi電
極(5)とドレイン電極(1)との間のショートがなく
なった。
The case where a metal or metal oxide film is left is shown in FIG.
: After forming the -th layer insulating film (3), the gate electrode is formed with an Or film (
7) And the display electrode is coated with an I'l'O film (6),
During pattern formation by etching (: C: Simultaneous C) Intersection of drain electrode (1) and auxiliary capacitance electrode (5) (: also gate electrode material or PAf7) (gold!: A) or display electrode material I TOff !+61 (metal oxidation #,'
I) After that, a second layer insulating film (4) and a semiconductor thin film were simultaneously formed using a P-eVD device, and when the drain (1 pole (11) and source electrode were formed, the auxiliary capacitor 'fi electrode (5) and There is no longer a short circuit with the drain electrode (1).

ここでゲー)!極材料及び表示電極材料を共(二補助容
量電極(5)とドレイ/電極(1)の交差部(=残した
場合(=も同様な結果が得られた。当然のことながら、
半導体と金属化合物が共存しても良い。
Game here)! Similar results were obtained when both the electrode material and the display electrode material were left at the intersection of the two auxiliary capacitor electrodes (5) and the drain/electrode (1). Naturally,
A semiconductor and a metal compound may coexist.

ここでは、現在の工程数を増やさない改良案としてa−
8i、Qr、ITO’i’例):示したが、他の半導体
薄膜や金属や金属酸化物や導電性高分子(例えばポリア
ニリン)を用いても、同様の効果がある。
Here, as an improvement plan that does not increase the current number of processes, a-
8i, Qr, ITO'i' example): Although shown, similar effects can be obtained by using other semiconductor thin films, metals, metal oxides, or conductive polymers (eg, polyaniline).

MIM素子の中間層の絶縁物(jnsulat;or)
も多層で形成されているので、補助電極と信号線以上の
ようC二本発明は信号配線と補助容量の交点の絶縁膜上
(二手導体膜や金属や金属酸化物を残すととC二よって
絶縁膜中の欠陥を補償し、層間隔を広げることC:より
、信号配線と袖助容にとのショートを防ぐことができる
Insulator of intermediate layer of MIM element (jnsulat;or)
Since the auxiliary electrode and the signal line are also formed in multiple layers, the present invention can be applied to the insulating film at the intersection of the signal line and the auxiliary capacitor (if the two-handed conductor film, metal, or metal oxide is left on the C2). C: By compensating for defects in the insulating film and widening the layer spacing, it is possible to prevent short circuits between the signal wiring and the sleeve support.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の液晶表示装置の平面図、ドレイン電極
と補助容Jf/L電極の交点及びドレイン電極とゲート
電極の交点の断面図である。 第2図は従来の液晶表示装置の平面図、ドレイン電極と
補助容Ik電柩の交点の断面図である。 (11・・・ドレイン電極、(2+・・・アモルファス
シリコン膜、(3)・・・第−層絶縁腔、(4)・・・
第二層絶縁膜、(5)・・・補助容it極、+61・Z
 T O膜、(7)・・・or膜、(81・・・導電膜
FIG. 1 is a plan view of the liquid crystal display device of the present invention, and a sectional view of the intersection of the drain electrode and the auxiliary capacitor Jf/L electrode and the intersection of the drain electrode and the gate electrode. FIG. 2 is a plan view of a conventional liquid crystal display device and a sectional view of the intersection of the drain electrode and the auxiliary capacitor Ik electric coffin. (11...Drain electrode, (2+...Amorphous silicon film, (3)...-th layer insulation cavity, (4)...
Second layer insulating film, (5)... Auxiliary capacitance it pole, +61・Z
T O film, (7)...or film, (81...conductive film.

Claims (1)

【特許請求の範囲】 1、アクティブマトリクス液晶表示装置において補助容
量と信号配線が絶縁膜で隔てられている部分に導電膜あ
るいは半導体膜を設けることによつて補助容量と信号配
線が絶縁膜及び前記導電膜又は半導体膜を介して交差す
ることを特徴とする液晶表示装置。 2、導電膜は半導体、金属、金属酸化物、有機物なる群
より選択された1若しくは2以上の物質で形成されてい
る請求項1記載の液晶表示装置。
[Claims] 1. In an active matrix liquid crystal display device, a conductive film or a semiconductor film is provided in a portion where an auxiliary capacitance and a signal wiring are separated by an insulating film. A liquid crystal display device characterized by intersecting conductive films or semiconductor films. 2. The liquid crystal display device according to claim 1, wherein the conductive film is formed of one or more substances selected from the group consisting of semiconductors, metals, metal oxides, and organic substances.
JP63113150A 1988-05-10 1988-05-10 Liquid crystal display device Pending JPH01283519A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63113150A JPH01283519A (en) 1988-05-10 1988-05-10 Liquid crystal display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63113150A JPH01283519A (en) 1988-05-10 1988-05-10 Liquid crystal display device

Publications (1)

Publication Number Publication Date
JPH01283519A true JPH01283519A (en) 1989-11-15

Family

ID=14604836

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63113150A Pending JPH01283519A (en) 1988-05-10 1988-05-10 Liquid crystal display device

Country Status (1)

Country Link
JP (1) JPH01283519A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5042916A (en) * 1989-10-04 1991-08-27 Hosiden Corporation Active matrix display device having divided additional capacitors
JPH0445425A (en) * 1990-06-12 1992-02-14 Nec Corp Production of liquid crystal panel
EP0488802A2 (en) * 1990-11-30 1992-06-03 Sharp Kabushiki Kaisha An active matrix display device
US5276540A (en) * 1990-11-30 1994-01-04 Sharp Kabushiki Kaisha Active matrix substrate with conductive film covering transparent conductive film portion connecting additional and non-additional capacitance portions of pixel electrode
US5614730A (en) * 1990-11-09 1997-03-25 Seiko Epson Corporation Active matrix substrate
JP2007121793A (en) * 2005-10-31 2007-05-17 Epson Imaging Devices Corp Liquid crystal display device and manufacturing method thereof

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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