JPH09325364A - Active matrix substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance a rate of nondefective products by making the film thickness of a insulating film forming an auxiliary capacitance thinner than the film tickness of an insulating film forming a thin film transistor to reduce the leakage between a drain electrode and a source wiring. SOLUTION: A gate wiring 14 as a scanning wiring, a Cs wiring 15 for forming an auxiliary capacitance and a source wiring as a signal line 16 are formed on the transparent insulating substrate 11 of glass or the like so as to intersect with each other. A TFT as a switching element is provided in the vicinity of the intersection part. A pixel electrode 12 and a drain electrode 18 are connected by the contact hole 19 provided in an interlayer insulating film 17. Moreover, an auxiliary capacitance part is formed by allowing the drain electrode 18 and the Cs wiring 15 to hold a gate insulating film 20. Then, the gate insulating film 20 of a part forming the auxiliary capacitance is formed thinner 20a. Since the gap between the drain electrode 18 and the source wiring 16 can be formed large by this structure, leakage faults are remarkably reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix substrate used for liquid crystal display devices and the like.

[0002]

2. Description of the Related Art FIG. 5 is an equivalent circuit diagram showing a part of a conventional active matrix substrate, in which a gate wiring 34 as a scanning wiring and an auxiliary capacitance are formed on a transparent insulating substrate 31 such as glass by using aluminum or tantalum. Cs wiring for 3
5, the source wiring 36 is formed as a signal wiring by aluminum, tantalum, ITO or the like so as to intersect with each other. The pixel electrodes 32 are formed of a transparent conductive film such as ITO in the case of a transmissive type and are formed of aluminum or the like in the case of a reflective type and arranged in a matrix. A thin film transistor 33 is arranged as a switching element connected to the source wiring 36 and the pixel electrode 32.

FIG. 6 is a plan view of one picture element portion, and FIG.
A cross-sectional view between A'is shown in FIG. The pixel electrode 32 is formed so as to sandwich the interlayer insulating film 37, and the drain electrode 38 of the thin film transistor 33 is connected to the pixel electrode 32 through a contact hole 39. The pixel electrode 32 is shown in FIG.
Is omitted. Further, the drain electrode 38 and the Cs wiring 35 sandwich the gate insulating film 40 to form an auxiliary capacitance portion.

The thin film transistor 33 is constructed, for example, as shown in FIG. First, after forming the gate electrode 42,
The gate insulating film 40, the silicon semiconductor layer 43, and the etching stopper 44, which is a channel protection layer, are sequentially formed. Next, the n + silicon film 45 and the second n + silicon layer 4
6 are formed separately, and the first n + silicon layer 45 and the drain electrode 38 are electrically connected, and the second n + silicon layer 46 is electrically connected to the source electrode 47. The interlayer insulating film 37 and the pixel electrode 32 are not shown.

As described above, in the structure in which the wiring and the pixel electrode 32 are formed in different layers via the interlayer insulating film 37, it is possible to increase the aperture ratio. Further, since the pixel electrode 32 is in the upper layer of the interlayer insulating film 37 on the source wiring 36, it is possible to reduce the source-pixel leakage.

[0006]

However, since the drain electrode 38 and the source line 36 in the auxiliary capacitance portion formed to obtain the auxiliary capacitance are close to each other, the film abnormally patterned by dust or the like is formed. The drain electrode 38 and the source wiring 36 leak due to the remainder, and as a result, this is an obstacle to the improvement of the yield rate. Further, in order to form a large auxiliary capacitance, the drain electrode 38 and the source wiring 3
When the gap 6 was narrowed, it was a cause of inducing etching failure. This tendency is to increase the aperture ratio,
It becomes remarkable by thinning the Cs wiring 35.

[0007]

In order to solve the above problems, in the active matrix substrate of the present invention, a thin film transistor is provided near the intersection of the scanning wiring and the signal wiring, and the pixel electrode, the scanning electrode and the signal wiring are provided. It is formed so as to overlap through the insulating film, the auxiliary capacitance is formed by the electrode having the same potential as the pixel electrode, the auxiliary capacitance wiring and the insulating film between them, and from the film thickness of the insulating film forming the thin film transistor,
It is characterized in that the film thickness of the insulating film forming the auxiliary capacitance is thinner.

As a result, the leakage between the drain electrode and the source wiring caused by the proximity of the auxiliary capacitance portion and the source wiring described in the prior art is reduced. Further, electrostatic breakdown of the thin film transistor can be suppressed. as a result,
The rate of non-defective products can be improved.

The insulating film forming the thin film transistor and the insulating film forming the auxiliary capacitance are preferably gate insulating films.

With this structure, the interlayer insulating film can be formed thick and the parasitic capacitance between the wiring and the pixel electrode can be reduced.

Further, the gate insulating film may be composed of multiple layers, and the portion forming the auxiliary capacitance may have a smaller number of layers than the thin film transistor portion.

This structure facilitates manufacturing.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION

(Embodiment 1) Embodiment 1 of the present invention will be described with reference to FIGS. FIG. 1 is a plan view of one pixel portion of an active matrix substrate of the present invention, and FIG. 2 is a sectional view taken along line AA ′ of FIG. The active matrix substrate of the present invention is formed on a transparent insulating substrate 11 such as glass so that a gate wiring 14 as a scanning wiring, a Cs wiring 15 for forming an auxiliary capacitance, and a source wiring 16 as a signal wiring cross each other. There is. A TFT (thin film transistor) 13 is provided as a switching element near the intersection. Then, the pixel electrode 12 is formed separately from the wiring and the switching element via the interlayer insulating film 17. In addition, in order to make the drawing easy to understand, in FIG.
Is omitted. The pixel electrode 12 and the drain electrode 18 are
It is connected by a contact hole 19 provided in the interlayer insulating film 17.

Further, the drain electrode 18 and the Cs wiring 15 sandwich the gate insulating film 20 to form an auxiliary capacitance portion. Here, what is different from the conventional one is that the gate insulating film 20 in the auxiliary capacitance forming portion is thinly formed to be 20a. With this structure, a large gap between the drain electrode 18 and the source wiring 16 can be formed, and leak defects can be significantly reduced. This can also be explained by the following equation.

Cs = εS / d (where ε: dielectric constant of gate insulating film, S: area where Cs wiring and drain electrode overlap, d: film thickness of gate insulating film) It can be seen that the area S can be reduced by reducing the film thickness of. That is, the gap between the drain electrode 18 and the source wiring 16 can be increased.

Here, if the gate insulating film 20 is thinned over the entire surface, leakage is likely to occur at, for example, the intersection of the gate wiring 14 and the source wiring 16, which is not preferable.
Further, if the gate insulating film 20 in the TFT portion is made thin, electrostatic breakdown is likely to occur. Therefore, it is desirable not to thin the portion where the wirings other than the auxiliary capacitance forming portion intersect and the TFT portion by etching or the like.

As described above, in the structure in which the wiring and the pixel electrode 12 are formed in different layers via the interlayer insulating film 17, it is possible to increase the aperture ratio. Further, since the pixel electrode 12 is on the interlayer insulating film 17 on the source wiring 16, the leak between the source and the pixel can be reduced.

Further, by forming the auxiliary capacitance by the gate insulating film 20a without using the interlayer insulating film 17, the interlayer insulating film 17 can be formed thick, and the parasitic capacitance between the pixel electrode 12 and the wiring can be suppressed. .

An example of the manufacturing method of the present invention is shown in FIGS.
(F). First, tantalum is formed as the gate wiring 14, the gate electrode, and the Cs wiring 15 by about 300 nm in the same process (a), silicon nitride is formed by about 300 nm as the gate insulating film 20, and a silicon semiconductor layer (not shown) is formed by about 3 nm.
0 nm, an etching stopper layer (not shown) of about 300 n
m continuous film formation (b). Then, the etching stopper layer is patterned, an n + layer is formed to a thickness of about 50 nm and then etched to form a semiconductor portion of the TFT (not shown).

Then, the gate insulating film 20 in the auxiliary capacitance forming portion is etched to a thickness of about 200 nm (c). As a result, the drain electrode 18 formed in the step after forming Cs can be formed small. After that, ITO is formed with a film thickness of 150 nm as the source wiring 16, the source electrode, and the drain electrode 18 (d). At this time, the source wiring and the like may be formed in two layers of aluminum tantalum or the like in order to reduce the resistance.

After that, as in the prior art, the interlayer insulating film 17 is formed.
Then, 2 μm of acrylic resin or the like is formed as (e), and ITO is formed to 150 nm as the pixel electrode 12 (f). After that, an alignment film or the like is formed if necessary, and the active matrix substrate of the present invention is completed. Then, after bonding with the counter substrate, the liquid crystal is sealed to complete the liquid crystal display device.

As described above in detail, in the first embodiment of the present invention, since the gate insulating film in the auxiliary capacitance forming portion is thinned, the auxiliary capacitance forming portion (drain electrode 18) and the source wiring 16 are formed. The gap can be enlarged, and leakage due to dust or defective patterning can be prevented. When the overlapping length of the Cs wiring 15 and the drain electrode 18 (in the direction of the source wiring) is set, the Cs wiring 15 can be formed thin and the aperture ratio can be improved. It is possible to prevent leakage between wirings at the intersection with the wirings. And the like.

(Embodiment 2) Hereinafter, Embodiment 2 of the present invention
Will be described with reference to FIGS. 1 and 4. Note that the plan view is the same as that of the first embodiment, and therefore FIG. FIG. 4 is a cross-sectional view of Embodiment 2 of the present invention, and the cross section is the same as the AA ′ portion in FIG. 1. Further, the same parts as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted. In this embodiment, the gate insulating film is an upper layer gate insulating film 28 and a lower layer gate insulating film 29.
Shows a case of a two-layer structure. Here, in the auxiliary capacitance forming portion, the gate insulating film is a single layer having only one of them.

For example, tantalum oxide (200 nm) is formed as the lower gate insulating film 29 and silicon nitride (100 nm) is continuously formed as the upper gate insulating film 28. Then, selective etching is performed by a photoresist method and a hydrofluoric acid wet etching method. Since the silicon nitride 28 can be removed only in the capacitance forming portion, a single layer can be formed. At this time, it is preferable to form tantalum oxide by an anodic oxidation method because a film without pinholes can be obtained.

Here, the number of gate insulating films is shown only when one of two layers is removed, but the number of gate insulating films is not limited to this. Obviously, one or two layers may be removed.

In this case, the auxiliary capacitance is connected to the auxiliary capacitance wiring 1
The Cs on Com method, which is formed by stacking the drain electrode 18 and the drain electrode 18 on each other, has been described. is there.

[0027]

As described above in detail, according to the present invention, a thin film transistor is provided in the vicinity of an intersection of a scanning wiring and a signal wiring so that the pixel electrode, the scanning electrode and the signal wiring overlap with each other through an insulating film. The thickness of the insulating film that forms the auxiliary capacitance is formed by the electrode having the same potential as the pixel electrode, the auxiliary capacitance wiring, and the insulating film that forms the thin film transistor. Is thinner. This structure reduces leakage defects, and
Since the electrostatic breakdown of the thin film transistor can be suppressed, improvement of the non-defective product rate can be expected. As a result, the manufacturing cost can be significantly reduced.

Further, the insulating film forming the auxiliary capacitance is
By using the gate insulating film, the interlayer insulating film can be formed thick and the parasitic capacitance between the wiring and the pixel electrode can be reduced.

Further, since the gate insulating film has a multi-layer structure and the number of layers for forming the auxiliary capacitance is smaller than that of the thin film transistor portion, selective etching can be facilitated and manufacturing can be simplified.

[Brief description of drawings]

FIG. 1 is a plan view of one picture element portion of an active matrix substrate of the present invention.

FIG. 2 is a cross-sectional view taken along the line A-A ′ in FIG.

FIG. 3 is a diagram showing an example of a method for manufacturing one picture element portion of the active matrix substrate according to the first embodiment of the present invention.

FIG. 4 is a sectional view of one picture element portion of an active matrix substrate according to a second embodiment of the present invention.

FIG. 5 is a partial equivalent circuit diagram of a conventional active matrix substrate.

FIG. 6 is a plan view of one picture element portion of a conventional active matrix substrate.

7 is a cross-sectional view taken along the line A-A ′ in FIG.

8 is a cross-sectional view taken along the line B-B ′ of FIG.

[Explanation of symbols]

 11: transparent insulating substrate 12: pixel electrode 13: thin film transistor 14: gate wiring 15: Cs wiring 16: source wiring 17: interlayer insulating film 18: drain electrode 19: contact hole 20: gate insulating film 20a: auxiliary capacitance gate insulating Film 28: Upper layer gate insulating film 29: Lower layer gate insulating film

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 29/78 619A

Claims (3)

[Claims] 1. A thin film transistor is provided in the vicinity of an intersection of a scanning wiring and a signal wiring, the pixel electrode and the scanning electrode and the signal wiring are formed so as to overlap with each other through an insulating film, and the auxiliary capacitance has the same potential as the pixel electrode. In the active matrix substrate formed of the auxiliary capacitance wiring and the insulating film between them, the insulating film forming the auxiliary capacitor is thinner than the insulating film forming the thin film transistor. And active matrix substrate. 2. The active matrix substrate according to claim 1, wherein the insulating film forming the auxiliary capacitance is a gate insulating film. 3. The active matrix substrate according to claim 2, wherein the gate insulating film has a multi-layered structure, and the number of layers in the portion for forming the auxiliary capacitance is smaller than the number of layers in the thin film transistor portion.