JP2618034B2 - Matrix substrate and manufacturing method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a matrix substrate, and more particularly to a reduction in resistance of electrode lines and an increase in withstand voltage between electrode lines effective in a large-area active matrix knitted image display device. And a method of manufacturing the same.

2. Description of the Related Art Due to recent advances in microfabrication technology, liquid crystal materials, packaging technology, and the like, television images that are as small as 2 to 6 inches, but which do not hinder practical use of liquid crystal panels, can be obtained on a commercial basis. Was. A so-called active-type liquid crystal panel that easily realizes color display by forming an RGB colored layer on one of the two glass plates that compose the liquid crystal panel, and incorporates a switching element for each pixel. Thus, an image having less crosstalk and a high contrast ratio is guaranteed. Such liquid crystal panels have 120-240 scanning lines and 240-7 signal lines.
A matrix formation of about 20 lines is standard. For example, as shown in FIG.
A COG (Chip-chip) that directly connects the semiconductor integrated circuit chip 3 that supplies a drive signal to the electrode terminals 6 of the scanning lines formed above.
On-Glass method, or a connection film 4 based on, for example, a polyimide resin thin film and having a gold-plated copper foil terminal group (not shown) is fixed to an electrode terminal group 5 of a signal line while being pressed with an adhesive. An electric signal is supplied to the image display unit by a mounting means such as a system that performs the operation. Here, two mounting methods are shown simultaneously for the sake of convenience, but it goes without saying that one of the mounting methods is selected for the solid line. Note that 7,
Reference numeral 8 denotes a wiring path that connects the image display unit at the center of the liquid crystal panel 1 to the electrode terminals 5 and 6 for signal lines and scanning lines, and does not necessarily need to be formed of the same conductive material as the electrode terminals.

Reference numeral 9 denotes another glass plate having a transparent conductive counter electrode common to all picture elements, and the two glass plates 2, 9 are separated by a predetermined distance by a spacer such as a quartz fiber or a plastic bead. The gap is a closed space sealed with a sealing material and a sealing material, and the closed space is filled with liquid crystal. In order to realize color display, an organic thin film containing one or both of a dye and a pigment called a colored layer is applied to the closed space side of the glass plate 9 to provide a color display function. Also called a color filter. Then, depending on the properties of the liquid crystal material, a polarizing plate is stuck on one or both of the upper surface of the glass plate 9 and the lower surface of the glass plate 2, and the liquid crystal panel 1 functions as an electro-optical element.

FIG. 11 is an equivalent circuit diagram of an active liquid crystal panel in which insulated gate transistors 10 are arranged as switching elements for each picture element. The elements drawn by solid lines are formed on one glass substrate 2 and the elements drawn by broken lines are formed on the other glass substrate 9. The scanning lines 11 (8) and the signal lines 12 (7) are formed on the glass substrate 2 at the same time as the formation of the thin film transistor 10 using, for example, amorphous silicon as a semiconductor layer and a silicon nitride film (Si ₃ N ₄ ) as a gate insulating film. Produced. The liquid crystal cell 13 is a closed space composed of a transparent conductive picture element electrode formed on the glass substrate 2, a transparent conductive counter electrode 15 formed on the color filter 9, and two glass plates. And is electrically treated the same as a capacitor. In order to align the liquid crystal molecules in a predetermined direction, it is necessary to form an alignment film on the counter electrode 15 and the picture element electrode, but the details are omitted here.

Although the storage capacitor 16 in FIG. 11 is not always an essential component for an active liquid crystal panel, it improves the efficiency of use of the driving signal source, suppresses the stray parasitic capacitance, and operates at high temperature. Image flicker (flicker)
It is effectively employed for prevention and the like and is appropriately adopted. Reference numeral 17 denotes a conductive path common to all the storage capacitors 16 and generally includes a counter electrode 15.
And the common conductive furnace 17 is used by being connected.

Insulated gate transistor 10 as a switching element
Although it is difficult to say that it has been industrially established in terms of both materials and processes, FIGS. 12 and 13 show two typical pattern layouts, respectively, and FIG. A-
FIGS. 14 and 15 are cross-sectional views taken along the lines A ′ and BB ′,
The manufacturing process of the insulated gate transistor will be briefly described below.

First, a metal layer 11 serving also as a gate electrode and a scanning line of an insulated gate transistor is coated on one main surface of a glass substrate 2 with chromium (Cr) having a thickness of 0.1 μm using a film forming apparatus such as sputtering. To form a selective pattern. Next, in the case of the insulated gate transistor shown in FIGS. 12 and 14, SiNx-a and Si-SiNx are formed by P-CVD (plasma film formation).
After continuously depositing a layer with a thickness of, for example, 0.4-0.05-0.1 μm and selectively leaving an upper SiNx layer serving as an etching stopper layer 20, an amorphous silicon layer containing impurities is similarly formed on the entire surface. Deposit by P-CVD. Then, an amorphous silicon layer (n + a.Si) containing impurities and amorphous silicon layers (a.Si) 21 and 22 containing no impurities are formed as semiconductor layers in an island shape, and the gate insulating layer 23 is selectively formed. Expose. After an opening 24 for connecting to the scanning line 11 is formed in the gate insulating layer 23 to expose a part of the scanning line 11, the opening 24 is made of, for example, aluminum (Al) having a thickness of 1 μm including the opening 24. Gate wiring
An amorphous silicon layer containing impurities on the etching stopper layer 20 by selectively forming source / drain wirings 26 and 27 on the island-like semiconductor layer 25 and using the source / drain wirings 26 and 27 as a mask. Is removed to complete an insulated gate transistor.

In the case of the insulated gate transistor shown in FIGS. 13 and 15, SiNx-a.Si-n + a.S by P-CVD (plasma film formation)
For example, three layers i are continuously deposited to a thickness of, for example, 0.4-0.1-0.1 μm, and an amorphous silicon layer containing impurities (n + a · Si) and an amorphous silicon layer containing no impurities (a · Si ) Are formed in an island shape as the semiconductor layers 21 and 22, and the gate insulating layer 23 is selectively exposed. After an opening 24 for connection to the scanning line 11 is formed in the gate insulating layer 23 to expose a part of the scanning line 11, a gate wiring made of aluminum having a thickness of, for example, 1 μm including the opening 24 is formed. 25 and source on the island-like semiconductor layer
The drain wirings 26 and 27 are selectively formed, and the source / drain wirings 26 and 27 are used as a mask to selectively remove only the amorphous silicon layer 21 containing impurities from the semiconductor layer. Complete.

In order to improve the heat resistance of the insulated gate transistor, a barrier metal is formed between the source / drain wirings 26 and 27 made of Al and the amorphous silicon layer 21 containing impurities.
A technique of interposing a metal thin film layer such as Ti (titanium) or Cr or a silicide thin film layer, or a gate wiring 25 made of Al by forming a passivation of a metal layer constituting a scanning line exposed in the opening 24
A detailed description of a technique for stacking another metal layer or a silicide layer in order to prevent a contact failure from occurring and a technique for forming a pixel electrode made of ITO will be omitted.

Problems to be Solved by the Invention In P-CVD (plasma film formation), the substrate temperature at the time of film formation is as low as about 300 ° C., and SiNx or a. Si peels off and floats in the reaction chamber as dust or foreign matter of about 1 μm and adheres to a film-formed substrate such as a glass substrate. As a result, a large number of pin holes are present in the formed film, and the It is known that a short circuit occurs in a multilayer wiring and the yield does not increase.

Efforts to reduce such fine dust and foreign matter are generally treated as know-how, and are rarely disclosed externally. However, several improvements have been demonstrated from a technical point of view regarding device structures and manufacturing methods that are resistant to dust and foreign matter. It will be described based on FIG.

In FIG. 16, the scanning line (gate) 11 is formed of Ta (tantalum) and its surface is anodized so that the performance index of the insulated gate transistor does not decrease even if the gate insulating layer is thickly applied. Ta ₂ O ₅ layer 28 with high dielectric constant
After that, an insulated gate transistor is manufactured through three-layer deposition of SiNx-a.Si-SiNx. That is, the gate insulating layer has a _two- layer structure of the Ta ₂ O ₅ layer 28 and the SiNx layer 23.

In FIG. 17, an opening 29 is formed in the first gate insulating layer 23 'on the scanning line 11 so that the figure of merit of the insulated gate transistor does not decrease even if the gate insulating layer is thickly applied.
After the three layers of SiNx-a.Si-n + a.Si are deposited,
An insulated gate transistor is manufactured. That is, the gate insulating layer is doubled with 23 'and 23 SiNx.

According to these manufacturing methods, it is apparent that the dielectric strength between the scanning line 11 and the source / drain wirings 26 and 27 is improved and the yield is increased for the following reasons.

One reason is that the formation of the gate insulating layer is divided into two, and if a cleaning step is introduced during that time, the removal of dust and foreign matter is promoted and the number of pinholes is reduced at random. Second, in FIG. 16, the shoulder portion of the scanning line 11 is rounded by anodic oxidation, so that the coverage characteristic of the gate insulating layer 23 is improved, and in FIG. 17, the gate at the shoulder portion of the scanning line 11 is improved. This is because the thicker insulating layer 23 is more resistant to dust and foreign matter.

However, with respect to the further improvement of the withstand voltage, since there is a step in the scanning line, and in the case of the conventional improvement example in which the constituent material of the scanning line is Ta or an alloy of Ta and Mo, the resistance of the scanning line is also reduced. Not enough. Lowering the resistance of the scanning line is an essential design item as the screen size increases, but for that, it is necessary to use a metal with lower resistance from the material side, and increase the thickness of the wiring path from the device side. Is necessary. In particular, as the thickness of the wiring path increases, the required increase in the thickness of the gate insulating layer becomes an unacceptable condition from the viewpoint of a decrease in the figure of merit of the insulated gate transistor and a decrease in productivity. Come.

Means for Solving the Problems The present invention has been made in view of the above-mentioned situation, and selects a metal which is an insulator by low-resistance and anodic oxidation when forming a scanning line, and surrounds the periphery of the scanning line with the insulator. By filling in, the scanning lines of the flattened structure are obtained, and the specific means are as described in the claims.

The scanning line made of a low-resistance metal layer has a substantially flat surface with its surface and side surfaces buried with an insulator, so that the semiconductor layer is continuously formed or is formed via the insulator and the semiconductor layer. The withstand voltage between the conductive wiring and the conductive wiring is significantly improved.

Embodiment FIGS. 1 to 3 are cross-sectional views showing steps of manufacturing an active matrix substrate according to a first embodiment of the present invention. First, as shown in FIG. 1, Al having a thickness of 0.1 μm is deposited on one main surface of an insulating substrate, for example, a glass plate 2, and an Al layer (metal layer) 3 is formed.
The value is set to 0, and a photosensitive resin pattern 31 corresponding to the scanning line pattern is selectively formed on the Al layer 30. Subsequently, as shown in FIG. 2, by anodic oxidation in a container containing a chemical conversion solution, the Al layer 30 is selectively insulated by using the photosensitive resin pattern 31 as a mask to form an Al ₂ O ₃ layer 32. The scanning line 11 is immediately below the conductive resin pattern 31. For the selective anodic oxidation of Al, see JP-B-59-34798. After that, the photosensitive resin pattern 31 is removed, and SiNx-a / Si-SiNx
Through the three-layer deposition, an insulated gate transistor is completed as shown in FIG. Needless to say, since the Al ₂ O ₃ layer 32 is a transparent insulator, application to an active substrate constituting a transmission type liquid crystal panel does not hinder at all. In FIG. 3, reference numeral 20 denotes an etching stopper layer, reference numerals 21 and 22 denote semiconductor layers, reference numeral 23 denotes insulating layers 26 and 27, and source / drain wirings.

In the first embodiment, Al is changed to Al ₂ O by anodic oxidation.
_{Since the} film thickness increases when it changes to ₃ (0.1 → 0.15μ
m), for the subsequently deposited SiNx layer (insulating layer) 23, it can be seen that the effective step of the scanning line 11 has been reduced from 0.1 μm to 0.05 μm.

In the second embodiment of the present invention shown in FIGS. 4 to 6, the object is to further reduce the step, and the Al layer 30 is selectively anodized using the photosensitive resin pattern 31 as a mask. At this time, as shown in FIG. 4, the exposed Al layer 30 is oxidized by about 0.1 μm to form an Al ₂ O ₃ layer 32 ′.
At this point, the anodic oxidation is temporarily interrupted. Then, after the photosensitive resin pattern 31 is removed, the anodic oxidation is continued until the periphery of the scanning line 11 becomes the Al ₂ O ₃ layer 32 completely. 2
At the time of the second anodic oxidation, the Al ₂ O ₃ layer 33 also grows on the scanning line 11 as shown in FIG. 5, and the effective step is further reduced to a substantially flat surface. After that, three layers of SiNx-a and Si-SiNx are deposited in the same manner as in the conventional example, and the insulated gate transistor is completed as shown in FIG. 6 (for details of other components, see the description of the conventional example). ).

In the second embodiment, the gate insulating layer is formed of SiNx and Al ₂ O at the time of forming the opening 24 for taking out the electrode to the scanning line 11.
₃ and it is difficult to detect the end point of the etching of Al ₂ O ₃ because the scanning line 11 is Al, and there is no etching method with a large selectivity between Al and Al ₂ O ₃ . In this case, after removing the photosensitive resin pattern 31, a mask made of the photosensitive resin is introduced again at a predetermined position on the scanning line, and if the anodic oxidation is restarted, the Al surface can be left as it is. It should be additionally noted that the etching of can be made only with SiNx as in the first embodiment.

In the third embodiment of the present invention shown in FIGS. 7 to 9, the scanning line 11 is formed of a two-layer film of Al and a noble metal or a silicide, thereby avoiding the problems occurring in the second embodiment. As shown in FIG. 7, a 0.1 μm Al layer 30 and a 0.05 μm
A noble metal such as gold (Pt) or a silicide layer such as molybdenum silicide is deposited, and the noble metal or silicide layer is selectively removed using the photosensitive resin pattern 31 as a mask to expose the underlying Al layer 30 as a layer 34. . After that, if the noble metal, the photosensitive resin pattern 31 is removed and then the noble metal layer is used as a mask, and if the silicide layer is used, the Al layer 30 is anodized using the photosensitive resin pattern as a mask to form the Al ₂ O ₃ layer 32.
The glass substrate 2 having a substantially flat surface as shown in FIG. 8 is obtained. After that, SiNx-a / Si-SiNx
After completion of the three-layer deposition, the insulated gate transistor is completed as shown in FIG. 9 for details of other components (see the description of the conventional example).

Advantageous Effects of the Invention As is clear from the above description, according to the present invention, a scanning line made of a metal such as Al on an insulating substrate is formed by anodic oxidation on the surface around its periphery in order to reduce an effective step. Not only is it formed by being buried with an insulating metal oxide, for example, Al ₂ O ₃ , but it is also an insulator on its surface
Al ₂ O ₃ or the like, or a noble metal or a silicide which is a conductor is applied, and is formed to have almost the same height as Al ₂ O ₃ or the like filling the periphery. Therefore, even if a conductive line perpendicular to the scanning line is formed through the semiconductor layer or the insulating layer and the semiconductor layer to be continuously applied, the semiconductor layer and the insulating layer are applied with good coverage. An active matrix substrate having a high withstand voltage with respect to the conductive line and a high yield can be obtained.

A matrix substrate in which a low-resistance wiring path is formed to be almost flat with its periphery buried with an insulator (eg, Al ₂ O ₃ ) is not limited to the liquid crystal panel described in the present invention. It is also effective for a matrix device using a semiconductor light emitting material such as EL, and particularly exhibits a remarkable effect in a large screen display device having a long wiring path. This is because if the wiring path is long, it is difficult to avoid the film thickness from increasing even if a low-resistance material such as a metal layer such as Al is used to reduce the resistance of the wiring path. This is because the coverage of the insulating layer and the semiconductor layer deteriorates, and the withstand voltage of the multilayer wiring via the insulating layer and the semiconductor layer rapidly decreases. According to the present invention, even if the thickness of the metal layer such as Al is increased, the time for anodic oxidation is prolonged, or only the formation voltage is increased, and the surroundings are made of an insulator (for example,
Al ₂ O ₃ ) fills the surroundings and forms a substantially flat wiring path, so it is possible to keep high dielectric strength,
Its industrial value is remarkably high.

[Brief description of the drawings]

1 to 3 are cross-sectional views of a matrix substrate according to a first embodiment of the present invention in a manufacturing process, and FIGS. 4 to 6 are cross-sectional views of a matrix substrate in a second embodiment of the present invention. , FIG. 7 to FIG. 9 are cross-sectional views in the manufacturing process of the matrix substrate in the third embodiment of the present invention, FIG. 10 is a perspective view showing a mounting means for a liquid crystal panel, and FIG. 12 and 13 are equivalent circuit diagrams of an active type liquid crystal panel, FIG. 12 and FIG. 13 are pattern layout diagrams of a conventional insulated gate transistor, FIG. 14 and FIG. 15 are sectional views thereof, and FIG. 16 and FIG. 1 shows a cross-sectional view of a completed insulated gate transistor. 1 ... liquid crystal panel, 2 ... (active) matrix substrate, 3 ... semiconductor chip, 4 ... connection film, 9 ...
Color filter, 10 …… Insulated gate transistor, 11
…… scanning line, 12 …… signal line, 13 …… liquid crystal cell, 20 ……
(For etching stopper) SiNx layer, 21 ... amorphous silicon layer containing impurities, 22 ... amorphous silicon layer containing no impurities, 23 ... gate insulating layer (of SiNx), 25 ... gate wiring , 26, 27 ... source / drain wiring, 28 ... Ta
₂ O ₅ layer, 29: opening, 30: Al layer, 31: photosensitive resin pattern, 32, 33: Al ₂ O ₃ layer, 34: noble metal or silicide layer.

Claims (3)

(57) [Claims] 1. A scanning line mainly containing aluminum as the Al ₂ O ₃ insulator by anodic oxidation on one principal surface of the insulating substrate, the periphery of said scanning lines and said scanning lines the Al ₂ O _Three
A thin film transistor that is formed by filling the scan line and the periphery of the scan line to be flattened and including at least a gate insulating layer, a semiconductor layer, and a signal line orthogonal to the scan line via the semiconductor layer and the semiconductor layer. A matrix substrate, characterized in that: 2. One of other metal or silicide layers is formed on one main surface of an insulating substrate on a scanning line mainly composed of aluminum which becomes an insulator Al ₂ O ₃ by anodic oxidation. The thin film transistor is formed by filling the Al ₂ O ₃ and flattening the scanning line and the periphery, and including at least a gate insulating layer, a semiconductor layer, and a signal line orthogonal to the scanning line via the semiconductor layer and the semiconductor layer. A matrix substrate characterized in that: 3. An insulator formed on an insulating substrate by anodic oxidation.
A step of applying a gate metal layer containing aluminum as a main component to become Al ₂ O ₃ , a step of selectively forming a photosensitive resin pattern on the gate metal layer, and using the photosensitive resin pattern as a mask, A step of partially anodizing the gate metal layer, and after removing the photosensitive resin pattern, continuing the anodic oxidation to fill the pattern and the periphery of the gate metal layer with the Al ₂ O ₃ and the gate metal layer And a step of forming a thin film transistor including at least a gate insulating layer, a semiconductor layer, and a signal line orthogonal to the scanning line via the semiconductor layer and the semiconductor layer.