JPH01279490A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To attain data exchange between memory cells at a high speed internally by providing a data exchange function from a memory cell to another memory cell to a semiconductor memory. CONSTITUTION:A data S0 to be exchanged is read from a memory cell 17 of an array 11 from the memory cell array 11 by a row decoder 12 and a column decoder 13, amplified by a sense amplifier 16 and written in a buffer 14. Then other data S1 to be exchanged is read from the memory cell 18 in the array 11 by the row decoder 12 and the row decoder 13, sensed by the amplifier 16 to read the cell 17 by the row decoder 12 and the column decoder 13 thereby writing the data S1 sensed. Then the data S0 written in the buffer 14 is written in the cell 18 of the other data S1 to be exchanged by using the decoders 12, 13 while designating the address. As a result, the data S0 of the cell 17 stored in the buffer at first and the data S1 called from the cell 18 are exchanged.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to memory devices, and more particularly to semiconductor memory cells.

[Conventional technology]

Conventionally, data exchange between memory cells in this type of semiconductor memory has been performed using a semiconductor memory and an external register. FIG. 3 shows a conventional example in which data is exchanged between memory cells in a semiconductor memory 200. First, in a read cycle, two pieces of data to be exchanged in the memory cell array 31 are Q-selected by the row decoder 321 and the column decoder 33, and the values are held in the external register 100 through the input/output buffer 35 to jII. Next, in the write cycle, the row decoder 32 and column decoder 33 mutually exchange and designate the addresses of data to be exchanged, and the two data are read from the external register 100 through the human output buffer 35 into the memory cell array.

Let one data to be exchanged be A and the other data be B.

A and H are stored in the memory cell. A is taken out to the external register, one read cycle is performed, one read cycle and one write cycle are performed to read B to the external register and write AK, and one write cycle is performed to write BK from the external register. , a total of two write cycles and two read cycles are required.

[Problem to be solved by the invention]

Data exchange in the conventional semiconductor memory described above is performed via an external register, and therefore requires two read and write cycles for the semiconductor memory, resulting in a disadvantage in that data exchange becomes slow.

[Failure to solve the problem]

A semiconductor memory of the present invention includes a memory cell array, a row decoder that determines the row address of the memory cell array, a column decoder that stores the column address, and a buffer connected to the column decoder.
It has a sense amplifier connected to a buffer and an internal timing generation circuit, and has a function of exchanging data in one or more memory cells with data in another memory cell.

[Example 1] FIG. 1 is a block diagram of a first embodiment of the present invention.

The memory cell array 11 is a part that stores binary information, and the address where the data is stored is determined by the row decoder 13.

The buffer 14 is necessary to hold the data taken out from the memory cell array 11, and the sense amplifier 16 amplifies the data in the memory cell array 11.
Also, writing and reading are performed in the memory cell array 11. First, the row decoder 12 and column decoder 13 read one data So to be exchanged from the memory cell array 11 from the memory cell 17 in the memory cell array 11.
The signal is amplified by the sense amplifier 16, and written to the buffer 14 after being amplified by the sense amplifier 16. and row decoder 1
2 and the column decoder 13 read the other data S+7 to be exchanged from the memory cell 18 in the memory cell array 11, and while the sense amplifier 16 remains sensing, the row decoder and column decoder read out the memory cell 17, and the sense Write the data SI as it is.

Next, the data So written in the buffer 14 is written into the memory cell 18 of the other data S1 to be exchanged by specifying an address using the row decoder 12 and the column decoder 13. As a result, the data SO of the memory cell 17 initially held in the buffer can be exchanged with the data Sl read from the memory cell 18.

[Example 2] FIG. 2 is a block diagram of a second embodiment of the present invention.

Memory cell 27 in memory cell array 20.21
．． A row decoder 22 and a column decoder 23 that select 28, a sense amplifier 25 that senses the selected data, a buffer 24 that holds the sensed data, and an internal typing generation circuit 26 that controls each internal block. It can be configured.

First, the row decoder 22 and column decoder 23 read data Do from the memory cell 27 in the memory cell array 20, sense it with the sense amplifier 25, and then write it into the buffer 24. Next, row decoder 22 and column decoder 23
As a result, the data Dl to be exchanged is read from the memory cell 28 in the memory cell array 21 and, while being sensed, the address of the memory cell 27 is designated by the row decoder 22 and the column decoder 23 and written. Next, the data in the buffer 24 is written into the memory cell 28. As a result, the data Do of the memory cell 27 and the data Dl of the memory cell 28 can be exchanged.

In this embodiment, the memory cell array is divided into two memory cell arrays 20 and 21, and a row decoder is attached to each. Therefore, when exchanging data between memory cells at the same row address, the exchange between memory cell array 20 and memory cell array 21 is not possible. Since data can be exchanged while the same row address is selected, there is an advantage that the precharge cycle can be omitted and the speed can be increased.

〔Effect of the invention〕

As explained above, the present invention makes it possible to exchange data between memory cells without going through an external register by providing a semiconductor memory with a data exchange function from memory cell to memory cell. This has the effect of allowing high-speed internal data exchange between memory cells, which requires .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a block diagram of a second embodiment of the present invention, and FIG. 3 is a block diagram of a conventional example. 11.21.22...Memory cell array, 12
゜23.24... Row decoder, 13.25...
... Column de''der, 16.27 ... Sense amplifier, 14.26 ... Buffer, 15.28.
...Internal timing generation circuit. Agent Patent Attorney Uchihara Oto No. 1, Figure 2, Ward 3

Claims (1)

[Claims] A memory cell array, a row decoder and a column decoder connected to this memory cell array, a buffer connected to the column decoder, a sense amplifier connected to this buffer, and an internal circuit that controls the row decoder, column decoder, buffer, and sense amplifier. 1. A semiconductor memory comprising a timing generation circuit for exchanging data of one or more memory cells in the memory cell array with data of another memory cell.