JPS60147996A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To set the cycle time of a system by the read cycle and by holding a writing indicating signal in correspondence to the number of shifts of a shift register. CONSTITUTION:When a clock CLK is inputted to a shift register SR1 and an OR gate 3, the first step of the SR1 sets a WE1 signal by one cycle, an output of an OR gate 2 becomes ''H'' and an output of the gate 3 is inputted to a register 5. An address signal AD specified the prescribed address of a memory array 9 through an address decoder driver 6. On the other hand, the output of the gate 2 is inputted to a register 7 through an OR gate 4, and writing data DIN are written in the specified address of the array 9. When the next CLK is inputted into the SR1, the output of the gate 2 holds ''H'', the writing indicating signal in the point P is set up to two cycles of the CLK, and writing of the Q/R serving as the inner signal is held.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a semiconductor memory device, and particularly to a commit cycle (
Wl(ITE CYOLB) tl-Read cycle #(R
EAD C! YOLIl: ) n times (H, = 1!2)
Random access memory that can be configured to
FLAM).

Conventional technology and problems As already known, RAM chips are basically.

It consists of a memory cell array, address decoder drivers on the X side and Y side, a write amplifier, and a sense amplifier. In such a configuration, WRITE 0Y is generally lower than RBAD oyct,g.
OI and E+ are slow because memory cells have structural limitations, and as they become smaller, the memory contents change due to the influence of noise etc.
There was a limit to how fast E 0YOLE could go. On the other hand, in recent years, there has been significant progress in increasing the speed of RAM, especially when used as a buffer memory.
OLI3 TIMI! Since i is restricted to the slower one, such READ 0YOIJ and WRITEOY
The discrepancy in OIJ was an obstacle to speeding up the system2.

Purpose of invention The object of the present invention is to solve the above problems.

WRITBOYOLBtl-RI! ! AD 0YOLE
WRI is based on the idea of controlling by n times (n≧2)
0YOL of a system that was constrained to TE 0YOLB
BTIMIi! The object of the present invention is to provide a RAM 1 that can be set with READ 0YOLE, thereby increasing the speed of the system.

Structure of the Invention According to the present invention, a shift register to which clock No. 1B and a write instruction signal are input, a plurality of OR gates to which the clock signal is input, and an address signal and write data are input. This is achieved by providing a semiconductor memory device comprising each register and a register into which read data is input, and in which the write instruction signal is held in accordance with the number of shifts of the shift register. .

Embodiment FIG. 1 is a block diagram showing the basic configuration of a RAM as an embodiment of the present invention. In FIG. 1, a RAM according to the present invention includes a shift register 1. or gate 2,3
．． and 4. Registers 5°7 and 11, address decoder driver 6° write amplifier 8. Memory cell array9. and a sense amplifier 10.

FIG. 2 is a timing chart showing the signal timing of the RAM shown in FIG. The instruction signals (WEx, 2) O, M and H read data (DOUT) are shown with OLK as a reference. In this case,
WRITg 0YOLIii is Rf! XAD 0YO
This is shown for twice LE, that is, n=2.

The operation of such a configuration and signal timing will be described next.

When OLK as an external signal is input to shift register 1 and OR gate 3, the first stage of shift register 1 becomes W.
BI signal f 10YOI, set for 8 minutes. As a result, the output of the OR gate 2 becomes high ()l), and at the same time, the output of the OR gate 3 is input to the register 5, and the address signal (AD) is sent to the predetermined address of the memory cell play via the address decoder driver 6. Specify. On the other hand, the output of OR gate 2 passes through OR gate 4'ft to register 7.
The write data CD, N) input to the write amplifier 8
The data is written to the designated address of the memory cell array 9 through the process. Even if the n1 signal ends in one cycle.

When the next OLK is input to shift register 1, the next stage becomes H.
Therefore, the output of the OR gate 2 is held at Hf, and the write instruction signal WE2 as an internal signal at the point P is set up to 20YOI, Ft of OLE. Therefore, Q/R as an internal signal can hold the write. On the other hand, if the input of the internal signal Q/R changes due to the next OLK when the primary WBl signal is input, a malfunction will occur, so the WB2 signal and 01. The OR gate 4 constitutes an OR circuit.

In the above example, we explained the case where shift register 1 has two stages, but by changing the number of shifts, WRITI
it 0YOLFi wo 几BAI) 0YOI, F! n of
It is possible to set it twice.

On the other hand, read data CDOUT) is taken into the register 11 from the memory cell array 9 via the sense amplifier 10t-, and is output every 10YOIg of OLK.

Effects of the Invention According to the present invention, after writing to the memory area once, R
A control memory that uses only ead has a significant effect in speeding up 0YCLH.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of a RAM as an embodiment of the present invention, and FIG. 2 is a timing chart showing signal timing of the RAM shown in FIG. (Explanation of symbols) 1...Shift register, 2, 3.4...OR gate. 5, 7.11...Register. 6...Address decoder driver. 8...Light amplifier. 9...Memory cell array. lO...Sense amplifier.

Claims (1)

[Claims] 1. A shift register to which a clock signal and a write instruction signal are input, a plurality of OR gates to which the clock signal is input, each register to which an address signal and write data are input, and a register to which read data is input. What is claimed is: 1. A semiconductor memory device comprising: a semiconductor memory device, wherein the write instruction signal is held in correspondence with the number of shifts of the shift register.