JPS60147996A - Semiconductor storage device - Google Patents

Semiconductor storage device

Info

Publication number
JPS60147996A
JPS60147996A JP59003557A JP355784A JPS60147996A JP S60147996 A JPS60147996 A JP S60147996A JP 59003557 A JP59003557 A JP 59003557A JP 355784 A JP355784 A JP 355784A JP S60147996 A JPS60147996 A JP S60147996A
Authority
JP
Japan
Prior art keywords
gate
signal
register
output
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59003557A
Other languages
Japanese (ja)
Inventor
Kazuo Oami
大網 和夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59003557A priority Critical patent/JPS60147996A/en
Publication of JPS60147996A publication Critical patent/JPS60147996A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices

Abstract

PURPOSE:To set the cycle time of a system by the read cycle and by holding a writing indicating signal in correspondence to the number of shifts of a shift register. CONSTITUTION:When a clock CLK is inputted to a shift register SR1 and an OR gate 3, the first step of the SR1 sets a WE1 signal by one cycle, an output of an OR gate 2 becomes ''H'' and an output of the gate 3 is inputted to a register 5. An address signal AD specified the prescribed address of a memory array 9 through an address decoder driver 6. On the other hand, the output of the gate 2 is inputted to a register 7 through an OR gate 4, and writing data DIN are written in the specified address of the array 9. When the next CLK is inputted into the SR1, the output of the gate 2 holds ''H'', the writing indicating signal in the point P is set up to two cycles of the CLK, and writing of the Q/R serving as the inner signal is held.

Description

【発明の詳細な説明】 技術分野 本発明は半導体記憶装置に関し、特に誓込みサイクル(
Wl(ITE CYOLB)tl−読出しサイク#(R
EAD C!YOLIl: )のn倍(H,=1!2)
に設定することが可能なランダム アクセス メモリ(
FLAM)に関する。
DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a semiconductor memory device, and particularly to a commit cycle (
Wl(ITE CYOLB) tl-Read cycle #(R
EAD C! YOLIl: ) n times (H, = 1!2)
Random access memory that can be configured to
FLAM).

従来技術と問題点 既に知られるように、RAMチップは基本的に。Conventional technology and problems As already known, RAM chips are basically.

メモリ・セル・アレイ、X側およびY側のアドレス・デ
コーダ・ドライバ、ライト・アンプおよびセンス・アン
プにより構成されている。このような構成において一般
的にRBAD oyct、gに比べてWRITE 0Y
OI、E+は遅く、これはメモリ・セルには構造上の制
限があるからであり、小型化すればするほどノイズ等の
影響によりメモリ内容が変化してしまい従ってWRIT
E 0YOLEの高速化には限界があった。一方、近年
、RAMの高速化、特にバッファメモリとして使用する
場合の高速化には著しい進展があるが、システムの0Y
OLI3 TIMI!iは遅い方に制約されてしまうた
め、このようなREAD 0YOIJとWRITEOY
OIJの不一致はシステムの高速化2図る上で障害とな
っていた。
It consists of a memory cell array, address decoder drivers on the X side and Y side, a write amplifier, and a sense amplifier. In such a configuration, WRITE 0Y is generally lower than RBAD oyct,g.
OI and E+ are slow because memory cells have structural limitations, and as they become smaller, the memory contents change due to the influence of noise etc.
There was a limit to how fast E 0YOLE could go. On the other hand, in recent years, there has been significant progress in increasing the speed of RAM, especially when used as a buffer memory.
OLI3 TIMI! Since i is restricted to the slower one, such READ 0YOIJ and WRITEOY
The discrepancy in OIJ was an obstacle to speeding up the system2.

発明の目的 本発明の目的は、上記の問題点に鑑み。Purpose of invention The object of the present invention is to solve the above problems.

WRITBOYOLBtl−RI!!AD 0YOLE
のn倍(n≧2)で制御するという着想に基づきWRI
TE 0YOLBに制約されていたシステムの0YOL
B TIMIi!をREAD 0YOLEで設定するこ
と、全可能にし、これによりシステムの高速化を図るこ
とが可能なRAM1提供することにある。
WRITBOYOLBtl-RI! ! AD 0YOLE
WRI is based on the idea of controlling by n times (n≧2)
0YOL of a system that was constrained to TE 0YOLB
BTIMIi! The object of the present invention is to provide a RAM 1 that can be set with READ 0YOLE, thereby increasing the speed of the system.

発明の構成 この目的は、本発明によれば、クロツク1B号および魯
込み指示信号が入力されるシフトレジスタと、該クロッ
ク信号が入力される複数のオアゲートと、アドレス信号
および書込みデータが入力される各々のレジスタと、読
出しデータが入力されるレジスタとを備え、該シフトレ
ジスタのシフト数に対応して該書込み指示信号が保持さ
れること全特徴とする半導体記憶装置を提供することに
より達成される。
Structure of the Invention According to the present invention, a shift register to which clock No. 1B and a write instruction signal are input, a plurality of OR gates to which the clock signal is input, and an address signal and write data are input. This is achieved by providing a semiconductor memory device comprising each register and a register into which read data is input, and in which the write instruction signal is held in accordance with the number of shifts of the shift register. .

実施例 第1図は1本発明の一実施例としてのRAMの基本的構
成を示すブロック線図である。第1図において1本発明
によるRAMは、シフトレジスタ1.オアゲート2,3
.および4.レジスタ5゜7および11、アドレス・デ
コーダ・ドライバ6゜ライト・アンプ8.メモリ・セル
・アレイ9.およびセンス・アンプ10により構成され
る。
Embodiment FIG. 1 is a block diagram showing the basic configuration of a RAM as an embodiment of the present invention. In FIG. 1, a RAM according to the present invention includes a shift register 1. or gate 2,3
.. and 4. Registers 5°7 and 11, address decoder driver 6° write amplifier 8. Memory cell array9. and a sense amplifier 10.

第2図は、第1図に示すRAMの信号タイミングを示す
タイミングチャートでちゃ、ダイナミック形RAMにお
いて必要とされるクロック信号(0LK)、アドレス信
号(AD)、書込みデータ(DIN)、 書込ミ指示信
号(WEx、2)オ、mヒ読出しデータ(DOUT)を
OLKを基準にして示したものである。尚、この場合、
 WRITg 0YOLIiiがRf!XAD 0YO
LEの2倍即ちn=2について示したものである。
FIG. 2 is a timing chart showing the signal timing of the RAM shown in FIG. The instruction signals (WEx, 2) O, M and H read data (DOUT) are shown with OLK as a reference. In this case,
WRITg 0YOLIii is Rf! XAD 0YO
This is shown for twice LE, that is, n=2.

このような構成および信号タイミングにおける動作を次
に説明する。
The operation of such a configuration and signal timing will be described next.

外部信号としてのOLKがシフトレジスタ1およびオア
ゲート3に入力されると、シフトレジスタ1の初段はW
BI信号f 10YOI、8分セットする。これによジ
オアゲート2の出力はhigh ()l)となシ同時に
オアゲート3の出力はレジスタ5に入力されアドレス信
号(AD)はアドレス・デコーダ・ドライバ6を経てメ
モリ・セル・プレイの所定の番地を指定する。一方、オ
アゲート2の出力はオアゲート4′ft経てレジスタ7
に入力され書込みデータCD、N)はライト・アンプ8
を経てメモリ・セル・アレイ9の指定された番地にデー
タを書込む。n1信号が1サイクルで終了しても。
When OLK as an external signal is input to shift register 1 and OR gate 3, the first stage of shift register 1 becomes W.
BI signal f 10YOI, set for 8 minutes. As a result, the output of the OR gate 2 becomes high ()l), and at the same time, the output of the OR gate 3 is input to the register 5, and the address signal (AD) is sent to the predetermined address of the memory cell play via the address decoder driver 6. Specify. On the other hand, the output of OR gate 2 passes through OR gate 4'ft to register 7.
The write data CD, N) input to the write amplifier 8
The data is written to the designated address of the memory cell array 9 through the process. Even if the n1 signal ends in one cycle.

シフトレジスタ1に次のOLKが入力されると次段がH
となるためにオアゲート2の出力はHf保持し点Pにお
ける内部信号としての書込み指示信号WE2はOLEの
20YOI、Ft分までセットされる。従って内部信号
としてのQ/Rは書込みを保持することができる。一方
1次のWBl信号が入力されたときに次のOLKによっ
て内部信号のQ/Rの入力が変化しては誤動作となって
しまうためWB2信号と01.にとはオアゲート4によ
ってオア回路を構成するようになっている。
When the next OLK is input to shift register 1, the next stage becomes H.
Therefore, the output of the OR gate 2 is held at Hf, and the write instruction signal WE2 as an internal signal at the point P is set up to 20YOI, Ft of OLE. Therefore, Q/R as an internal signal can hold the write. On the other hand, if the input of the internal signal Q/R changes due to the next OLK when the primary WBl signal is input, a malfunction will occur, so the WB2 signal and 01. The OR gate 4 constitutes an OR circuit.

上述の例ではシフトレジスタ1が2段の場合について説
明したが、−シフト数を変えることによってWRITI
it 0YOLFiを几BAI) 0YOI、F!のn
倍に設定することが可能である。
In the above example, we explained the case where shift register 1 has two stages, but by changing the number of shifts, WRITI
it 0YOLFi wo 几BAI) 0YOI, F! n of
It is possible to set it twice.

一方、読出しデータCDOUT )はメモリ・セル・ア
レイ9からセンス・アンプ10t−経てレジスタ11に
取込まれOLKの10YOIg ごとに出力される。
On the other hand, read data CDOUT) is taken into the register 11 from the memory cell array 9 via the sense amplifier 10t-, and is output every 10YOIg of OLK.

発明の効果 本発明によれば、メモリ領域に、1度書込んだ後、 R
eadのみという使用の仕方をするコントロール・メモ
リにおいては、0YCLHの高速化の面で著しい効果が
ある。
Effects of the Invention According to the present invention, after writing to the memory area once, R
A control memory that uses only ead has a significant effect in speeding up 0YCLH.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は1本発明による一実施例としてのRAMの基本
構成を示すブロック線図、および第2図は、第1図に示
すRAMの信号タイミングを示すタイミングチャートで
ある。 (符号の説明) 1・・・シフトレジスタ、2,3.4・・・オアゲート
。 5、7.11・・・レジスタ。 6・・・アドレス・デコーダ・ドライバ。 8・・・ライト・アンプ。 9・・・メモリ・セル・アレイ。 lO・・・センス・アンプ。
FIG. 1 is a block diagram showing the basic configuration of a RAM as an embodiment of the present invention, and FIG. 2 is a timing chart showing signal timing of the RAM shown in FIG. (Explanation of symbols) 1...Shift register, 2, 3.4...OR gate. 5, 7.11...Register. 6...Address decoder driver. 8...Light amplifier. 9...Memory cell array. lO...Sense amplifier.

Claims (1)

【特許請求の範囲】[Claims] 1、 クロック信号および書込み指示信号が入力される
シフトレジスタと、該クロック信号が入力される複数の
オアゲートと、アドレス信号および書込みデータが入力
される各々のレジスタと、読出しデータが入力されるレ
ジスタとを備え、該シフトレジスタのシフト数に対応し
て該書込み指示信号が保持されることを特徴とする半導
体記憶装置。
1. A shift register to which a clock signal and a write instruction signal are input, a plurality of OR gates to which the clock signal is input, each register to which an address signal and write data are input, and a register to which read data is input. What is claimed is: 1. A semiconductor memory device comprising: a semiconductor memory device, wherein the write instruction signal is held in correspondence with the number of shifts of the shift register.
JP59003557A 1984-01-13 1984-01-13 Semiconductor storage device Pending JPS60147996A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59003557A JPS60147996A (en) 1984-01-13 1984-01-13 Semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59003557A JPS60147996A (en) 1984-01-13 1984-01-13 Semiconductor storage device

Publications (1)

Publication Number Publication Date
JPS60147996A true JPS60147996A (en) 1985-08-05

Family

ID=11560723

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59003557A Pending JPS60147996A (en) 1984-01-13 1984-01-13 Semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS60147996A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6370996A (en) * 1986-09-11 1988-03-31 Fujitsu Ltd Semiconductor memory device
JPH02247893A (en) * 1989-03-20 1990-10-03 Nec Corp Semiconductor memory device
KR100757931B1 (en) 2006-06-29 2007-09-11 주식회사 하이닉스반도체 Apparatus for inputting data of semiconductor memory

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6370996A (en) * 1986-09-11 1988-03-31 Fujitsu Ltd Semiconductor memory device
JPH02247893A (en) * 1989-03-20 1990-10-03 Nec Corp Semiconductor memory device
KR100757931B1 (en) 2006-06-29 2007-09-11 주식회사 하이닉스반도체 Apparatus for inputting data of semiconductor memory

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