KR0154586B1 - Semiconductor memory device - Google Patents

Abstract

An object of the present invention is to provide a synchronous DRAM capable of speeding up an operation speed while preventing an increase in circuit area, and providing each signal latch circuit without having the same signal transfer time between signal latch circuits. .

A plurality of latch circuits 24 are interposed in the signal transfer path from the input buffer circuit 21 to the output buffer circuit 14, and the latch operation of each latch circuit 24 is controlled based on the same clock signal CLK. Then, the signal transfer between the latch circuits 24 is performed in one cycle of the clock signal CLK. The clock signal CLK is input to the latch circuit 24 through a control signal generation circuit 160 which makes the input timing of the clock signal CLK suitable for the signal transfer time from the previous latch circuit to the latch circuit.

Description

Semiconductor memory

1 is an explanatory view of the principle of the present invention.

2 is a block diagram showing a synchronous DRAM of one embodiment.

3 is a circuit diagram illustrating a sense buffer and I / O gates.

4 is a circuit diagram showing a specific configuration of a control signal generation circuit.

5 is an operation explanatory diagram of one embodiment.

6 is a block diagram showing a synchronous DRAM of a conventional example.

7 is a circuit diagram showing a sense buffer and an I / O gate of a conventional example.

8 is an operation explanatory diagram of a conventional example.

* Explanation of symbols for main parts of the drawings

14: output buffer 16: control signal generation circuit

21: input buffer 22: signal transmission circuit

23: data transfer circuit 24: latch circuit

CS: Motion control signal Dout: Read data

CLK: Clock Signal

The present invention relates to a semiconductor memory device for performing input / output operations of data synchronized with a clock signal.

Recently, the operating speed of a processor unit constituting a semiconductor integrated circuit is getting faster. Accordingly, there is a demand for an increase in the operating speed of the semiconductor memory device connected to such a processor unit. One type of semiconductor memory device which is advantageous in speeding up the operation speed is a synchronous DRAM that performs data input / output operations in synchronization with a clock signal. Increasingly, the speed of operation is increasingly required without increasing the circuit area of such a synchronous DRAM.

An example of a conventional synchronous DRAM will be described with reference to FIGS. 6 and 7.

The clock signal CLK input from the external circuit is controlled by the control signal latch circuit 2, the row address latch circuit 3, the open address latch circuit 4, the plurality of latch circuits 5, and the like through the clock buffer 1. It is input to the output latch circuit 6.

The control signals RAS and CAS and the write control signal WE input from the outside are input to the control signal latch circuit 2 via the command decoder 7. The control signal latch circuit 2 latches each control signal RAS, CAS, WE based on the clock signal CLK, and outputs the latches to the peripheral circuits of the memory cell array 8.

The address signal AD input from the outside is input to the hangdress latch circuit 3 and the open-dress latch circuit 4 via the address buffer 9.

The row address latch circuit 3 latches the row address signal based on the clock signal CLK and outputs it to the row decoder 10.

The open-dress latch circuit 4 latches the open-dress signal based on the clock signal CLK and outputs it to the column decoder 11.

The row decoder 10 outputs an output signal decoded a row address signal to the memory cell array 8, and selects a specific word line based on the row address signal among a plurality of word lines in the same memory cell array 8; do.

The column decoder 11 outputs an output signal obtained by decoding the open dress signal to the latch circuit 5. The latch circuit 5 latches an output signal of the column decoder 11 based on the clock signal CLK and outputs it to the sense buffer and the I / O gate 12.

The sense buffer and the I / O gate 12 open among a plurality of columns (bit line pairs) in the memory cell array 8 based on the output signal of the column decoder 11 to select a particular column based on the dress signal.

The memory cell array 8 is composed of a plurality of memory cells connected to word lines and bit lines. In the cell information reading operation, the cell information read from the memory cell selected based on the output signals of the row decoder 10 and the column decoder 11 is transferred through the sense buffer and the I / O gate 12. It is output to (13).

The data selector 13 outputs cell information output from the sense buffer and the I / O gate 12 to the output latch circuit 6. The output latch circuit 6 latches an output signal of the data selector 13 based on the clock signal CLK to output to the output buffer 14 and read cell information from the output buffer 14. It is output as read data Dout.

In the write operation, the externally input write data is input to the write amplifier (not shown) through the input buffer, and the write data is written in the same write amplifier for the memory cell selected by the address signal AD.

A detailed configuration of the latch circuit 5, the sense buffer and the I / O gate 12, and the memory cell array 8 will be described with reference to FIG.

A plurality of memory cells 15 are respectively connected to a plurality of pairs of bit lines BLO, BLO to BLn, BLn arranged in the memory cell array 8, and the word lines WL are respectively connected to each memory cell 15. ) Is connected. One of the word lines WL is selected based on an output signal of the row decoder 10.

The bit line ( ) Are connected to the data buses DB and DB through the transfer transistors Trn constituting the I / O gates, respectively. An output signal of the latch circuit 5 provided for each bit line pair is input to the gate of the transfer transistor Trn connected to each bit line pair. The output signal of the column decoder 11 and the clock signal CLK are input to each latch circuit 5.

The sense buffer 12a is connected to the data buses DB and DB, and the cell information read in the same data bus DB and DB is amplified in the same sense buffer 12a and output to the data selector 13. .

The operation of the synchronous DRAM will be described with reference to FIG. In the read operation, when the clock signal CLK is input, the row address latch circuit 3 sequentially latches the row address signal output from the address buffer 9 and outputs it to the row decoder 10.

When the first clock signal CLK1, which is one pulse of the clock signal CLK, is input, the open-dress latch circuit 4 latches the open-dress signal output from the address buffer 9 and outputs it to the column decoder 11. Let's do it. Then, the column decoder 11 decodes the open dress signal and outputs it to the latch circuit 5.

Then, based on the second clock signal CLK2, the latch circuit 5 latches the output signal of the column decoder 11 and outputs it to the sense buffer and the I / O gate 12. Then, the cell information read from the memory cell selected based on the output signals of the row decoder 10 and the column decoder 11 is output to the output latch circuit 6 through the sense buffer 12a and the data selector 13. .

Then, based on the third clock signal CLK3, the output latch circuit 6 latches the output signal of the data selector 13 and outputs it to the output buffer 14, and output data Dout from the same output buffer 14. ) Is output.

Therefore, in the synchronous DRAM as described above, the clock signal CLK is latched by each latch circuit every one cycle and output to the circuit of the next stage, and from the output buffer 14 every cycle of each clock signal CLK. Output data Dout is output. The read operation of one cycle is performed at the third pulse of the clock signal CLK.

By this operation, the signal is stably transmitted between the latch circuits, and the frequency of the clock signal CLK is raised to shorten the time interval for transmitting the signal, thereby improving the read speed of the cell information.

In the synchronous DRAM as described above, the period of the clock signal CLK needs to be set longer than the time until each latch circuit performs a latch operation and its output signal is input to the latch circuit of the next stage. Then, it is necessary to set the signal transfer time t1 between the latch circuits in the same manner.

In the synchronous DRAM, one latch circuit 5 interposed between the column decoder 11, the sense buffer, and the I / O gate 12 needs to be provided for each column, so that the same latch circuit 5 There is a problem that the chip area is increased by increasing the circuit area.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronous DRAM in which each signal latch circuit can be disposed without increasing the operation speed while preventing an increase in the circuit area and making the signal transfer time between the signal latch circuits the same. have.

1 is an explanatory view of the principle of the present invention. That is, the operation control signal CS is input to the input buffer circuit 21 from the outside, and the input control signal CS is output to the memory cell array 8 through the plurality of signal transfer circuits 22 to correspond to the corresponding memory. The memory cells in the cell array 8 are selected. Cell information is read from the selected memory cell, the cell information is input to the output buffer circuit 14 through the plurality of data transfer circuits 23, and the cell information is read data Dout through the output buffer circuit 14. As externally output. A plurality of latch circuits 24 are interposed in the signal transfer path from the input buffer circuit 21 to the output buffer circuit 14, and the latch operation of each latch circuit 24 is based on the same clock signal CLK. Is controlled, and signal transmission between the latch circuits 24 is performed in one cycle of the clock signal CLK. The latch circuit 24 has the clock signal CLK through a control signal generation circuit 16 which makes the input timing of the clock signal CLK suitable for the signal transfer time from the latch circuit of the previous stage to the latch circuit. Is entered.

As shown in FIGS. 2 and 3, the latch circuit includes an open-dress latch circuit 4 provided at the next stage of the address buffer 9 and a latch circuit provided at the next stage of the sense buffer 12a. 17) and an output latch circuit 6 provided in front of the output buffer circuit 14. The clock signal CLK is input to the open-dress latch circuit 4 and the output latch circuit 6, and the clock signal CLK is supplied to the latch circuit 17 through the control signal generation circuit 16. Is entered. In addition, the control signal generation circuit 16 is formed in each of a plurality of banks formed on a chip.

Even if the signal transfer time between the latch circuits 24 is different, after a predetermined input signal is inputted to each latch circuit 24, a clock signal is inputted to the same latch circuit 24 by the control signal generating circuit 16. Latch operation is performed.

2 and 3, the open-dress latch circuit 4 latches and outputs the open-dress signal based on the clock signal CLK, and then reads from the memory cell corresponding to the open-dress signal. The control signal generation circuit 16 delays the clock signal CLK and outputs it to the latch circuit 17 so as to correspond to the signal transfer time until the information is input to the latch circuit 17.

If the control signal generation circuit 16 is formed in each of a plurality of banks formed on the chip, the delay time of the same control signal generation circuit 16 can be set for each bank.

EXAMPLE

Hereinafter, one Example which actualized this invention is shown. In addition, the same code | symbol is attached | subjected to the said prior art example, and the description is abbreviate | omitted.

In the synchronous DRAM shown in FIG. 2, the latch circuit 5 provided between the column decoder 11, the sense buffer and the I / O gate 12 is omitted in the synchronous DRAM of the conventional example.

In addition, a latch circuit 17 is provided between the sense buffer and the I / O gate 12 and the data selector 13, and the same latch circuit 17 generates a control signal to which the clock signal CLK is input. It operates based on the output signal of the circuit 16. The rest of the configuration is the same as in the conventional example.

The connection configuration of the column decoder 11, the sense buffer, the I / O gate 12, and the latch circuit will be described with reference to FIG. A plurality of memory cells 15 are connected to a plurality of pairs of bit lines BLO, BLO to BLn, and BLn arranged in the memory cell array 8, and the word lines WL to each memory cell 1, respectively. ) Is connected. One of the word lines WL is selected based on the output signal of the row core 10.

The bit line ( Are each connected to the data bus through the transfer transistor Trn. ) Is connected. An output signal of the column decoder 11 is input to a gate of the transfer transistor Trn connected to each pair of bit lines.

The data bus ( The sense buffer 12a is connected to the same data bus ( ), The cell information is amplified in the same sense buffer 12a and output to the latch circuit 17. The data bus ( ), For example, eight pairs of bit line pairs are connected to the same data bus ( Is connected to one sense buffer 12a.

The latch circuit 17 latches the cell information output from the sense buffer 12a based on the output signal of the control signal generation circuit 16 and outputs the cell information to the data selector 13.

The detailed configuration of the control signal issuing circuit 16 will be described with reference to FIG. The clock signal CLK is input to, for example, a series circuit between a six stage inverter circuit 18 and a resistor R interposed between the inverter circuits 18.

The input terminal of the inverter circuit 18 from the third stage to the termination is connected to the low potential side power supply Vss via the capacitor C. The output signal CLKa of the inverter circuit 18 at the end is output to the latch circuit 17.

The control signal generation circuit 16 configured in this manner delays the input clock signal CLK with the delay time set by the inverter circuit 18, the resistor R and the capacitor C, and outputs it as the clock signal CLKa. The latch circuit 17 has a sum of the delay time and the time for one cycle of the clock signal CLK after the open dress signal is output from the open dress latch circuit 4 to the column decoder 11. It is set to be longer than the time until the output signal of the essence buffer 12a is input.

Next, the operation of the synchronous DRAM constructed as described above will be explained with reference to FIG.

When the clock signal CLK is input during the read operation time, the row address latch circuit 3 sequentially latches the row address signal output from the address buffer 9 and outputs it to the row decoder 10.

When the first clock signal CLK1, which is one pulse of the clock signal CLK, is input, the open-dress latch circuit 4 latches the open-dress signal output from the address buffer 9 and outputs it to the column decoder 11. Let's do it. The column decoder 11 decodes the open dress signal and outputs it to the sense buffer and the I / O gate 12.

Then, the cell information read from the memory cell selected based on the output signals of the row decoder 10 and the column decoder 11 is output from the sense buffer 12a to the latch circuit 17.

Then, based on the second clock signal CLK2, the control signal generation circuit 16 delays the second clock signal CLK2 and is output to the latch circuit 17 as the clock signal CLK2a.

The latch circuit 17 latches the output signal of the sense buffer 12a based on the delayed clock signal CLK2a and outputs it to the data selector 13. The data selector 13 outputs the cell information output from the sense buffer 12a to the output latch circuit 6.

Then, based on the third clock signal CLK3, the output latch circuit 6 latches the output signal of the data selector 13 and outputs it to the output buffer 14 to read data from the same output buffer circuit 14. (Dout) is output.

As described above, in the synchronous DRAM, the latch circuit 17 is driven by the clock signal CLKa in which the clock signal CLK is delayed by the control signal generation circuit 16.

After the open address signal is output from the open address latch circuit 4, the read cell information is input from the sense buffer 12a to the latch circuit 17, and then the clock signal CLKa is applied to the same latch circuit 17. Is output.

Therefore, the signal transfer time t2 until the read cell information is input from the sense buffer 12a to the latch circuit 17 after the open address signal is output from the open address latch circuit 4 is set to the clock signal CLK. It is not necessary to set it according to the period.

By such a configuration, by adjusting the delay time of the control signal generating circuit 16, the open latch latch circuit 4, the latch circuit 17 and the output latch circuit 6 can be driven based on the clock signal CLK. Can be.

Therefore, it is not necessary to set the cycle of the clock signal in accordance with the longest time of the signal transfer time between the latch circuits, and the frequency of the clock signal CLK can be increased. Therefore, the reading speed of cell information can be improved.

It is not necessary to provide a latch circuit in each column, but one latch circuit 17 may be provided at the next stage of each sense buffer 12a. If one sense buffer 12a is provided, for example, in eight columns, in the above-described conventional example, eight latch circuits 5 provided in the next stage of the column decoder 11 are sense buffers 12a in this embodiment. Since only one block is required to cut off the circuit, the circuit area of the latch circuit can be reduced.

In addition, a synchronous DRAM is provided with a plurality of banks on a chip, and can read or write independently of each bank.

In such a DRAM, by providing control signal generation circuits in each bank, it is possible to improve the operation speed while operating each bank independently.

The technical idea other than the claims grasped in the above embodiment will be described together with the effects below.

(1) An operation control signal and write data are externally input to an input buffer circuit, and the input operation control signal and write data are output to a memory cell array through a plurality of signal transfer circuits to select memory cells in the memory cell array. And write the write data to the selected memory cell, and control the latch operation of each latch circuit based on a common clock signal by interposing a plurality of latch circuits in a signal transmission path from the input buffer circuit to the memory cell. In the semiconductor memory device, the clock signal is inputted to the latch circuit through a control signal generation circuit which makes the input timing of the clock path suitable for the signal transfer time from the latch circuit in the previous stage to the latch circuit. Even if the signal transfer time between the latch circuits is different, after a predetermined input signal is inputted to each latch circuit, a clock signal is inputted to the same latch circuit by the control signal generating circuit to perform an input latch operation.

As described above, the present invention aims to speed up the operation speed while preventing the increase in the circuit area, and can also arrange the signal latch circuits without making the signal transfer time between the signal latch circuits the same. Can be provided.

Claims (3)

The operation control signal CS is input to the input buffer 21 from the outside, and the input operation control signal CS is output to the memory cell array 8 through a plurality of signal transfer circuits 22 to the memory cell array. (8) selecting a memory cell, reading cell information from the selected memory cell, and inputting the cell information into an output buffer circuit 14 through a plurality of data transfer circuits 23, and outputting the cell information to the output; Output to the outside through the buffer 14 as the read data (Dout), and each latch circuit (24) via a plurality of latch circuits 24 in the signal transmission path from the input buffer 21 to the output buffer (14). A semiconductor memory device which controls the latching operation of the circuit 24 based on the same clock signal CLK and transmits signals between the latch circuits 24 in one cycle of the clock signal CLK. Input timing of the clock signal CLK And the clock signal (CLK) is inputted through a control signal generation circuit (16) adapted for a signal transfer time from the latch circuit to the latch circuit. 2. The latch circuit according to claim 1, wherein the latch circuit comprises an open-dress latch circuit (4) provided at the next stage of the address buffer (9), a latch circuit (17) provided at the next stage of the sense buffer (12a), and the output buffer circuit. And an output latch circuit 6 provided at the front end of the circuit board 14, the clock signal CLK is input to the open-dress latch circuit 4 and the output latch circuit 6, and to the latch circuit 17. And the clock signal (CLK) is inputted through the control signal generation circuit (16). The semiconductor memory device according to claim 1, wherein said control signal generation circuit (16) is formed in each of a plurality of banks formed on a chip.