JPH01270260A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPH01270260A JPH01270260A JP63099673A JP9967388A JPH01270260A JP H01270260 A JPH01270260 A JP H01270260A JP 63099673 A JP63099673 A JP 63099673A JP 9967388 A JP9967388 A JP 9967388A JP H01270260 A JPH01270260 A JP H01270260A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline silicon
- silicon film
- doped polycrystalline
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 61
- 239000010410 layer Substances 0.000 claims abstract description 37
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 16
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000002356 single layer Substances 0.000 claims abstract description 6
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims 1
- 238000004904 shortening Methods 0.000 abstract description 2
- 239000002131 composite material Substances 0.000 description 17
- 238000000605 extraction Methods 0.000 description 8
- -1 boron ions Chemical class 0.000 description 7
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910008479 TiSi2 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
［概要］
複合形ＩＣなどの電極配線構造とその形成方法に関し、
品質を安定し、動作を高速化する複合形ＩＣを設けるこ
とを目的とし、
ｎ型にドープしたドープド多結晶シリコン膜と該ドープ
ド多結晶シリコン膜上に積層した金属膜あるいは金属シ
リサイド膜からなる２層構造の電極配線と、ｐ型にドー
プしたドープド多結晶シリコン膜のみからなる単層の電
極配線とを具備した半導体装置の構造を特徴とする。[Detailed Description of the Invention] [Summary] Regarding the electrode wiring structure and its formation method for composite ICs, the purpose of this invention is to provide composite ICs with stable quality and faster operation. An electrode wiring with a two-layer structure consisting of a polycrystalline silicon film and a metal film or metal silicide film laminated on the doped polycrystalline silicon film, and a single-layer electrode wiring consisting only of a p-type doped polycrystalline silicon film. The structure of a semiconductor device is characterized by:
且つ、その製造方法として、半導体基板上にノンドープ
ド多結晶シリコンを被着し、イオン注入して選択的にｎ
型にドープしたドープド多結晶シリコン膜の部分と、ｐ
型にドープしたドープド多結晶シリコン膜の部分とを形
成する工程、次いで、ｐ型にドープしたドープド多結晶
シリコン膜の部分上に酸化シリコン膜を被覆し、ｎ型に
ドープしたドープド多結晶シリコン膜の部分上に選択的
に金属シリサイド膜あるいは金属膜を被着する工程が含
まれることを特徴とする。In addition, as a manufacturing method, non-doped polycrystalline silicon is deposited on a semiconductor substrate, and ions are implanted to selectively add n.
The part of the doped polycrystalline silicon film doped with the mold and the p
Next, a silicon oxide film is coated on the p-type doped polycrystalline silicon film, and an n-type doped polycrystalline silicon film is formed. The method is characterized in that it includes a step of selectively depositing a metal silicide film or a metal film on the portion.
［産業上の利用分野］
本発明は半導体装置およびその製造方法のうち、特に複
合形ＩＣなどの電極配線構造とその形成方法に関する。[Industrial Field of Application] The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to an electrode wiring structure of a composite IC or the like and a method of forming the same.
最近、ＩＣ，ＬＳＩなど半導体装置は高性能化するため
にすべて高集積化、高密度化する方向に技術開発が進め
られており、例えば、バイポーラトランジスタ素子と０
ＭＯ３）ランジスタ素子とを組合わせたバイポーラシー
モス（Ｂｉｐｏｌａｒ−ＣＭＯ５）の複合形ＩＣが開発
されている。この複合形ＩＣはバイポーラ素子のもつ高
速性と０ＭＯ３素子のもつ低電力性の利点を活かした高
性能なＩＣであるが、タイプの異なるトランジスタ素子
の組合せであるから、性能・品質の安定について更に十
分な検討を必要としている。Recently, in order to improve the performance of semiconductor devices such as ICs and LSIs, technology development is progressing toward higher integration and higher density.For example, bipolar transistor elements and
A composite type IC of bipolar CMO5 (Bipolar-CMO5) in combination with MO3) transistor elements has been developed. This composite IC is a high-performance IC that takes advantage of the high speed of bipolar elements and the low power consumption of 0MO3 elements, but since it is a combination of different types of transistor elements, it is difficult to maintain stable performance and quality. Sufficient consideration is required.
［従来の技術］
第３図は従来のｎｐｎ型バイポーラ素子とＣＭＯＳとの
複合形ＩＣの断面図を示しており、Ｂはバイポーラ素子
領域９Ｍは０ＭＯ３のｎチャネル素子領域である。図中
の１はｐ型シリコン基板。[Prior Art] FIG. 3 shows a cross-sectional view of a conventional composite IC of an npn type bipolar element and a CMOS, in which B is a bipolar element region 9M, and a 0MO3 n-channel element region. 1 in the figure is a p-type silicon substrate.
２はフィールド絶縁膜、 １１はｎ＋型埋没層、１２は
エピタキシャル成長したｎ型コレクタ層、１３はｐ１型
ベース層、１４はｎ＋型エミッタ層、１５はｐ型ドープ
ド多結晶シリコン膜とタングステンシリサイド（ＷＳｉ
２）膜とを積層した２層構造のベース引出し電極、１６
はアルミニウム膜からなるベース電極、 １７はｎ型ド
ープド多結晶シリコン膜とアルミニウム膜とからなるエ
ミッタ電極であり、また、２１はｐ型ウェル領域、２２
はゲート絶縁膜、２３はｎ型ドープド多結晶シリコン膜
とＷ Ｓ ｉ ２膜とを積層した２層構造のゲート電極
、２４はｎ＋型ソース層またはドレイン層、２５はソー
ス電極またはドレイン電極であって、その他の無記号の
部分（梨地模様の部分）は酸化シリコン（ＳｉＯ２）膜
からなる絶縁膜である。2 is a field insulating film, 11 is an n + type buried layer, 12 is an epitaxially grown n type collector layer, 13 is a p1 type base layer, 14 is an n + type emitter layer, 15 is a p type doped polycrystalline silicon film and tungsten silicide (WSi).
2) A base extraction electrode with a two-layer structure laminated with a membrane, 16
17 is a base electrode made of an aluminum film, 17 is an emitter electrode made of an n-type doped polycrystalline silicon film and an aluminum film, 21 is a p-type well region, and 22 is a base electrode made of an aluminum film.
23 is a gate insulating film, 23 is a gate electrode with a two-layer structure in which an n-type doped polycrystalline silicon film and a W Si 2 film are laminated, 24 is an n + type source layer or drain layer, and 25 is a source or drain electrode. The other unmarked portions (the matte patterned portions) are insulating films made of silicon oxide (SiO2).
なお、０ＭＯ３のｎチャネル素子領域は図示していない
が、ゲート電極などの構成はｎチャネル素子と同じであ
り、且つ、バイポーラ素子領域Ｂにはコレクタ電極の部
分を図示していないが、そのコレクタ電極はエミッタ電
極とほぼ同じ構成である。Although the n-channel device region of 0MO3 is not shown, the structure of the gate electrode etc. is the same as that of the n-channel device, and the collector electrode part is not shown in the bipolar device region B. The electrode has almost the same configuration as the emitter electrode.
［発明が解決しようとする課題］
さて、上記の複合形ＩＣの構造において、その特徴の一
つとして、バイポーラ素子のｐ型ドープド多結晶シリコ
ン膜とＷ Ｓ ｉ ２膜とを積層した２層構造のベース
引出し電極１５と、ｎチャネル素子のｎ型ドープド多結
晶シリコン膜とＷ Ｓ ｉ ２膜とを積層した２層構造
のゲート電極２３（ｎチャネル素子のゲート電極も同じ
）とがあり、形成工程においてはこの画電極が同時に形
成される。なお、このように、ドープド多結晶シリコン
膜と高融点金属シリサイド膜を積層した２層構造の電極
配線を設ける理由はドープド多結晶シリコン膜のみの電
極配線では電気抵抗が高く、動作の高速化を阻害するか
らである。[Problems to be Solved by the Invention] Now, in the structure of the above-mentioned composite IC, one of its features is a two-layer structure in which a p-type doped polycrystalline silicon film of a bipolar element and a W Si 2 film are laminated. The gate electrode 23 has a two-layer structure in which the n-type doped polycrystalline silicon film of the n-channel device and the W Si 2 film are laminated (the same applies to the gate electrode of the n-channel device). In the process, this picture electrode is formed at the same time. The reason for providing the two-layered electrode wiring structure in which a doped polycrystalline silicon film and a high melting point metal silicide film are laminated is that electrode wiring made of only a doped polycrystalline silicon film has high electrical resistance, so it is important to increase the speed of operation. This is because it inhibits.
ところが、検討した結果によれば、理由が定かではない
が、上記の２層構造の電極配線のうち、ｐ型ドープド多
結晶シリコン膜とＷ Ｓ ｉ ２膜とを積層したベース
引出し電極１５はコンタクト性が悪く、且つ、形成工程
中の８００℃以上の熱処理が加わると、益々そのコンタ
クト性が劣化することが判明した。更に、それが進行す
ると、ｎｐｎ型バイポーラ素子が正常に動作しなくなる
という問題が起こる。However, according to the results of the study, although the reason is not clear, among the two-layered electrode wiring described above, the base lead electrode 15, which is a stack of a p-type doped polycrystalline silicon film and a W Si 2 film, is not a contact. It has been found that the contact properties are poor, and that when heat treatment at 800° C. or higher is applied during the formation process, the contact properties are further deteriorated. Furthermore, as this progresses, a problem arises in that the npn type bipolar element no longer operates properly.
一方、このようなベース引出し電極１５とゲート電極２
３をそのような２層構造とはせずに、ドープド多結晶シ
リコン膜からなる単層の電極配線のみにすれば、当然、
配線の電気抵抗が高くなって動作が遅延する。On the other hand, such a base extraction electrode 15 and gate electrode 2
If 3 is not made into such a two-layer structure but only has a single-layer electrode wiring made of a doped polycrystalline silicon film, of course,
The electrical resistance of the wiring increases, causing a delay in operation.
本発明はこのような問題点を解消させて、品質を安定し
、動作を高速化する複合形ＩＣを設けることを目的とし
た半導体装置とその製造方法を提案するものである。The present invention proposes a semiconductor device and a method for manufacturing the same, with the purpose of solving these problems and providing a composite IC with stable quality and high-speed operation.
［課題を解決するための手段］
その課題は、ｎ型にドープしたドープド多結晶シリコン
膜と該ドープド多結晶シリコン膜上に積層した金属膜あ
るいは金属シリサイド膜からなる２層構造の電極配線と
、ｐ型にドープしたドープド多結晶シリコン膜のみから
なる単層の電極配線とを具備した半導体装置によって解
決される。[Means for solving the problem] The problem is to provide an electrode wiring having a two-layer structure consisting of an n-type doped polycrystalline silicon film and a metal film or metal silicide film laminated on the doped polycrystalline silicon film; The problem is solved by a semiconductor device having a single-layer electrode wiring made of only a p-type doped polycrystalline silicon film.
また、その製造方法として、半導体基板上にノンドープ
ド多結晶シリコンを被着し、イオン注入して選択的にｎ
型にドープしたドープド多結晶シリコン膜の部分と、ｐ
型にドープしたドープド多結晶シリコン膜の部分とを形
成する工程、次いで、ｐ型にドープしたドープド多結晶
シリコン膜の部分上に酸化シリコン膜を被覆し、ｎ型に
ドープしたドープド多結晶シリコン膜の部分上に選択的
に金属シリサイド膜あるいは金属膜を被着する工程が含
まれることを特徴とするものである。In addition, as a manufacturing method, non-doped polycrystalline silicon is deposited on a semiconductor substrate, and ions are implanted to selectively
The part of the doped polycrystalline silicon film doped with the mold and the p
Next, a silicon oxide film is coated on the p-type doped polycrystalline silicon film, and an n-type doped polycrystalline silicon film is formed. The method is characterized in that it includes a step of selectively depositing a metal silicide film or a metal film on the portion.
［作用］
即ち、本発明は、金属膜、金属シリサイド膜とのコンタ
クト性の悪いｐ型ドープド多結晶シリコン膜を金属膜（
高融点金属膜）あるいは金属シリサイド膜を積層せずに
、ｐ型ドープド多結晶シリコン膜のみの電極配線とし、
他方、コンタクト性の良いｎ型ドープド多結晶シリコン
膜上には金属膜あるいは金属シリサイド膜を積層した２
層構造の電極配線を設けた構造にする。[Function] That is, the present invention converts a p-type doped polycrystalline silicon film, which has poor contact properties with a metal film and a metal silicide film, into a metal film (
The electrode wiring is made of only p-type doped polycrystalline silicon film without stacking high melting point metal film) or metal silicide film,
On the other hand, a metal film or metal silicide film is laminated on an n-type doped polycrystalline silicon film with good contact properties.
Create a structure with layered electrode wiring.
そうすれば、ｐ型ドープド多結晶シリコン膜のみの電極
配線は少し抵抗が高くなるが、配線距離を短くすること
によって配線抵抗の低下を図り、他方のｎ型ドープド多
結晶シリコン膜と金属膜あるいは金属シリサイド膜を積
層した２層構造の電極配線は低抵抗化されるから、配線
距離が多少長（なっても動作が遅延しない。かくして、
ＩＣ全体の高速動作に役立てる。In this case, the resistance of the electrode wiring made only of the p-type doped polycrystalline silicon film will be a little high, but by shortening the wiring distance, the wiring resistance will be lowered, and if the other n-type doped polycrystalline silicon film and the metal film or Since the electrode wiring has a two-layer structure in which metal silicide films are laminated, the resistance is reduced, so even if the wiring distance is somewhat long, the operation will not be delayed.
Useful for high-speed operation of the entire IC.
［実施例］ 以下、図面を参照して実施例によって詳細に説明する。[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.
第１図は本発明にかかる複合形ｒｃの断面図を示してお
り、バイポーラ素子領域Ｂのうち、３５はｐ型ドープド
多結晶シリコン膜のみからなる単層のベース引出し電極
、ＣＭＯ３のｎチャネル素子領域Ｍのうち、３３はｎ型
ドープド多結晶シリコン膜とＷ Ｓ ｉ ２膜とを積層
した２層構造のゲート電極で、その他の記号は第３図と
同一部位に同一記号が付けである。FIG. 1 shows a cross-sectional view of a composite type RC according to the present invention. Of the bipolar element region B, 35 is a single-layer base extraction electrode made of only a p-type doped polycrystalline silicon film, and a CMO3 n-channel element. In region M, reference numeral 33 is a gate electrode having a two-layer structure in which an n-type doped polycrystalline silicon film and a W Si 2 film are laminated, and the other symbols are the same parts as in FIG. 3 with the same symbols.
このような構成にすれば、ｎｐｎ型バイポーラ素子とＣ
ＭＯ３素子を組合せた複合形ＩＣにおいて、バイポーラ
素子のベース引出し電極３５はｐ型ドープド多結晶シリ
コン膜のみの電極配線となるが、このベース引出し電極
は距離が短く、且つ、アルミニウム膜からなるベース電
極とのコンタクトが良好であるから動作速度の劣化は小
さい。−方、ＣＭＯ３素子はゲート電極３３の配線距離
が長く、幅も狭くて、電気抵抗が高くなるために、ｎ型
ドープド多結晶シリコン膜の上にＷ Ｓ ｉ ２膜を積
層した２層構造にし、低抵抗化して動作を高速化し、か
くして、この複合形ＩＣを高速動作させる。With this configuration, the npn bipolar element and C
In a composite IC that combines MO3 elements, the base extraction electrode 35 of the bipolar element is an electrode wiring made only of a p-type doped polycrystalline silicon film, but this base extraction electrode has a short distance and has a base electrode made of an aluminum film. Since there is good contact with the controller, there is little deterioration in operating speed. - On the other hand, in the CMO3 element, the wiring distance of the gate electrode 33 is long, the width is narrow, and the electrical resistance is high. , the resistance is lowered and the operation speed is increased, thus allowing this composite IC to operate at high speed.
次に、第２図（ａ）〜（ｆｌは上記の本発明にかかる複
合形ＩＣの形成方法の工程順断面図を示しており、以下
にベース引出し電極とゲート電極との形成工程を主体に
した形成方法を説明する。Next, FIGS. 2(a) to (fl) show cross-sectional views in the order of steps of the method for forming a composite IC according to the present invention, and below, the steps for forming the base lead electrode and the gate electrode will be mainly explained. The method of forming this will be explained below.
第２図（ａ）参照；まず、従来法と同様に、ｐ型シリコ
ン基板１にｎ＋型埋没層１１を拡散し、ｎ型コレクタ層
１２をエピタキシャル成長して、次に、選択的にｐ型ウ
ェル領域２１を形成し、しかる後、Ｌｏｃｏｓ法によっ
てフィールド絶縁膜２を選択的に形成して、バイポーラ
素子領域Ｂ、ＣＭＯ３のｎチャネル素子領域Ｍなどを区
分けする。Refer to FIG. 2(a); First, as in the conventional method, an n+ type buried layer 11 is diffused into a p type silicon substrate 1, an n type collector layer 12 is epitaxially grown, and then a p type well layer is selectively grown. A region 21 is formed, and then a field insulating film 2 is selectively formed by the Locos method to divide the bipolar element region B, the n-channel element region M of the CMO 3, etc.
第２図（ｂｌ参照；次いで、熱酸化してゲート絶縁膜２
２（膜厚２００〜３００人程度）を生成し、バイポーラ
素子領域Ｂ上など不要部分のゲート絶縁膜を選択的に除
去した後、化学気相成長（ＣＶ Ｄ）法によって膜厚３
０００人程度０ノンドープド多結晶シリコン膜を被着し
、更に、バイポーラ素子領域Ｂのノンドープド多結晶シ
リコン膜には硼素イオン（Ｂ＋）を注入してｐ型ドープ
ド多結晶シリコン膜５０とし、ｎチャネル素子領域Ｍ（
図示していないｐチャネル素子領域も同様）のノンドー
プド多結晶シリコン膜には砒素イオン（Ａｓ” ）また
は燐イオン（Ｐ＋）を注入してｎ型ドープド多結晶シリ
コン膜３０にする。この選択ドーピング工程にはフォト
プローセスを利用して不要領域をマスクしてイオン注入
して形成する。FIG. 2 (see bl; then, thermal oxidation is performed to form the gate insulating film 2.
After selectively removing unnecessary parts of the gate insulating film such as on the bipolar element region B, a film with a thickness of 3 is formed using chemical vapor deposition (CVD).
A non-doped polycrystalline silicon film of approximately 0.0000 nm is deposited, and further boron ions (B+) are implanted into the non-doped polycrystalline silicon film in bipolar element region B to form a p-type doped polycrystalline silicon film 50, and an n-channel element is formed. Area M(
Arsenic ions (As'') or phosphorus ions (P+) are implanted into the non-doped polycrystalline silicon film in the p-channel device region (not shown) to form an n-type doped polycrystalline silicon film 30. This selective doping step In this step, unnecessary regions are masked using a photo process and ions are implanted.
第２図（Ｃ１参照；次いで、ドープド多結晶シリコン膜
５０．３０の表面を熱酸化してＳｉＯ□膜４０膜形０し
、ｎチャネル素子領域Ｍ上の５ｉ０２膜４０を除去した
後、公知の選択ＣＶＤ法によってｎチャネル素子領域Ｍ
上のみに膜厚１０００人程度０Ｗ Ｓ ｉ ２膜３１を
積層する。FIG. 2 (see C1; next, the surface of the doped polycrystalline silicon film 50.30 is thermally oxidized to form a SiO□ film 40, and after removing the 5i02 film 40 on the n-channel device region M, the well-known N-channel device region M is formed by selective CVD method.
A 0W Si 2 film 31 having a thickness of about 1000 layers is laminated only on the top.
第２図（ｄ）参照；次いで、その上面に、ＣＶＤ法によ
って５ｉ０２膜４１（膜厚１０００〜２０００人）を成
長した後、この５ｉ０２膜４１とＷ Ｓ ｉ ２膜３１
とｎ型ドープド多結晶シリコン膜３０．または５ｉ０２
膜４１ （Ｓｉ０２膜４０を含む）とｐ型ド−プド多結
晶シリコン膜５０をフォトプロセスによって垂直にパタ
ーンニングして、５ｉ０２膜４１を被覆したｐ型ドープ
ド多結晶シリコン膜のみからなるベース引出し電極３５
゜５ｉ０２膜４１を被覆したｎ型ドープド多結晶シリコ
ン膜とＷ Ｓ ｉ ２膜とを積層した２層構造のゲート
電極３３を同時に形成する。See FIG. 2(d); next, after growing a 5i02 film 41 (thickness 1000 to 2000) on its upper surface by the CVD method, this 5i02 film 41 and the W Si 2 film 31
and an n-type doped polycrystalline silicon film 30. or 5i02
The film 41 (including the Si02 film 40) and the p-type doped polycrystalline silicon film 50 are vertically patterned by a photo process to form a base lead consisting only of the p-type doped polycrystalline silicon film covering the 5i02 film 41. Electrode 35
A gate electrode 33 having a two-layer structure in which an n-type doped polycrystalline silicon film covering the 5i02 film 41 and a W Si 2 film are laminated is formed at the same time.
第２図（ｅ）参照；次いで、表面を少し熱酸化した後、
ｎチャネル素子領域Ｍに砒素イオンを注入して薄いソー
ス・ドレイン層（本例はＬＤＤ形ＭＯ８の例である）を
形成し、次に、バイポーラ素子領域Ｂに硼素イオンを注
入してｐ＋型内部ベースを形成する。次に、ＣＶＤ法に
よって５ｉ０２膜を成長し、それを垂直に異方性エツチ
ングして、ｎチャネル素子領域Ｍのゲート電極３３の側
面にＳｉＯ２膜４２を残存させ、ベース引出し電極３５
の側面に５ｉ０２膜４３を残存させる。更に、再び砒素
または燐イオンを注入してｎ＋型ソース・ドレイン層２
４を形成する。尚、これらのソース・ドレイン層２４や
内部ベースを含むベース層１３は以降の熱処理工程（次
工程のエミツタ層の拡散など）によって同時に画定され
る場合が多い。See Figure 2(e); Next, after slightly thermally oxidizing the surface,
Arsenic ions are implanted into the n-channel device region M to form a thin source/drain layer (this example is for an LDD type MO8), and then boron ions are implanted into the bipolar device region B to form a p+ type internal layer. form the base. Next, a 5i02 film is grown by the CVD method, and it is vertically anisotropically etched to leave the SiO2 film 42 on the side surfaces of the gate electrode 33 in the n-channel device region M, and the base extraction electrode 35
The 5i02 film 43 is left on the side surface of the substrate. Furthermore, arsenic or phosphorus ions are implanted again to form the n+ type source/drain layer 2.
form 4. Note that these source/drain layers 24 and the base layer 13 including the internal base are often defined at the same time by a subsequent heat treatment process (such as diffusion of the emitter layer in the next process).
第２図（ｆ）参照−次いで、内部ベース部分およびソー
ス・ドレイン電極部分を露出させた後、多結晶シリコン
膜（膜厚２０００人程度０をＣＶＤ法で被着し、その多
結晶シリコン膜に砒素イオンを注入して、ｎ型ドープド
多結晶シリコン膜７０．７１とし、更に、熱処理して内
部ベース部分にｎ＋型エミッタ層１４を拡散形成し、そ
の多結晶シリコン膜７０はエミッタ電極部分およびソー
ス・ドレイン電極部分にのみ残して、他を除去するパタ
ーンニングをおこなう。Refer to FIG. 2(f) - Next, after exposing the internal base portion and the source/drain electrode portion, a polycrystalline silicon film (with a film thickness of approximately 2000 mm) is deposited by the CVD method, and the polycrystalline silicon film is Arsenic ions are implanted to form an n-type doped polycrystalline silicon film 70, 71, and an n+-type emitter layer 14 is diffused into the internal base portion by heat treatment.・Perform patterning to leave only the drain electrode part and remove the rest.
しかる後、全面にＣＶＤ法によってＰＳＧ膜（または５
ｉ０２膜）を成長し、選択的に窓開けしてアルミニウム
膜からなるソース電極、ドレイン電極２５およびベース
電極１６．エミッタ電極１７（図示していないコレクタ
電極も含む）を形成して、第１図に示す断面図のように
仕上げる。After that, a PSG film (or 5
i02 film) is grown, and windows are selectively opened to form a source electrode, a drain electrode 25, and a base electrode 16. made of an aluminum film. An emitter electrode 17 (including a collector electrode not shown) is formed and finished as shown in the cross-sectional view of FIG.
以上が本発明にかかる複合形ＩＣの形成方法の概要で、
このように形成すれば高速に動作する複合形ＩＣが得ら
れる。なお、本例は金属シリサイド膜または金属膜の例
としてＷ Ｓ ｉ ２膜を用いたが、その他の膜、例え
ば、チタン（Ｔｉ）膜、タングステン（Ｗ）膜、モリブ
デン（Ｍｏ） 、チタンシリサイド（ＴｉＳｉ２ ）膜
、モリブデンシリサイド（ＭｏＳｉ２）膜などの２層構
造の電極配線を設けても良い。The above is an overview of the method for forming a composite IC according to the present invention.
If formed in this way, a composite IC that operates at high speed can be obtained. In this example, a W Si 2 film was used as an example of the metal silicide film or metal film, but other films such as titanium (Ti) film, tungsten (W) film, molybdenum (Mo), titanium silicide ( An electrode wiring having a two-layer structure such as a TiSi2) film or a molybdenum silicide (MoSi2) film may be provided.
［発明の効果］
以上の実施例の説明から明らかなように、本発明にかか
る半導体装置とその製造方法によれば、高性能な複合形
ＩＣなどの製造歩留の向上および品質の安定に大きく貢
献するものである。[Effects of the Invention] As is clear from the description of the embodiments above, the semiconductor device and the manufacturing method thereof according to the present invention can greatly improve the manufacturing yield and stabilize the quality of high-performance composite ICs. It is something that contributes.
第１図は本発明にかかる複合形ｒｃの断面図、第２図（
ａｌ〜（ｆｌは本発明にかかる形成方法の工程順断面図
、
第３図は従来の複合形ＩＣの断面図である。
図において、
Ｂはバイポーラ素子領域、
ＭはＣＭＯ３のｎチャネル素子領域、
１はｐ型シリコン基板、２はフィールド絶縁膜、１１は
ｎ＋型埋没層、 １２はｎ型コレクタ層、１３はｐ＋
型ベース層、 １４はｎ＋型エミッタ層、１５はベース
引出し電極、１６はベース電極、１７はエミッタ電極、
２１はｐ型ウェル領域、２２はゲート絶縁膜、
２３はゲート電極、２４はｎ＋型ソース・ドレイン層、
２５はソース電極またはドレイン電極、３５はｐ型ドー
プド多結晶シリコン膜からなるベース引出し電極、
３３はｎ型ドープド多結晶シリコン膜とＷ Ｓ ｉ ２
膜からなる２層構造のゲート電極、
４０、４１．４２．４３は５ｉ０２膜
を示している。
手Ｖ４ ＋： Ｄ−ａ−Ｊ４１−今Ｗ’ｙ ＩＣ−ｔ’
ｒｊｆｆＩ６第 １ 図
従五め荷合形ＩＣｎ１ケ面図
第 ３ ＦＡFig. 1 is a sectional view of a composite type rc according to the present invention, and Fig. 2 (
al~(fl is a step-by-step cross-sectional view of the formation method according to the present invention, and FIG. 3 is a cross-sectional view of a conventional composite IC. In the figure, B is a bipolar element region, M is a CMO3 n-channel element region, 1 is a p-type silicon substrate, 2 is a field insulating film, 11 is an n+ type buried layer, 12 is an n-type collector layer, 13 is a p+ type
14 is an n+ type emitter layer, 15 is a base extraction electrode, 16 is a base electrode, 17 is an emitter electrode,
21 is a p-type well region, 22 is a gate insulating film,
23 is a gate electrode, 24 is an n+ type source/drain layer, 25 is a source electrode or drain electrode, 35 is a base extraction electrode made of a p-type doped polycrystalline silicon film, 33 is an n-type doped polycrystalline silicon film and W Si 2
A gate electrode having a two-layer structure consisting of a film, 40, 41, 42, and 43 indicates a 5i02 film. Hand V4 +: D-a-J41-Now W'y IC-t'
rjffI6 No. 1 Figure Sub-Five Combined ICn1 side view No. 3 FA
Claims (2)
ドープド多結晶シリコン膜上に積層した金属膜あるいは
金属シリサイド膜からなる２層構造の電極配線と、ｐ型
にドープしたドープド多結晶シリコン膜のみからなる単
層の電極配線とを具備してなることを特徴とする半導体
装置。(1) A two-layer electrode wiring structure consisting of an n-type doped polycrystalline silicon film, a metal film or metal silicide film laminated on the doped polycrystalline silicon film, and a p-type doped polycrystalline silicon film. 1. A semiconductor device comprising a single-layer electrode wiring made of
着し、イオン注入して選択的にｎ型にドープしたドープ
ド多結晶シリコン膜の部分と、ｐ型にドープしたドープ
ド多結晶シリコン膜の部分とを形成する工程、 次いで、ｐ型にドープしたドープド多結晶シリコン膜の
部分上に酸化シリコン膜を被覆し、ｎ型にドープしたド
ープド多結晶シリコン膜の部分上に選択的に金属シリサ
イド膜あるいは金属膜を被着する工程が含まれてなるこ
とを特徴とする半導体装置の製造方法。(2) Non-doped polycrystalline silicon is deposited on a semiconductor substrate, and a part of the doped polycrystalline silicon film is selectively doped to n-type by ion implantation, and a part of the doped polycrystalline silicon film is doped to p-type. Next, a silicon oxide film is coated on the p-type doped polycrystalline silicon film, and a metal silicide film or metal is selectively coated on the n-type doped polycrystalline silicon film. A method for manufacturing a semiconductor device, comprising the step of depositing a film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63099673A JPH01270260A (en) | 1988-04-21 | 1988-04-21 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63099673A JPH01270260A (en) | 1988-04-21 | 1988-04-21 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01270260A true JPH01270260A (en) | 1989-10-27 |
Family
ID=14253550
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63099673A Pending JPH01270260A (en) | 1988-04-21 | 1988-04-21 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01270260A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6072221A (en) * | 1997-06-30 | 2000-06-06 | Kabushiki Kaisha Toshiba | Semiconductor device having self-aligned contact plug and metallized gate electrode |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6196750A (en) * | 1984-10-17 | 1986-05-15 | Oki Electric Ind Co Ltd | Wiring structure for semiconductor device |
| JPS62155553A (en) * | 1985-12-17 | 1987-07-10 | シ−メンス、アクチエンゲゼルシヤフト | Simultaneous manufacture of bipolar transistor and cmos transistor |
-
1988
- 1988-04-21 JP JP63099673A patent/JPH01270260A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6196750A (en) * | 1984-10-17 | 1986-05-15 | Oki Electric Ind Co Ltd | Wiring structure for semiconductor device |
| JPS62155553A (en) * | 1985-12-17 | 1987-07-10 | シ−メンス、アクチエンゲゼルシヤフト | Simultaneous manufacture of bipolar transistor and cmos transistor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6072221A (en) * | 1997-06-30 | 2000-06-06 | Kabushiki Kaisha Toshiba | Semiconductor device having self-aligned contact plug and metallized gate electrode |
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