JPH01266787A - Construction of conductor of hybrid integrated circuit and manufacture of the conductor - Google Patents
Construction of conductor of hybrid integrated circuit and manufacture of the conductorInfo
- Publication number
- JPH01266787A JPH01266787A JP9525388A JP9525388A JPH01266787A JP H01266787 A JPH01266787 A JP H01266787A JP 9525388 A JP9525388 A JP 9525388A JP 9525388 A JP9525388 A JP 9525388A JP H01266787 A JPH01266787 A JP H01266787A
- Authority
- JP
- Japan
- Prior art keywords
- metal foil
- foil layer
- conductor
- integrated circuit
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 title claims abstract description 93
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 238000010276 construction Methods 0.000 title 1
- 229910052751 metal Inorganic materials 0.000 claims abstract description 69
- 239000002184 metal Substances 0.000 claims abstract description 69
- 239000011888 foil Substances 0.000 claims abstract description 65
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 13
- 239000011889 copper foil Substances 0.000 claims description 9
- 238000007747 plating Methods 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 229920005989 resin Polymers 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 230000001070 adhesive effect Effects 0.000 claims 1
- 238000009413 insulation Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 238000005549 size reduction Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
Landscapes
- Parts Printed On Printed Circuit Boards (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【発明の詳細な説明】
（イ）産業上の利用分野
本発明は同一基板上に大電流及び小電流用の導体が形成
された混成集積回路の導体構造及びその導体製造方法に
関する。DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a conductor structure of a hybrid integrated circuit in which conductors for large current and small current are formed on the same substrate, and a method for manufacturing the conductor.
（ロ）従来の技術
通常混成集積回路は基板上に所定の導体が形成され、そ
の導体上に複数の半導体素子が固着されてなっている。(B) Prior Art A hybrid integrated circuit typically has a predetermined conductor formed on a substrate, and a plurality of semiconductor elements fixed onto the conductor.
また金属基板からなる混成集積回路において、同一基板
上に銅箔を用いて電流容量の大きい導体パターンと電流
容量の小きい導体パターンとを形成する場合は通常第５
図に示す如く、導体（１１）の幅の太で電流容量の大小
が区別されている（このときの銅箔の膜厚は一定である
）。In addition, in a hybrid integrated circuit made of a metal substrate, when a conductor pattern with a large current capacity and a conductor pattern with a small current capacity are formed using copper foil on the same substrate, the fifth
As shown in the figure, the current capacity is distinguished by the width of the conductor (11) (the thickness of the copper foil at this time is constant).
（ハ）発明が解決しようとする課題
同一基板上に電流容量の大きい導体と電流容量の小さい
導体ブロックが必要の場合、電流容量大の導体を形成す
る時は、第５図に示す如く、銅箔幅を広くする方法しか
なく、基板の実装面積が小さくなると共に混成集積回路
の小型化という点で問題がある。(c) Problems to be Solved by the Invention When a conductor with a large current capacity and a conductor block with a small current capacity are required on the same substrate, when forming the conductor with a large current capacity, it is necessary to use copper as shown in Figure 5. The only method available is to widen the foil width, which poses problems in terms of reducing the mounting area of the board and miniaturizing the hybrid integrated circuit.
また、電流容量の大きい導体を銅箔厚さを犬にしてパタ
ーン面積を小さくしようとすると銅箔厚さが一定である
ので、電流容量の小きい導体ブロックでファインパター
ンを形成することが困難となり、やはり基板の実装面積
が小さくなるという点で問題がある。In addition, if you try to reduce the pattern area of a conductor with a large current capacity by increasing the thickness of the copper foil, since the copper foil thickness remains constant, it will be difficult to form a fine pattern with a conductor block with a small current capacity. However, there is still a problem in that the mounting area of the board becomes smaller.
（ニ）課題を解決するための手段
本発明は上述した問題点に鑑みて為されたものであり、
混成集積回路基板と、前記基板上に接着された第１の金
属箔層と、前記第１の金属箔層上の所望領域に固着され
た第２の金属箔層とを有し、前記第１の金属箔層より形
成された導体を小電流用、第２の金属箔層より形成され
た導体を大電流用に用いて解決する。(d) Means for solving the problems The present invention has been made in view of the above-mentioned problems,
a hybrid integrated circuit board; a first metal foil layer adhered on the substrate; and a second metal foil layer adhered to a desired area on the first metal foil layer; The problem is solved by using a conductor formed from the second metal foil layer for small currents and a conductor formed from the second metal foil layer for large currents.
（ホ）作用
この様に本発明に依れば、大電流、小電流用に導体の膜
厚を夫々異ならせ、即ち、大電流用の膜厚を厚く、小１
流用の膜厚を薄く形成することにより、大小電流用の導
体幅の差がなくなると共に大小電流用の導体幅の差を著
しく小さくし高密度導体パターンを形成することができ
、従来と同様に大電流用の導体に大電流を流すことがで
きる。(e) Effect As described above, according to the present invention, the film thickness of the conductor is made different for large currents and small currents, that is, the film thickness is thick for large currents, and the film thickness for small currents is thick.
By forming the diversion film thinner, the difference in conductor width for large and small currents is eliminated, and the difference in conductor width for large and small currents is significantly reduced, making it possible to form a high-density conductor pattern. A large current can be passed through a current conductor.
（へ）実施例
以下に図面に示した実施例に基づいて本発明の詳細な説
明する。(F) Examples The present invention will be described in detail below based on the examples shown in the drawings.
第１図りは本発明の混成集積回路の導体構造を示す要部
拡大斜視図であり、（１）は基板、（６）（５）は大小
電流用の導体、（２）は基板（１）と第１の金属箔層り
３）とを接着する絶縁樹脂層である。The first diagram is an enlarged perspective view of the main parts showing the conductor structure of the hybrid integrated circuit of the present invention, in which (1) is the substrate, (6) and (5) are conductors for large and small currents, and (2) is the substrate (1). and the first metal foil layer 3).
次に本発明の混成集積回路の導体の製造方法を説明する
。Next, a method for manufacturing a conductor for a hybrid integrated circuit according to the present invention will be explained.
先ず第１図Ａに示す如く、混成集積回路基板り１）を準
備する。混成集積回路基板（１）としては金属、セラミ
ックス、ガラエボ等の基板があるが銅箔の発熱を容易に
放熱することができる金属のアルミニウム基板を用いる
ものとする。そのアルミニウム基板（１）の表面は周知
技術である陽極酸化によって絶縁処理をする。その混成
集積回路基板り１）の−主面に所望厚の第１の金属箔層
（３）を貼着する。第１の金属箔層（３）は絶縁樹脂層
（２）との接着性を向上させるために銅箔を用いエポキ
シ樹脂等の絶縁樹脂層（２）を介して基板（１）に貼着
される。このとき第１の金属箔層（３）の膜厚は小電流
用の導体の膜厚となる様に設定しておく。First, as shown in FIG. 1A, a hybrid integrated circuit board 1) is prepared. The hybrid integrated circuit board (1) may be made of metal, ceramic, glass, etc., but a metal aluminum board is used because it can easily dissipate the heat generated by the copper foil. The surface of the aluminum substrate (1) is insulated by anodic oxidation, which is a well-known technique. A first metal foil layer (3) of a desired thickness is adhered to the main surface of the hybrid integrated circuit board (1). The first metal foil layer (3) is attached to the substrate (1) via an insulating resin layer (2) such as epoxy resin using copper foil to improve adhesion with the insulating resin layer (2). Ru. At this time, the thickness of the first metal foil layer (3) is set to be the same as that of a conductor for small current.
次に第１図Ｂに示す如く、第１の金属箔層（３）上の所
定領域に第２の金属箔層を形成する。第２の金属箔層（
４）は大電流用の導体が形成きれる領域である。即ち、
大電流用導体が形成される以外の領域にメッキ用のレジ
ストを塗布しく斜線部分）、第１の金属箔層（３）の露
出部分に銅あるいはニッケル等のメッキを行い大電流用
導体の膜厚（１）となるまで第１の金属箔層（３）上に
膜厚分だけ積層させる。ここでメッキは電解あるいは無
電解メッキのどちらでもよい。第１の金属箔層（３）上
の所定領域に第２の金属箔層（４）を形成した後、第１
の金属箔層（３）上に残されたメッキ用のレジストを除
去する。Next, as shown in FIG. 1B, a second metal foil layer is formed in a predetermined area on the first metal foil layer (3). Second metal foil layer (
4) is an area where a large current conductor can be formed. That is,
Apply a plating resist to areas other than where the large current conductor will be formed (shaded areas), and plate the exposed parts of the first metal foil layer (3) with copper or nickel to form the large current conductor film. It is laminated by the film thickness on the first metal foil layer (3) until the thickness becomes (1). Here, the plating may be either electrolytic or electroless plating. After forming the second metal foil layer (4) in a predetermined area on the first metal foil layer (3),
The plating resist left on the metal foil layer (3) is removed.
次に第１図Ｃに示す如く、第１及び第２の金属箔層（３
）（４）上にエツチング用の感光性レジストをスプレ一
方式、デイツプ及びロールコータ方式等を用いて塗布す
る。ホトレジストを塗布した後、小電流用導体が形成さ
れる第１の金属箔層（３）上に小電流用導体パターン（
５°）及び大電流用導体が形成される第２の金属箔層（
４）上に大電流用導体パターン（６′）となる様にホト
レジストを露光・現像しく斜線部分）、露出した第１及
び第２の金属箔層（３）（４）をエツチング除去して第
１図りに示す如く、小電流用の導体（５）と大電流用の
導体（６）を形成する。Next, as shown in FIG. 1C, the first and second metal foil layers (3
) (4) A photosensitive resist for etching is applied on top using a spray method, dip and roll coater method, etc. After applying the photoresist, a small current conductor pattern (
5°) and a second metal foil layer on which the high current conductor is formed (
4) Expose and develop the photoresist to form a large current conductor pattern (6') on top (shaded area), remove the exposed first and second metal foil layers (3) and (4), and remove the exposed first and second metal foil layers (3) and (4). As shown in Figure 1, a small current conductor (5) and a large current conductor (6) are formed.
他の実施例として第２図Ａに示す如く、第１の金属箔層
（３）をあらかじめ小電流用導体（５）と大電流用のブ
ロック（７）とにエツチング形成した後、大電流ブロッ
ク（７）以外の領域にレジストを塗布した後（斜線部分
）、第２図Ｂに示す如く、大電流用ブロック（７）上に
上述したメッキによって所定の膜厚分だけメッキした後
、ブロック（７）上に大電流用の導体パターンクロ′）
を形成して（点線斜線部分）、ブロック（７）をエツチ
ングすれば第１図りに示す様な大小電流用の導体（５）
（６）を形成することができる。As another example, as shown in FIG. 2A, after forming the first metal foil layer (3) on the small current conductor (5) and the large current block (7) in advance, the large current block is etched. After applying resist to the area other than (7) (shaded area), as shown in FIG. 7) There is a conductor pattern black on top for large current.
(dotted hatched area) and etching the block (7) will result in a conductor (5) for large and small currents as shown in the first diagram.
(6) can be formed.
上述した製造方法は夫々の導体（６）（７）の膜厚差が
あまりない場合において有効であるが、大小１流用導々
の導体（６）（７）の膜厚差が著しく異なる場合にはあ
まり適応しない。The manufacturing method described above is effective when there is not much difference in film thickness between the conductors (6) and (7), but when the difference in film thickness between the conductors (6) and (7) of the large and small diversion conductors is significantly different. is not very adaptable.
以下に膜厚差が著しく異なる場合の製造方法を説明する
。基板上に銅箔を貼着するまでは上述と同様であり説明
は省略する。The manufacturing method when the difference in film thickness is significantly different will be explained below. The process until the copper foil is pasted on the board is the same as described above, and the explanation will be omitted.
第３図Ａに示す如く、基板（１）上には絶縁樹脂層（２
）を介して所望の膜厚の第１の金属箔層（３）を貼着す
る。この第１の金属箔層（３）は上述の如く、銅箔であ
り、膜厚は小電流用導体の膜厚に設定しておく、感光性
レジストを第１の金属箔層（３）全面に塗布し、大電流
用導体パタニン（６′）形状に露光・現像して大電流用
導体領域となる以外の領域にレジストを残す（斜線部分
）。As shown in Figure 3A, there is an insulating resin layer (2) on the substrate (1).
) A first metal foil layer (3) of a desired thickness is attached through the film. As mentioned above, this first metal foil layer (3) is a copper foil, and the film thickness is set to the thickness of a small current conductor. The resist is coated on the substrate, exposed and developed in the shape of a large current conductor pattern (6'), and the resist is left in areas other than those that will become the large current conductor areas (shaded areas).
次に第３図Ｂに示す如く、大電流用導体領域に銅あるい
はニッケルの電解（非電解）メッキを施し、大電流用の
導体膜厚になるまで積層し、導体パターン形状の第２の
金属箔層（４）を形成する。Next, as shown in Figure 3B, electrolytic (non-electrolytic) plating of copper or nickel is applied to the conductor area for high current, and the layers are laminated until the conductor film thickness for high current is reached, and a second metal in the shape of a conductor pattern is applied. Form a foil layer (4).
第２の金属箔Ｍ（４）形成後、レジストを剥離する。次
に第３図Ｃに示す如く、再度第１及び第２の金属箔層（
３）（４）上にエツチング用のホトレジストを塗布し、
第１の金属箔層（３）上に小電流用導体のパターン（５
′）及び第２の金属箔層（４）のパターン形状に露光・
現像し、小電流導体と大電流導体となる領域上のみにレ
ジストを残したのも（斜線部分）、第１の金属箔層（３
）をエツチング除去すれば第３図りに示す如く、電流容
量の差が著しく異なる場合においても大小電流用の導体
（６）（５）を形成することができる。After forming the second metal foil M(4), the resist is peeled off. Next, as shown in FIG. 3C, the first and second metal foil layers (
3) Apply photoresist for etching on (4),
A pattern of small current conductors (5) on the first metal foil layer (3)
') and the pattern shape of the second metal foil layer (4).
The resist was developed and left only on the areas that will become the small current conductor and the large current conductor (shaded area).
) can be removed by etching, as shown in the third diagram, it is possible to form conductors (6) and (5) for large and small currents even when the difference in current capacity is significantly different.
他の実施例として第４図Ａ及び第４図Ｂに示す如く、基
板（１）上に第１の金属箔層（３）を貼着し、大小１流
用導体パターン（６’ ＞（５’ ）を形成して第１の
金属箔層（３）で夫々の導体（５）（６）をあらかじめ
形成しておき、第４図Ｃに示す如く、大電流用導体（６
）以外の領域にレジストを塗布して（斜線部分）、メッ
キすれば導体（６）上に金属が積層すれ、第３図りに示
す如く、膜厚差の異なる大小電流用の導体（６）（５）
を形成することができる。As another example, as shown in FIG. 4A and FIG. 4B, a first metal foil layer (3) is pasted on a substrate (1), and a conductor pattern of one size and one size (6'>(5' ), and conductors (5) and (6) are formed in advance with the first metal foil layer (3), and as shown in FIG.
) If a resist is applied to the area other than (shaded area) and plated, metal will be laminated on the conductor (6), and as shown in the third diagram, the conductor (6) for large and small currents with different film thicknesses will be formed. 5)
can be formed.
断る本発明に依れば、同一基板上に選択して電流容量の
異なる導体を形成することができるので、基板の大きさ
を変更せずにより大きさの異なった電流容量の導体を形
成することができる。According to the present invention, conductors with different current capacities can be selectively formed on the same substrate, so conductors with different current capacities can be formed without changing the size of the substrate. I can do it.
（ト）発明の効果
以上に詳述した如く、本発明に依れば、同一基板上に膜
厚の異なる導体即ち、電流容量の異なる導体を形成する
ことができるため、従来と同一基板で電流容量の大きい
導体形成することができ、混成集積回路の小型化を容易
にすることができる。(G) Effects of the Invention As detailed above, according to the present invention, conductors with different film thicknesses, that is, conductors with different current capacities can be formed on the same substrate. A conductor with a large capacity can be formed, and a hybrid integrated circuit can be easily miniaturized.
また本発明では従来の製造工程をそのまま用いて製造す
ることができる利点を有する。Furthermore, the present invention has the advantage that it can be manufactured using conventional manufacturing processes as they are.
第１図Ａ乃至第１図りは本発明の混成集積回路の導体製
造方法を示す斜視図、第２図Ａ及び第２図Ｂ、第３図Ａ
乃至第３図Ｄ、第４図Ａ乃至第４図Ｃは他の製造方法を
示す斜視図、第５図は従来例を示す斜視図である。
（１）・・・基板、 り２）・・・絶縁樹脂層、 （３
）・・・第１の金属箔層、 （４）・・・第２の金属箔
層、 （５）（６ン・・・導体。1A to 1D are perspective views showing the method for manufacturing a conductor of a hybrid integrated circuit according to the present invention; FIGS. 2A and 2B; and FIG. 3A.
3D to 3D and FIGS. 4A to 4C are perspective views showing other manufacturing methods, and FIG. 5 is a perspective view showing a conventional example. (1)...Substrate, 2)...Insulating resin layer, (3
)...first metal foil layer, (4)...second metal foil layer, (5)(6n...conductor).
Claims (9)
１の金属箔層と、前記第１の金属箔層上の所望領域に固
着された第２の金属箔層とを有し、前記第１の金属箔層
より形成された導体を小電流用、第２の金属箔層より形
成された導体を大電流用に用いたことを特徴とする混成
集積回路の導体構造。(1) comprising a hybrid integrated circuit board, a first metal foil layer adhered on the substrate, and a second metal foil layer adhered to a desired area on the first metal foil layer; A conductor structure for a hybrid integrated circuit, characterized in that the conductor formed from the first metal foil layer is used for small currents, and the conductor formed from the second metal foil layer is used for large currents.
ことを特徴とする請求項１記載の混成集積回路の導体構
造。(2) The conductor structure of a hybrid integrated circuit according to claim 1, wherein the second metal foil layer is laminated by plating.
の所望領域で区画させることを特徴とする請求項１記載
の混成集積回路の導体構造。(3) The conductor structure of a hybrid integrated circuit according to claim 1, wherein each of the conductors for large current and for small current is partitioned in a desired area of the substrate.
を接着し、前記第１の金属箔層上の所定領域に所望の膜
厚を有した第２の金属箔層を積層させた後、前記第１及
び第２の金属箔層を蝕刻して膜厚の異なる導体を形成す
ることを特徴とする混成集積回路の導体製造方法。(4) A first metal foil layer with a desired thickness is adhered onto the hybrid integrated circuit board, and a second metal foil layer with a desired thickness is laminated on a predetermined area on the first metal foil layer. A method for manufacturing a conductor for a hybrid integrated circuit, characterized in that the first and second metal foil layers are etched to form conductors having different thicknesses.
を接着し、前記第１の金属箔層上に導体パターン形状の
第２の金属箔層を積層し、前記第１の金属箔層のみを蝕
刻して膜厚の異なる導体を形成することを特徴とする混
成集積回路の導体製造方法。(5) A first metal foil layer having a desired thickness is adhered onto the hybrid integrated circuit board, a second metal foil layer having a conductor pattern shape is laminated on the first metal foil layer, and a second metal foil layer having a conductor pattern shape is laminated on the first metal foil layer. A method for manufacturing a conductor for a hybrid integrated circuit, characterized in that conductors having different thicknesses are formed by etching only a metal foil layer.
膜厚を異ならせて形成したことを特徴とする請求項５記
載の混成集積回路の導体製造方法。(6) The method of manufacturing a conductor for a hybrid integrated circuit according to claim 5, wherein the second metal foil layer having the conductor pattern shape is formed with different film thicknesses.
接着性を有する絶縁樹脂層を介して貼着することを特徴
とする請求項１，４及び５記載の混成集積回路の導体構
造及びその導体製造方法。(7) The hybrid integrated circuit according to any one of claims 1, 4, and 5, wherein a copper foil is used for the first metal foil layer, and the first metal foil layer is bonded to the substrate via an insulating resin layer having adhesive properties. conductor structure and method for manufacturing the conductor.
メッキによって行うことを特徴とする請求項４及び５記
載の混成集積回路の導体製造方法。(8) The method of manufacturing a conductor for a hybrid integrated circuit according to claim 4 or 5, wherein the second metal foil layer is formed by copper plating or nickel plating.
を特徴とする請求項１，４及び５記載の混成集積回路の
導体構造及びその導体製造方法。(9) The conductor structure of a hybrid integrated circuit and the method of manufacturing the conductor according to claims 1, 4, and 5, wherein the substrate is a metal substrate treated with insulation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63095253A JP2664409B2 (en) | 1988-04-18 | 1988-04-18 | Manufacturing method of hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63095253A JP2664409B2 (en) | 1988-04-18 | 1988-04-18 | Manufacturing method of hybrid integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01266787A true JPH01266787A (en) | 1989-10-24 |
| JP2664409B2 JP2664409B2 (en) | 1997-10-15 |
Family
ID=14132594
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63095253A Expired - Lifetime JP2664409B2 (en) | 1988-04-18 | 1988-04-18 | Manufacturing method of hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2664409B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013229603A (en) * | 2012-04-25 | 2013-11-07 | Semikron Elektronik Gmbh & Co Kg | Substrate, and method for manufacturing substrate for at least one power semiconductor component |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55159572U (en) * | 1979-05-04 | 1980-11-15 | ||
| JPS58110090A (en) * | 1981-12-24 | 1983-06-30 | 富士通株式会社 | Conductor pattern for plan circuit |
| JPS58138363U (en) * | 1982-03-11 | 1983-09-17 | オリジン電気株式会社 | Printed wiring board for power |
| JPS60182188A (en) * | 1984-02-29 | 1985-09-17 | 矢崎総業株式会社 | Circuit board and method of producing same |
| JPS60257191A (en) * | 1984-06-02 | 1985-12-18 | 株式会社日立製作所 | Printed circuit board |
| JPS622591A (en) * | 1985-06-28 | 1987-01-08 | 電気化学工業株式会社 | Manufacture of metal base hybrid integrated circuit board |
| JPH01253293A (en) * | 1988-03-31 | 1989-10-09 | Yamaha Motor Co Ltd | Printed wiring substrate and manufacture thereof |
-
1988
- 1988-04-18 JP JP63095253A patent/JP2664409B2/en not_active Expired - Lifetime
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55159572U (en) * | 1979-05-04 | 1980-11-15 | ||
| JPS58110090A (en) * | 1981-12-24 | 1983-06-30 | 富士通株式会社 | Conductor pattern for plan circuit |
| JPS58138363U (en) * | 1982-03-11 | 1983-09-17 | オリジン電気株式会社 | Printed wiring board for power |
| JPS60182188A (en) * | 1984-02-29 | 1985-09-17 | 矢崎総業株式会社 | Circuit board and method of producing same |
| JPS60257191A (en) * | 1984-06-02 | 1985-12-18 | 株式会社日立製作所 | Printed circuit board |
| JPS622591A (en) * | 1985-06-28 | 1987-01-08 | 電気化学工業株式会社 | Manufacture of metal base hybrid integrated circuit board |
| JPH01253293A (en) * | 1988-03-31 | 1989-10-09 | Yamaha Motor Co Ltd | Printed wiring substrate and manufacture thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2013229603A (en) * | 2012-04-25 | 2013-11-07 | Semikron Elektronik Gmbh & Co Kg | Substrate, and method for manufacturing substrate for at least one power semiconductor component |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2664409B2 (en) | 1997-10-15 |
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| Date | Code | Title | Description |
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| EXPY | Cancellation because of completion of term |