JPH03119789A - Manufacture of wiring board - Google Patents
Manufacture of wiring boardInfo
- Publication number
- JPH03119789A JPH03119789A JP25672289A JP25672289A JPH03119789A JP H03119789 A JPH03119789 A JP H03119789A JP 25672289 A JP25672289 A JP 25672289A JP 25672289 A JP25672289 A JP 25672289A JP H03119789 A JPH03119789 A JP H03119789A
- Authority
- JP
- Japan
- Prior art keywords
- conductor circuit
- base material
- thickness
- insulating
- conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 239000004020 conductor Substances 0.000 claims abstract description 45
- 239000000463 material Substances 0.000 claims abstract description 23
- 238000007747 plating Methods 0.000 claims abstract description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052802 copper Inorganic materials 0.000 abstract description 4
- 239000010949 copper Substances 0.000 abstract description 4
- 239000011810 insulating material Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 239000009719 polyimide resin Substances 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- KZHJGOXRZJKJNY-UHFFFAOYSA-N dioxosilane;oxo(oxoalumanyloxy)alumane Chemical compound O=[Si]=O.O=[Si]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O.O=[Al]O[Al]=O KZHJGOXRZJKJNY-UHFFFAOYSA-N 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 229910052863 mullite Inorganic materials 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Landscapes
- Manufacturing Of Printed Wiring (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】 ［産業上の利用分野］ この発明は多層化に適した配線板の製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method of manufacturing a wiring board suitable for multilayering.
［従来の技術］
従来、ビルドアップ方により多層配線板を製造する場合
には、絶縁性基材の表面全体に形成された導体層をエツ
チングすることによって導体回路を形成した後、その導
体回路の形成部分以外の部分にポリイミド樹脂等の絶縁
材を充填することにより、基材の表面全体を平坦化し、
次いで前記平坦化された表面全体に更に絶縁層を形成し
た後、導体層を形成する工程を繰り返すことにより、多
層配線板を製造していた。[Prior Art] Conventionally, when manufacturing a multilayer wiring board by the build-up method, a conductor circuit is formed by etching a conductor layer formed on the entire surface of an insulating base material, and then the conductor circuit is By filling parts other than the forming part with an insulating material such as polyimide resin, the entire surface of the base material is flattened,
Next, after further forming an insulating layer over the entire flattened surface, a multilayer wiring board was manufactured by repeating the process of forming a conductor layer.
［発明が解決しようとする課題］
ところが、上述した従来の製造方法では、絶縁材を導体
回路の狭隘な部分にも隈無く充填することは技術的に困
難であって導体回路と絶縁層との間に隙間が生じ易く、
又、絶縁材の収縮を制御して段差の発生を抑制すること
が難しかった。[Problems to be Solved by the Invention] However, with the above-mentioned conventional manufacturing method, it is technically difficult to fill even the narrow parts of the conductor circuit with insulating material, and it is difficult to fill the conductor circuit with the insulating layer. It is easy to create gaps between the
Furthermore, it is difficult to suppress the generation of steps by controlling the shrinkage of the insulating material.
この発明は上記の事情を考慮してなされたものであって
、その目的は導体回路と絶縁材との間に隙間が生じたり
、基材の表面に段差が形成されたりするおそれのない多
層化に適した配線板の製造方法を提供することにある。This invention was made in consideration of the above circumstances, and its purpose is to create a multilayer structure that eliminates the risk of creating gaps between the conductor circuit and the insulating material or forming steps on the surface of the base material. It is an object of the present invention to provide a method of manufacturing a wiring board suitable for.
［課題を解決するための手段皮〆忰用］上記の目的を達
成するために、この発明では、絶縁性基材の表面に導体
回路を形成し、少なくともその導体回路以外の基材表面
に、導体回路の厚みよりも大きな厚みを有する絶縁膜を
形成した後、前記導体回路の表面に、前記絶縁膜の高さ
までメッキ層を形成するようにしている。[Means for Solving the Problems] In order to achieve the above object, in the present invention, a conductive circuit is formed on the surface of an insulating base material, and at least a conductive circuit is formed on the surface of the base material other than the conductive circuit. After forming an insulating film having a thickness greater than the thickness of the conductor circuit, a plating layer is formed on the surface of the conductor circuit up to the height of the insulating film.
従って、上記の製造方法によれば、導体回路と絶縁膜と
の高さを平坦にして、複数の導体回路層を積層する際に
各層の密着性を向上させることができる。Therefore, according to the above manufacturing method, it is possible to flatten the height of the conductor circuit and the insulating film, and improve the adhesion of each layer when laminating a plurality of conductor circuit layers.
前記絶縁性基材としてはセラミックス材料を使用するこ
とが有利であり、セラミックス材料としては窒化アルミ
ニウム、アルミナ、ムライト等も使用できる。基材表面
の導体回路は、基材表面にスパッタリング法等によって
クロム若しくはチタン等からなる導体層を形成した後、
その導体層をエツチングして形成することが望ましい。It is advantageous to use a ceramic material as the insulating base material, and aluminum nitride, alumina, mullite, etc. can also be used as the ceramic material. The conductor circuit on the surface of the base material is formed by forming a conductor layer made of chromium, titanium, etc. on the surface of the base material by sputtering method, etc.
It is desirable to form the conductive layer by etching.
又、導体回路を形成した部分以外の基材表面に絶縁膜を
形成するには、エツチング法やフォトリソグラフィによ
ることが望ましい。この時、第６図に２点′ｕｉ線で示
すように、導体回路の側縁部表面に絶縁剤が覆い被さる
ようにすることが望ましい。絶縁膜を構成する絶縁剤と
しては、ポリイミド樹脂を使用することが望ましく、そ
れ以外にはエポキシ樹脂も使用可能である。Further, in order to form an insulating film on the surface of the base material other than the portion where the conductive circuit is formed, it is preferable to use an etching method or photolithography. At this time, it is desirable that the surface of the side edge of the conductor circuit be covered with the insulating material, as shown by the two-dot 'ui line in FIG. As the insulating agent constituting the insulating film, it is desirable to use polyimide resin, and epoxy resin can also be used.
更に、導体回路の表面を被覆するメッキ膜の構成材料と
しては銅を使用することが望ましく、それ以外には銀、
金、ニッケル等も使用できる。メッキ膜は、化学メッキ
或いは電解メッキによって形成することができる。Furthermore, it is desirable to use copper as the constituent material of the plating film that covers the surface of the conductor circuit, and silver,
Gold, nickel, etc. can also be used. The plated film can be formed by chemical plating or electrolytic plating.
［実施例］
次に、この発明を具体化した配線板の実施例について説
明する。第７図に示すように、基材１は窒化アルミニウ
ム焼結体によってシート状に形成され、その上面にはク
ロム若しくはチタン等の金属からなる厚さ約２０μｍの
導体回路２が形成されている。導体回路２を形成した部
分以外の基材１表面には導体回路２の数倍の厚さを有す
ると共にポリイミド樹脂からなる絶縁膜３が形成されて
いる。[Example] Next, an example of a wiring board embodying the present invention will be described. As shown in FIG. 7, the base material 1 is formed into a sheet shape from a sintered aluminum nitride body, and a conductor circuit 2 made of a metal such as chromium or titanium and having a thickness of about 20 μm is formed on its upper surface. An insulating film 3 made of polyimide resin and having a thickness several times that of the conductor circuit 2 is formed on the surface of the base material 1 other than the portion where the conductor circuit 2 is formed.
更に、各絶縁膜３の間において、導体回路２の表面には
銅メッキ層４が形成され、このメッキ層４の厚みｔ３及
び導体回路２の厚みｔｌの総和Ｔが絶縁膜３の厚みｔ２
と時開−に設定されて、基材１の表面が平坦に形成され
ている。従って、上記の配線板の表裏両面を平坦に形成
でき、多層状に積層する際に、各配線板の密着性を向上
させて、多層配線板の信幀性を向上させることができる
。Furthermore, a copper plating layer 4 is formed on the surface of the conductive circuit 2 between each insulating film 3, and the sum T of the thickness t3 of this plating layer 4 and the thickness tl of the conductive circuit 2 is the thickness t2 of the insulating film 3.
The surface of the base material 1 is formed to be flat. Therefore, both the front and back surfaces of the above-mentioned wiring board can be formed flat, and when laminated in multiple layers, the adhesion of each wiring board can be improved, and the reliability of the multilayer wiring board can be improved.
さて、上記の配線板の製造に際し、先ず第１図に示す基
材１の表面全体に、スパッタリング法によって第２図に
示す金属製導体層２ａを形成した。In manufacturing the above wiring board, first, a metal conductor layer 2a shown in FIG. 2 was formed on the entire surface of the base material 1 shown in FIG. 1 by sputtering.
次に導体層２ａの表面にレジスト膜５を形成し、導体回
路パターンの形状に応じて、第３図に示すようにレジス
ト膜５の不要部分を除去した後、導体層２ ａのエツチ
ングを行うことによって、第４図に示す導体回路２を形
成した。Next, a resist film 5 is formed on the surface of the conductor layer 2a, and after removing unnecessary portions of the resist film 5 according to the shape of the conductor circuit pattern as shown in FIG. 3, the conductor layer 2a is etched. As a result, a conductor circuit 2 shown in FIG. 4 was formed.
次に、第５図に示すように前記レジスト膜５を除去した
。そして、基材１の表面全体にポリイミド樹脂からなる
絶縁材を塗布して、隣接する導体回路２の間に絶縁材を
充填した後、第６図に示すように導体回路２の形成部分
に対応する部分を、エツチングによって除去して絶縁膜
３を形成した。Next, as shown in FIG. 5, the resist film 5 was removed. Then, after applying an insulating material made of polyimide resin to the entire surface of the base material 1 and filling the spaces between adjacent conductor circuits 2, the areas where the conductor circuits 2 will be formed are applied as shown in FIG. The portion to be etched was removed by etching to form an insulating film 3.
そして、最後に、第７図に示すように電解メッキ法によ
って導体回路２の表面に銅メッキ層４を形成した。この
時、メッキ膜４の厚みｔ３及び導体回路２の厚みｔｌの
総和Ｔが絶縁膜３の厚みｔ２に一致するようにメッキを
行った。Finally, as shown in FIG. 7, a copper plating layer 4 was formed on the surface of the conductor circuit 2 by electrolytic plating. At this time, plating was performed so that the sum T of the thickness t3 of the plating film 4 and the thickness tl of the conductor circuit 2 matched the thickness t2 of the insulating film 3.
それにより、基材１の導体回路側の表面を平坦にした配
線板を簡単かつ確実に得ることができ、複数の導体回路
を積層する際に、密着性を向上させて信転性を高めるこ
とができた。As a result, it is possible to easily and reliably obtain a wiring board with a flat surface on the conductor circuit side of the base material 1, and to improve reliability by improving adhesion when laminating a plurality of conductor circuits. was completed.
［発明の効果］
以上詳述したように、この発明は導体回路と絶縁層との
間に隙間が生じたり、基材の表面に段差が形成されたり
するおそれを未然に防止して、表面を平坦に形成するこ
とができ、積層に適した配線板を簡単かつ確実に形成す
ることができるという優れた効果を発揮する。[Effects of the Invention] As detailed above, the present invention prevents the possibility that a gap will occur between the conductor circuit and the insulating layer or that a step will be formed on the surface of the base material, and improves the surface. It can be formed flat and exhibits the excellent effect of easily and reliably forming a wiring board suitable for lamination.
第１図〜第７図は配線板の製造工程を示す断面図である
。
１・・・基材、２・・・導体回路、３・・・絶縁膜、４
・・・メッキ膜、ｔｌ・・・導体回路の厚み、ｔ２・・
・絶縁膜の厚み、ｔ３・・・メッキ膜の厚み、Ｔ・・・
厚み１１．１２の総和。1 to 7 are cross-sectional views showing the manufacturing process of the wiring board. DESCRIPTION OF SYMBOLS 1... Base material, 2... Conductor circuit, 3... Insulating film, 4
...Plating film, tl...Thickness of conductor circuit, t2...
・Thickness of insulating film, t3... Thickness of plating film, T...
Total thickness of 11.12.
Claims (1)
、 次いでその導体回路（２）以外の基材表面に、導体回路
（２）の厚み（ｔ１）よりも大きな厚み（ｔ２）を有す
る絶縁膜（３）を形成した後、前記導体回路（２）の表
面に、前記絶縁膜（３）の高さまでメッキ膜（４）を形
成することを特徴とする配線板の製造方法。[Claims] 1. A conductor circuit (2) is formed on the surface of an insulating base material (1), and then a thickness (t1) of the conductor circuit (2) is formed on the surface of the base material other than the conductor circuit (2). After forming an insulating film (3) having a thickness (t2) greater than , a plating film (4) is formed on the surface of the conductor circuit (2) up to the height of the insulating film (3). A method of manufacturing a wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25672289A JPH03119789A (en) | 1989-09-29 | 1989-09-29 | Manufacture of wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25672289A JPH03119789A (en) | 1989-09-29 | 1989-09-29 | Manufacture of wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03119789A true JPH03119789A (en) | 1991-05-22 |
Family
ID=17296542
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25672289A Pending JPH03119789A (en) | 1989-09-29 | 1989-09-29 | Manufacture of wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03119789A (en) |
-
1989
- 1989-09-29 JP JP25672289A patent/JPH03119789A/en active Pending
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