經濟部中央標準局貝工消费合作社印裝 A7 B7 .............^ 五、發明说明（1 ) 申請專利範園優先權當屬於1996年5月1曰申請之美國暫 定專利申請號碼6〇/016,665。 本發明大體關於製造印刷電路板之方法。特別是有關— 形成非常纖維電路線之新穎方法。 在典型印刷電路板之生產中，薄銅箔被積層至一絕緣基 板，通常是一玻璃強化環氧基樹脂預浸溃體，然後該積層 被進一步處理，藉化學蝕刻經由選擇性地去除銅之部分將 該銅箔轉變爲一電路型式。此蚀刻一般是令人滿意的，但 是每當需要較纖維（較窄）電路線噼其限制就變得明顯。 很頻繁地，爲了增強其結合至絕緣基板之能力，銅结可 以在積層之前被處理。爲了此應用，除非以其他特定方 式’在此參考銅洛將被推斷爲交替地參考被處理及未被處 理銅箔二者。 〃 ’實際上’蚀刻並未產生電路線之垂直邊。而是他們傾向 下切光阻及較少在線之底部蝕刻而去除線之頂端上太多 銅，留下一有些不規則狀電路線。結果，電路線之最小寬 度被容許此不一致蝕刻之需求所限制。此問題在美國專利 文號5,437,914中已被討論，而且顯示蝕刻電路線之形狀受 銅羯紋理結構之形狀所影響。根據，914專利，隨著磨光邊 向下藉積層銅箔至基板，蝕刻之改良精確將被獲得，與習 知之實行相反。 另外改良電路線之精確之方法是使用較薄銅箔，因爲他 們能夠以較少切除被很快地蝕刻。然而，此箔並不容易處 理。因此’有了提議沈積銅之薄層於能夠在箔被積層至— —-- -4 - 本纸張尺度適财國_縣（CNS) A4規格（21Gx297公楚） -----------— f請先閲讀背面之注意事項再填寫本頁)Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives, A7, B7, .................. V. Description of Invention (1) The priority of applying for a patent park shall belong to the application of May 1, 1996 US Provisional Patent Application No. 60 / 016,665. The present invention relates generally to a method for manufacturing a printed circuit board. Especially relevant-a novel way to form very fiber circuit wires. In the production of a typical printed circuit board, a thin copper foil is laminated to an insulating substrate, usually a glass-reinforced epoxy resin pre-impregnated body, and then the laminate is further processed by selectively removing copper by chemical etching. The copper foil is partially converted into a circuit type. This etch is generally satisfactory, but its limitations become apparent whenever a fiber (narrower) circuit line is required. Very often, to enhance its ability to bond to an insulating substrate, copper junctions can be processed before lamination. For this application, unless reference is made to Tongluo here in other specific ways, it will be inferred to refer to both treated and untreated copper foils alternately. ’'Actually' etching does not produce vertical edges of the circuit lines. Instead, they tend to undercut the photoresist and less etch the bottom of the line to remove too much copper from the top of the line, leaving a somewhat irregular circuit line. As a result, the minimum width of the circuit lines is limited by the need to allow this inconsistent etching. This problem has been discussed in U.S. Patent No. 5,437,914, and it has been shown that the shape of the etched circuit lines is affected by the shape of the copper ridge texture structure. According to the 914 patent, as the polished edge borrows the copper foil down to the substrate, the improved accuracy of the etching will be obtained, as opposed to the conventional practice. Another way to improve the accuracy of circuit lines is to use thinner copper foil because they can be etched quickly with less cut-off. However, this foil is not easy to handle. Therefore, 'There is a proposal to deposit a thin layer of copper to be able to be laminated on the foil to ----- -4-This paper size is suitable for the country of wealth_County (CNS) A4 size (21Gx297 Gongchu) ------- ----— f Please read the notes on the back before filling in this page)
、1T ^ A7 B7 輕濟部中央插率局ΙΗ消贽合作.杜印製 -5- 五 '發明説明（2 ) 基板後被移除之支撑薄板上。一實例被發現於美國專利文 號3,998<01中2-12微米銅層被沈積於一習知厚鋼羯（如35_ 70微米）且被一釋放層分離。積層合成箔至—基板之後， 支撑銅箔被機械式地剝去，留下現成用於處理—電子電路 之薄2-12微米箔。當支撑箔被剝去，此—程序會導致移除 薄箔之部分。 本發明以一種完全不同之方法解決蝕刻問題。_箱在產 生電路線中並未被蝕刻去除，而是電路線在被—光阻界定 之缘溝内被電沈積至很薄傳導層-上。爲使用以製造多層電 路板之外部電路層’該方法特別有利，但也可以用於内部 層或一及兩面電路板上。 發明摘要 —方面，在被一熟化光阻界定之區域中，藉塗敷銅於 —薄傳導層上，本發明是一形成非常狹窄電路線於—非導 電性基板之新穎方法。藉塗敷一導電性金屬、金屬或合金 之薄層至非導電性基板上，這是可能達成的。導電性金屬 層介於鋼及基板間，導電性金屬、金屬或合金被塗敷至一 銅箱薄板，然後銅箔被積層至一基板。假如銅箔被處理以 增強其接合至基板之能力’導電性金屬可以在此處理之前 或之後被塗敷至銅箔。當處理電路板時，銅箔被蝕刻去 除’留下薄導電性金屬。然後—光阻被塗敷、成像及熟 化。未使光阻熟化被移除，如此界定了所需求電路線之區 域或"壕溝"。由於現在傳導層被曝光，選擇性地塗敷電 路線在這些區域是可能的。最後，熟化光眭被移除且被曝 私紙張尺度適用中®I國家鮮（CNS ) A4^f§· ( 21GX297公楚 ----；-I—ΊΠ ———- — 丨-玎------Λ 丨 (請先閲讀背面之注意事項再填寫本頁} A7 B7 經濟部中央標準局員工消费合作社印製 五、發明説明（3 ) 光之導電性金屬層藉化學蝕刻被移除，留下完成之電路。 熟諳此藝者將了解銅箔及導電性金屬，可藉任何習知之 方法包括，但不限於此，電解沈積、化學蒸發沈積、非電 沈積及濺射，而被抹塗至個別表層。 在一較佳具體實施例中，在使電路線電沈積之前無電錦 鍍覆被用來涵蓋導電性金屬層。 圖示之説明 圖1是一本發明應用於多層電路板製程之區塊圖。 圖2是一用於多層路板先前技藝製程之區域圖。 圖3説明了與本發明多層電路板比較習知電路線之切面 圏。 較佳具體實施例之説明 本發明包括一形成一電路板及導致該製程之板之新穎製 程。該製程採用習知之程序，但具有重大優勢，特別是該 電路線較習知之製程被更精確界定。如此，可以產生較纖 細電路線，能夠在板上被較密集封裝。 電沈積金屬於銅箔上是習知作法β例如，在專利中 一結狀沈積鋼形成於銅箔之磨光（平滑）邊，以使其粗糙並 改良至絕緣基板之附著。在共同專利申請一般指定美國專 利〇8/517,321中，一纖細沈積被放置於銅箔上以改良附 著，雖然該箔之測量粗糙未被改變。一相同方法被揭示於 美國專利5,482,784中。 在系列才曰疋至歐米加電子（Ohmega Electronics)(例如， 美國4,808,967)文號之專利中，—用於產生電阻於一印刷 -6 —^ I 衣 訂^ 1^ (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS 1 A4找抵ί ?m、y〇〇7八教 \ 經濟部中央標準局員工消资合作社印來 A7 B7 五、發明説明（4 ) 電路板之表層上之技術被讨論。它是以銅落表面上一鎳磷 層之電沈積開始的，然後被積層至—絕緣基板。除了充當 一典型傳導層外，該鎳磷層藉選擇性將涵蓋在電路設計中 所需電阻之銅蝕刻去除而被曝光。留下之銅層藉習知之蝕 刻程序變成導電性電路線。 本發明之製程清楚地與藉選擇性地蝕刻去除銅而形成電 路線製程之習知電路板不同。如以上説明，化學蝕刻有先 天上限制，當電路線變得較窄及其紋距變得較接近時變得 特別麻煩。本發明之新穎製程直-接將電路線沈積進入由光 阻蝕劑之使用所產生之間隔，留下打開的壕溝被銅之電沈 積所填滿。一旦涵蓋銅而箔載體被移除，這被餘留於基板之 表面上之傳導層變得可能。本發明之製程也與在基板表.面 充纟一電阻之層上之歐米加（Ohmega)製程不同。 如塗敷至一多層板之外層之製程被顯示於圖工之區塊圖 中。在第一步驟中，經由一可溶解導電性金屬之合成物之 電解槽銅板箔被穿過，且他們被電沈積至一箱之表面上厚 度約〇_2至5微米上，在去光澤或磨光邊。如先前所確認， 不是導電性金屬之塗敷前就是塗敷後，銅箔可以被給予一 處理（例如結狀銅）以改良其至絕緣基板之附著。金屬或合 金可以是錫、錄 ' 錫辞、鋅錄 '錫銅及其他，假如他們在 其後步驟中用來移除銅之蝕刻有光阻力a電予製_程之情況 是那些商業上被使用典型，以提供銅箔上之保護金屬層。 在第二步驟中，磨光的㈣被積層至-使用習知技術及 以鄰近基板之導電性金屬之絕縣板，例如常用之玻璃增 本紙張尺度適财關家標率（⑽）M規格（2丨㈤97公楚） ;：I-τί I (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部中央標準局員工消f合作社印裝 A7 _____ B7 _ 五、發明説明（5 ) 下一步驟是將銅箔蝕刻去除，留下嵌入基板之表層中導 電性金屬之薄層。爲此，蝕刻被選擇自將移除銅處，而非 到一重要程度傳導層之金屬。一此蝕刻之實例是氨化銅。 薄銅箔過去自鋁支撑層被應用，與被蝕刻鋁方式相同。一 本製程之優點是銅是可收回的且與溶解鋁之污損被避免。 假如在本發明之製程中鋁被替換成銅板將會發生。一旦銅 板被蚀刻去除，導電性金屬（或合金）層被曝光並現成用於 光阻之塗敷、成像及熟化。 本發明之製程中，未熟化光阻:被移除以使將形成電路線 之壤溝曝光。對熟諳此藝者將顯而易見熟化光阻將較精確 地界定電路線，且填滿壤溝之銅將較曝光區域中藉蝕刻去 除銅板形成之電路線接近到達理想之矩形狀。這表示較纖 細電路線能夠被完成，因爲其形狀並__不被一蚀刻製程所決 定°因此，除了 4密爾（mil)(100微米）線及間隔，新穎方法 容許降低線及間隔至約i密爾（mil)(25微米）。 銅板使習知程序被電沈積，例如常用來鍍覆鋼板至多層 電路板之外部當嵌入基板表層中之金屬薄層導電性足 夠’是可能做到的。假如不然，銅板之無電鍍覆能夠被用 來促進電路線之電沈積。銅板能夠被增進如所需厚度，— 直達到界定壕溝形狀光光阻蝕劑之高度。 在這點上，電路線被形成。所留下的是藉習知方法移除 光P 以下被曝光之導電性金屬層藉使用一例如氨酸銅 蝕刻被移除。 本發明具有製作多層電路板外層之特殊價値。多層電路 板一般具有關於以銅板被無電鍍覆之外與内層之洞，然後, 1T ^ A7 B7 The Ministry of Light Industry Central Interpolation Bureau Ⅰ Η eliminate cooperation. Du Yin -5- Five 'Invention (2) The supporting sheet after the substrate is removed. An example is found in U.S. Patent No. 3,998 < 01 where a 2-12 micron copper layer is deposited on a conventional thick steel reed (e.g. 35-70 micron) and separated by a release layer. After laminating the composite foil to the substrate, the supporting copper foil was mechanically peeled off, leaving a thin 2-12 micron foil ready for processing electronic circuits. When the supporting foil is peeled off, this procedure will cause the thin foil portion to be removed. The present invention addresses the problem of etching in a completely different way. The box is not etched away in the generated circuit line, but the circuit line is electrodeposited onto a very thin conductive layer in the edge groove defined by the -photoresist. This method is particularly advantageous for use in the manufacture of external circuit layers for multilayer circuit boards, but can also be used for internal layers or on one or both sides of a circuit board. Summary of the Invention-In one aspect, the present invention is a novel method of forming very narrow circuit lines on a non-conductive substrate by coating copper on a thin conductive layer in an area defined by a cured photoresist. This is possible by applying a thin layer of a conductive metal, metal or alloy to a non-conductive substrate. A conductive metal layer is interposed between the steel and the substrate. The conductive metal, metal or alloy is applied to a copper box sheet, and then the copper foil is laminated to a substrate. If the copper foil is treated to enhance its ability to bond to the substrate, the conductive metal may be applied to the copper foil before or after this treatment. When the circuit board is processed, the copper foil is etched away 'leaving a thin conductive metal. Then—the photoresist is applied, imaged, and cured. The photoresist curing has not been removed, thus defining the area of the required circuit line or "ditch". Since the conductive layer is now exposed, it is possible to selectively coat the electrical lines in these areas. Finally, the curing light was removed and exposed to private paper. Applicable to China's national standards (CNS) A4 ^ f§ · (21GX297 Gongchu ----; -I—ΊΠ ———- — 丨-玎- ---- Λ 丨 (Please read the precautions on the back before filling in this page} A7 B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (3) The conductive metal layer of light was removed by chemical etching Those skilled in the art will understand copper foil and conductive metal, and can be wiped away by any conventional method including, but not limited to, electrolytic deposition, chemical evaporation deposition, non-electrodeposition and sputtering. It is applied to individual surface layers. In a preferred embodiment, electroless bromide plating is used to cover the conductive metal layer before the circuit lines are electrodeposited. Explanation of the figure Figure 1 is a process for applying the present invention to a multilayer circuit board Figure 2 is a block diagram of a prior art process for a multilayer circuit board. Figure 3 illustrates a cross section of a conventional circuit line compared to the multilayer circuit board of the present invention. Description of a preferred embodiment The present invention includes Forming a circuit board and a board leading to the process Novel process. This process uses a known process, but has significant advantages, especially the circuit line is more accurately defined than the conventional process. In this way, it can produce thinner circuit lines, which can be densely packed on the board. Electrodeposited gold Belonging to the copper foil is a conventional practice β. For example, in the patent, a knot-shaped deposited steel is formed on the polished (smooth) edge of the copper foil to make it rough and improve the adhesion of the insulating substrate. Common patent applications generally specify the United States In patent 08 / 517,321, a fine deposit is placed on a copper foil to improve adhesion, although the measurement of the foil is not altered. An identical method is disclosed in U.S. Patent 5,482,784. The series is described in Omega to Omega Electronics (Ohmega Electronics) (for example, U.S. 4,808,967) document number—for the purpose of generating resistance in a printing-6 — ^ I clothing order ^ 1 ^ (Please read the precautions on the back before filling this page) This paper size Applicable to Chinese National Standards (CNS 1 A4 arrives at ί? M, y〇07 八 教 \ Central Standards Bureau of the Ministry of Economic Affairs, printed by the Consumers' Cooperative of A7 B7 V. Description of Invention (4) Circuit Board The layer-on-layer technology is discussed. It starts with the electrodeposition of a nickel-phosphorus layer on the copper surface and is then laminated to an insulating substrate. In addition to acting as a typical conductive layer, the nickel-phosphorus layer will be selectively covered by The copper resistance required for circuit design is removed by copper etching and exposed. The remaining copper layer becomes a conductive circuit line by a conventional etching process. The manufacturing process of the present invention is clearly similar to the process of forming a circuit line by selectively removing copper by etching. Conventional circuit boards are different. As explained above, chemical etching has inherent limitations, which becomes particularly troublesome when circuit lines become narrower and their pitches become closer. The novel process of the present invention directly deposits circuit lines Enter the gap created by the use of photoresist, leaving open trenches filled with copper electrodeposition. Once the copper is covered and the foil carrier is removed, this becomes possible with a conductive layer remaining on the surface of the substrate. The process of the present invention is also different from the Ohmega process on the surface of the substrate filled with a resistor. For example, the process of applying to the outer layer of a multilayer board is shown in the block diagram of the graphics worker. In the first step, copper foils of electrolytic cells are passed through a composition that can dissolve conductive metals, and they are electrodeposited on the surface of a box to a thickness of about 0 to 5 micrometers. Polished edges. As previously confirmed, either before or after the application of the conductive metal, the copper foil may be given a treatment (such as knotted copper) to improve its adhesion to the insulating substrate. Metals or alloys can be tin, tin, tin, zinc, tin, copper, and others. If they are used to remove copper in subsequent steps, the etching will have photoresistance. Typical use to provide a protective metal layer on copper foil. In the second step, the polished plutonium is laminated to a plate using conventional techniques and conductive metal adjacent to the substrate, such as commonly used glass-enhanced paper.丨 ㈤97 公 楚);: I-τί I (Please read the precautions on the back before filling this page) Order the staff of the Central Standards Bureau of the Ministry of Economic Affairs and the cooperative printed A7 _____ B7 _ V. Description of the invention (5) Next step The copper foil is etched away, leaving a thin layer of conductive metal embedded in the surface layer of the substrate. For this reason, the etch is chosen from the metal where the copper will be removed, rather than to a significant extent the conductive layer. An example of this etching is copper amide. Thin copper foil was previously applied from an aluminum support layer in the same way as aluminum was etched. An advantage of this process is that copper is recoverable and fouling with dissolved aluminum is avoided. This would happen if aluminum was replaced with copper in the process of the present invention. Once the copper plate is etched away, the conductive metal (or alloy) layer is exposed and ready for photoresist coating, imaging, and curing. In the process of the present invention, the uncured photoresist is removed to expose the soil trench that will form a circuit line. It will be apparent to those skilled in the art that curing photoresist will more accurately define circuit lines, and that the copper filling the soil trench will be closer to the ideal rectangular shape than the circuit lines formed by etching to remove the copper plate in the exposed area. This means that thinner circuit lines can be completed because their shape is not determined by an etching process. Therefore, in addition to 4 mil (100 micron) lines and spacing, the novel method allows to reduce the lines and spacing to about i mil (25 microns). The copper plate allows conventional processes to be electrodeposited. For example, it is commonly used to plate steel plates to the outside of multi-layer circuit boards when a thin metal layer embedded in the surface layer of the substrate is sufficiently conductive '. If not, the electroless plating of copper can be used to facilitate electrodeposition of circuit lines. The copper plate can be increased to the required thickness—up to the height of the photoresist that defines the trench shape. In this regard, a circuit line is formed. What remains is the removal of light P by conventional methods. The conductive metal layer exposed below is removed by using, for example, copper etch. The invention has a special price for making the outer layer of a multilayer circuit board. Multilayer circuit boards generally have holes on the outer and inner layers that are plated with copper, and then
本紙張尺度適^( CNS ) Λ4規;( 21GX297:f ) ------J (請先閱讀背面之注意事項再填寫本頁) 衣· I . 五、發明説明（6 A7 B7 電路線被電予鍍覆所形成。典型程序顯示於圖2之區塊圖 中。銅板箱與一至内電路層預浸潰體之插入層被積層，但 不是被蝕刻去除。無電鍍覆被用來沈積銅板至箔上並下至 連接該層之洞。然後，一光阻被塗敷且銅電路線被電子鍍 覆。在此點上，過多銅箔必須被蝕刻所移除。然而，電路 線及鍍覆洞必須被一電子鍍覆一光阻金屬例如錫保護。然 後’光阻能夠被移除且曝光銅板箔可被箔。可以察知此_ 步驟導致電路線之邊也不被附著錫所保護。在本發明中， 錫不需被塗敷因爲它只需移除錫傳導層，可以很快地被完 成。很重要地’必須用於塗敷及移除錫方案之處理之實質 成本被避免了。 圖3説明了藉好比使用本發明之製程所形成必要矩形線 之習知蝕刻製程形成於多層電路板之··外層中之電路線β先 前技藝之電路線在電路線被形成（頂端被錫層所保護）之 後，藉蝕刻去除銅箔之需要被嚴格地切除。 本發明之製程使電路線之較精確生產成爲可能，如此電 路設計者不必補償先天上藉蝕刻電路線形成之不精確。該 製程使用電路板製造商所熟悉之技術且不包括技術上大改 變。事實上’當採用本發明之製程時，我們預期製程將可 以簡化。 I-_ I —《f- (請先閲讀背面之注項再填寫本頁) 訂 經濟部中央標準局貝工消资合作社印製 -9 - 本纸張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐）This paper is suitable for ^ (CNS) Λ4 regulations; (21GX297: f) ------ J (Please read the precautions on the back before filling this page). I. V. Description of the invention (6 A7 B7 circuit line It is formed by electroplating. The typical procedure is shown in the block diagram in Figure 2. The copper box and the interlayer of the pre-impregnated body of the inner circuit layer are laminated, but not removed by etching. Electroless plating is used to deposit The copper plate goes to the foil and down to the hole connecting this layer. Then, a photoresist is applied and the copper circuit wires are electronically plated. At this point, too much copper foil must be removed by etching. However, the circuit wires and The plating hole must be protected by an electronic plating of a photoresist metal such as tin. Then the photoresist can be removed and the exposed copper foil can be covered by foil. It can be seen that this step leads to the side of the circuit line not being protected by tin. In the present invention, tin does not need to be coated because it only needs to remove the tin conductive layer and can be completed quickly. It is important that the substantial cost of the process that must be used for the coating and removal of the tin solution is avoided Fig. 3 illustrates the necessary rectangular line formed by using the process of the present invention. It is known that the etching process is formed on the outer layer of the multi-layer circuit board. The circuit wires in the outer layer β The circuit wires of the prior art are formed after the circuit wires are formed (the top is protected by the tin layer), and the copper foil needs to be strictly removed by etching. The invented process enables more accurate production of circuit lines, so that circuit designers do not have to compensate for the inaccuracy formed by etching circuit lines inherently. This process uses techniques familiar to circuit board manufacturers and does not include major technical changes. Facts When using the process of the present invention, we expect that the process will be simplified. I-_ I — "f- (Please read the note on the back before filling this page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs -9-This paper size applies to China National Standard (CNS) Α4 specification (210X297 mm)