KR19980081867A - Micro Circuit Line Formation Method - Google Patents

Abstract

A new method of forming circuit lines on a substrate by supplying a conductive metal (metals) using copper foil as a carrier. The copper foil is etched, leaving only the conductive metal embedded in the surface of the substrate. Photoresist is used to expose the trenches that determine the desired circuit and copper is supplied over the exposed conductive metal. This method is particularly suitable for manufacturing the outer layer of a multilayer circuit board.

Description

Micro Circuit Line Formation Method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a printed circuit board, and more particularly, to a method for forming a high fine circuit line.

In the manufacture of a typical printed circuit board, a thin copper foil is laminated to an insulating substrate, more often epoxy glass prepreg reinforced glass, and then the laminate is processed to obtain copper by chemical etching. The copper foil becomes a circuit pattern as a part is selectively removed. Such etching is generally a satisfactory process, but there are obvious limitations to forming fine (narrow) circuit lines.

Copper foil is often processed prior to lamination to improve adhesion to insulating substrates. For the purposes of this application, unless otherwise indicated, reference to copper foil herein will be interpreted interchangeably to refer to treated and untreated copper foil.

In practice, etchant does not make a vertical plane of the circuit line. Instead, the etchant undercuts the resist to etch more copper over the circuit line and less etch the copper below, forming a roughly trapezoidal circuit line. As a result, the minimum width of the circuit line is defined by this non-uniform etching. This problem has been discussed in US Pat. No. 5,437,914, which discloses that the shape of the etched circuit lines is affected by the grain structure of the copper foil. The improved accuracy of etching can be realized by laminating copper foil on a substrate having a shiny side according to the above-mentioned 5,437,914 patent. Improved etching factors cause the sides of the circuit lines to be nearly vertical.

Another approach to improving the accuracy of the circuit lines is to etch the copper foil quickly with less undercutting using thinner copper foil. However, such copper foil is not easy to handle. As a result, it is proposed to form a thin layer of laminated copper on a support plate that can be removed after the copper foil is laminated to the substrate. An example is disclosed in US Pat. No. 3,998,601, wherein a 2-12 μm copper layer is laminated on a conventional thick copper foil (35-70 μm) and separated by a release layer. After laminating the synthetic foil on the substrate, the supporting copper foil is peeled off mechanically, leaving only 2-12 μm thin foil prepared for the processing of the electric circuit. This method is possible because part of the thin foil is removed when the support foil is peeled off.

In the present invention, the etching problem is solved in a completely different way. To make the circuit lines, rather than etching the copper foil, the circuit lines are electrically layered over a very thin conductive layer in the trenches defined by the resist. This method has particular advantages not only in forming the outer circuit layer of the multilayer circuit board but also in the fabrication of the inner layer, single sided or double sided circuit board.

In one aspect of the present invention, the present invention is a novel method of forming a very narrow circuit on a nonconductive substrate by supplying copper over a thin conductive layer in a region defined by a cured photoresist. This is made possible by supplying a conductive metal, conductive metals or a conductive alloy to the nonconductive substrate. The conductive metal, the conductive metals or the conductive alloy are supplied to the copper foil plate, and then the copper foil is laminated on the substrate to form a conductive metal layer between the copper and the substrate. When copper foil is processed in order to improve the adhesiveness with a board | substrate, a conductive metal is supplied to copper foil before or after the said process. During the circuit board process, the copper foil is etched to leave the thin conductive metal in the etched position. The photoresist is fed, imaged, and cured. The uncured resist is removed to define the area or trench where the circuit lines are formed. Since the conductive layer is exposed, it is possible to selectively form a circuit line in the region. Finally, the cured photoresist is removed and the exposed conductive metal layer is removed by chemical etching leaving only the last circuit.

It is well known that copper foil and conductive metal are supplied to each surface by conventional methods such as electroless lamination, chemical vapor deposition (CVD), electroless lamination and sputtering.

In a preferred embodiment, electroless copper plating covers the conductive metal layer before the electrical layer of the circuit.

1 is a block diagram of the process of the present invention applied to a multilayer circuit board.

2 is a block diagram of a conventional process for a multilayer circuit board.

3 is a cross-sectional view comparing a conventional circuit line and the circuit line of the present invention in a multilayer circuit board.

The present invention includes a novel process for manufacturing a printed circuit board and a substrate produced by the process. The process employs conventional methods but in particular has the advantage that the circuit lines are formed more accurately than in conventional processes. Thus, finer circuit lines can be formed, making it possible to form circuits more densely on the substrate.

Electrical layering of metal on copper foil is a conventional method. For example, in Patent No. 5,437,914, nodular deposit copper is formed on the smooth side of a copper foil to roughen the side to improve adhesion to an insulating substrate. In pending US patent application Ser. No. 08 / 517,321, the measured roughness does not change but the microlamination is placed on the copper foil to improve adhesion. Similar access is disclosed in US Pat. No. 5,482,784.

A series of patents assigned to Ohmega Electronics (eg US Pat. No. 4,808,967) discusses the art of forming a resistor on the surface of a printed circuit board. In this technique, a nickel-phosphorus layer is electrically formed on the surface of a copper foil and then laminated to an insulating substrate. The nickel-phosphorus layer is exposed by selectively etching the covering cooper where it requires resistance in the circuit design rather than acting as a typical conductive layer.

The process of the present invention is clearly different from the conventional process of selectively etching copper to form circuit lines. As described above, chemical etching has a unique limitation in that a problem occurs in that the circuit line is narrowed and the pitch is formed close. The new process of the present invention stacks circuit lines directly in the space formed by the use of photoresist, leaving trenches filled by the electrical layer of copper. This is formed by the conductive layer left on the substrate from which the cover copper foil carrier has been removed. The process of the present invention is clearly different from the invention of omega electrics in which a layer on the substrate surface acts as a resistance.

The process of the invention applied to an outer layer of a multilayer circuit board is shown in block diagram in FIG. In the first step, the copper foil is passed through a synthetic molten bath of conductive metal to be electrically laminated on one surface of the copper foil and about 0.2-5 μm thick on a matte or shiny side. As previously defined, before or after the supply of the conductive metal, the copper foil is treated (such as the formation of nodular copper) to improve adhesion to the insulating substrate. Metals or alloys that are resistant to etchant used to remove copper in subsequent steps, such as tin, nickel, tin-zinc, zinc-nickel, tin-copper, etc., are mainly used. The conditions of the electrical layer process are common processes used commercially to form metal coding on copper foil.

In a second step, the coded copper foil is laminated to the substrate such that the conductive metal is adjacent to an insulating substrate such as glass reinforced with epoxy resin using conventional techniques.

In the next step, the copper foil is etched to form a thin layer of conductive metal embedded in the substrate surface. For this purpose, an etchant is used that removes copper but not the metal of the conductive layer. Such etchant is ammoniacal cupric chloride. In the past, thin copper foil was supplied from an aluminum support layer to etch aluminum by a similar method. The advantage of this process is that the copper is resilient and contamination by molten aluminum does not occur, which occurs when aluminum is replaced by copper in the process of the present invention. Once the copper is etched, the conductive metal layer (or alloy layer) is exposed and ready for supply, imaging and curing of the photoresist.

In the process of the present invention, the uncured photoresist is removed to expose the trench in which the circuit lines are to be formed. It is well known that the cured photoresist more accurately defines the circuit lines and becomes even more ideal rectangular shape than the circuit lines formed by etching copper in the exposed areas of the copper filled in the trenches. This means that finer circuit lines can be formed because the shape of the circuit lines is not determined by the etching process. As a result, the process according to the present invention can reduce circuit and space of 4 mils (100 μm) to about 1 mil (25 μm).

Copper is electrically laminated using conventional methods of plating copper on the outer surface of a multilayer circuit board. This method is possible when a thin layer of metal embedded in the surface of the substrate has sufficient conductivity. If the conductivity is not sufficient, electroless copper plating will be used to facilitate electrical lamination of the circuit lines. Copper may be laminated to a desired thickness up to the thickness of the photoresist, which determines the shape of the trench. Conventional electrical lamination conditions are used as the electrical layer conditions.

At this time, a circuit line is formed. After the exposed conductive metal layer is removed by an etchant such as acid cupric chloride or sulfur peroxide, the photoresist is removed by conventional methods.

It is well known that certain steps of the invention (eg, as shown in FIG. 1) may be carried out in other commercially viable sequences. In particular, the steps following the step of forming the conductive layer in the lamination may be implemented in whatever method the operator performs.

The present invention has a singular value in manufacturing the outer layer of the multilayer circuit board. Multilayer circuit boards generally have holes connecting the outer and inner layers where circuit lines are formed by electroplating after copper is electroless plated. The general sequence is shown in the block diagram of FIG. The copper foil is laminated to the inner circuit layer together with the intermediate layer of prepreg, but is not etched. Copper is deposited on the foil and under the holes connecting the layers by electroless plating. Thereafter, resist is supplied and the copper circuit lines are electrically layered. At this time, excessive copper foil must be removed by etching. However, circuit lines and plated holes must be electrically layered and protected from resistive metals such as tin. Thereafter, the resist is removed and the exposed copper foil is etched. This step causes the side of the circuit to be unprotected by the attached tin. In the present invention, since only the thin conductive layer is needed to be removed, it is not necessary to laminate tin, and the process proceeds very quickly. In particular, it is possible to prevent the occurrence of the solution treatment cost required to supply and remove tin.

3 is a view showing a comparison between a substantially rectangular circuit line formed by the process of the present invention and a circuit line formed on the outer layer of the multilayer circuit board by a conventional etching process. Conventionally, since a copper foil is etched after forming a circuit line, a circuit line is severely undercut (the upper part is protected by tin coding).

The process of the present invention enables more accurate fabrication of the circuit line, so that the circuit designer does not have to correct for inaccuracies in forming the circuit by etching. This means that the circuit formed is smaller and more compact. Since the process uses a technology similar to the circuit board manufacturing technology, many changes in technology do not occur. In fact, the manufacturing process to which the process of the present invention will be applied will be simplified.

Claims (10)

(a) forming a conductive metal layer resistant to the etchant used to remove copper on the copper foil; (b) laminating a conductive metal comprising the copper foil of step (a) on the prepreg or film substrate; (c) etching the copper foil from the laminate produced in step (b) to leave a conductive metal embedded in the surface of the prepreg or film substrate; (d) supplying, imaging and curing the photoresist over the conductive metal and the substrate produced in step (c); (e) removing the photoresist of step (d) to leave a trench with exposed conductive metal; (f) supplying copper over the exposed conductive metal of step (e) to form a circuit line; And (g) removing the cured photoresist of step (d) to expose the conductive metal and etch the exposed conductive metal to produce a circuit line on the substrate. The method of claim 1 wherein the conductive metal layer is 0.2-5 μm thick. The method of claim 1, wherein the conductive metal is supplied onto the copper foil by electroplating. The method of claim 1, wherein the conductive metal is supplied onto the copper foil by chemical vapor deposition (CVD). The method of claim 1, wherein the conductive metal is supplied to the copper foil by electroless plating. The method of claim 1, wherein the conductive metal is supplied to the copper foil by sputtering. The method of claim 1 wherein the conductive metal is selected from the group consisting of tin, nickel, tin-zinc, zinc-nickel and tin-copper. A stack comprising a substrate on which circuit lines are formed by the method of claim 1, 2, 3, 4, 5, 6, or 7. The stack of claim 8, wherein the substrate is an inner layer of the multilayer circuit board. Copper foil used for manufacturing a board | substrate by the method of Claim 1, 2, 3, 4, 5, 6, or 7.