KR20120072637A - The printed circuit board and the method for manufacturing the same - Google Patents

Abstract

PURPOSE: A printed circuit board and a manufacturing method thereof are provided to reduce the manufacturing processes for a printed circuit board by simultaneously forming an internal circuit layer and via holes. CONSTITUTION: A core insulation layer is composed of laminated first and second insulation layers(120,125) which are formed of a thermosetting or thermoplastic polymer substrate, a ceramic substrate, or an organic-inorganic composite substrate. Via holes(115) and an internal circuit layer(111) are formed in the core insulation layer. The via holes include a first part(115a) formed of copper-containing alloy, a second part(115b) buried in the second insulation layer, and a third part formed between the first and second parts. The internal circuit layer is formed on the second insulation layer. An external circuit layer including via pads(135,145) connected to the via holes and a circuit pattern(131) is formed on the top of the first and second insulation layers.

Description

[0001] The present invention relates to a printed circuit board and a method of manufacturing the same,

The present invention relates to a printed circuit board and a method of manufacturing the same.

Printed Circuit Boards (PCBs) are like copper on electrically insulating substrates.

Is formed by printing a circuit line pattern with a conductive material, and refers to a board immediately before mounting an electronic component. That is, it means the circuit board which fixed the mounting position of each component, and printed and fixed the circuit pattern which connects components to the flat surface surface, in order to mount many electronic elements of various types densely on a flat plate.

Such printed circuit boards generally include a single-layer PCB and a build-up board in which multilayered PCBs are formed, that is, multilayer PCB substrates.

These build-up boards and multilayer PCB boards manufacture boards one by one,

By evaluating the quality, the yield of the overall multilayer PCB board can be increased, and the interlayer wiring can be improved.

By connecting precisely, it is possible to manufacture high density compact PCBs. In this build-up process, a connection line of a wiring is formed between the layers and the layers are connected through via holes between the layers. In order to form such a via hole, a very fine diameter can be realized using a laser rather than a conventional mechanical drill.

1 is a cross-sectional view of a conventional multilayer printed circuit board.

Referring to FIG. 1, a conventional multilayer printed circuit board 10 includes a core insulating layer 1, internal circuit pattern layers 3 and 4 formed on and under the core insulating layer 1, and the internal circuit. Upper and lower insulating layers 5 and 6 filling the pattern layers 3 and 4 and external circuit pattern layers 7 and 8 formed on the upper and lower insulating layers 5 and 6 are included.

In the core insulating layer 1 and the upper and lower insulating layers 5 and 6, conductive vias 2 and conductive via holes electrically connecting the internal circuit pattern layers 3 and 4 and the external circuit pattern layers 7 and 8 are formed. It is.

In the conventional multilayer printed circuit board 10 described above, a process of forming an even number of circuit pattern layers (four layers are formed in the illustrated figure) centering on the core insulating layer 1 is generally performed. A process of electrically connecting two layers corresponding to the outer layers by using a drill or a laser is performed. However, since the number of circuit pattern layers is limited to an even number, there is a problem in that the thickness of the substrate is increased so that it is difficult to apply to a substrate such as a portable electronic device or a semiconductor chip that is aimed at a light and small thickness.

The embodiment provides a printed circuit board having a new structure and a method of manufacturing the same.

The embodiment provides a printed circuit board including an odd number of circuit layers and a method of manufacturing the same.

An embodiment may include a core insulating layer, at least one via penetrating through the core insulating layer, an internal circuit layer embedded in the core insulating layer, a pattern groove formed on an upper or lower surface of the core insulating layer, and And an external circuit layer filling the pattern groove, wherein the via is positioned between the first part, the second part under the first part, and the first and second parts. A printed circuit board including a third part formed of a metal different from the metal is provided.

Meanwhile, in the method of manufacturing a printed circuit board according to the embodiment, preparing a metal substrate on which a first metal layer, a second metal layer, and a third metal layer are stacked, etching the first metal layer of the metal substrate to form a first via. Forming a part, etching the second metal layer of the metal substrate to form a connection portion and an inner circuit layer below the second part of the via, etching the third metal layer of the metal substrate to form a portion of the via Forming a second part under the connection part, forming an insulating layer filling the via, forming a pattern groove on a surface of the upper or lower portion of the insulating layer, and plating a conductive material to form the pattern groove Forming an external circuit layer to fill the.

According to the present invention, a process can be reduced by simultaneously forming an inner circuit layer and a via, and a thin and thin printed circuit board can be provided by forming an odd layer circuit layer.

In addition, by forming a buried via in the insulating layer of the multilayer printed circuit board, heat dissipation may be improved, and a cost may be reduced by not using a plating method when forming a buried via.

In addition, a fine pattern is realized by embedding the external circuit layer.

1 is a cross-sectional view of a printed circuit board according to the prior art.
2 is a cross-sectional view of a printed circuit board according to a first embodiment of the present invention.
3 to 15 are flowcharts for describing a method of manufacturing the printed circuit board of FIG. 2.
16 is a cross-sectional view of a printed circuit board according to a second embodiment of the present invention.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

Throughout the specification, when a part is said to "include" a certain component, it means that it can further include other components, without excluding other components unless specifically stated otherwise.

In order to clearly illustrate the present invention in the drawings, thicknesses are enlarged in order to clearly illustrate various layers and regions, and parts not related to the description are omitted, and like parts are denoted by similar reference numerals throughout the specification .

Whenever a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case where it is "directly on" another portion, but also the case where there is another portion in between. On the contrary, when a part is "just above" another part, there is no other part in the middle.

The present invention provides a printed circuit board having an odd number of circuit layers, which can form a multilayer circuit board without using a plating method by simultaneously etching the buried via and the internal circuit layer.

Hereinafter, a printed circuit board according to an exemplary embodiment of the present invention will be described with reference to FIGS. 2 to 15.

2 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention.

Referring to FIG. 2, the printed circuit board 100 according to the present invention includes a core insulating layer formed by the first insulating layer 120 and the second insulating layer 125, and vias formed in the core insulating layer. 115), an internal circuit layer 111 formed in the core insulating layer, and first and second external circuit layers 131 and 135 formed on the first and second insulating layers 120 and 125, respectively. , 145).

The first insulating layer 120 is formed on the second insulating layer 125, and may be formed through another insulating layer (not shown).

The first and second insulating layers 120 and 125 may be a thermosetting or thermoplastic polymer substrate, a ceramic substrate, or an organic-inorganic composite material substrate, and may include an epoxy-based insulating resin when the polymer resin is included. Alternatively, polyimide resins may be included. In addition, the material forming the first and second insulating layers 120 and 125 may be a resin material including a solid component such as glass fiber.

The first and second insulating layers 120 and 125 may be formed of the same material.

Each of the first insulating layer 120 and the second insulating layer 125 may have a thickness of about 30 μm to 80 μm .

The thickness of the core insulating layer, which is a laminated structure of the first insulating layer 120 and the second insulating layer 125, may be about 60 μm to 160 μm , preferably about 60 μm to 140 μm . Vias 115 and internal circuit layers 111 are formed in the core insulating layer.

The via 115 is a conductive via 115 penetrating from the first insulating layer 120 to the second insulating layer 125, and the first insulating layer 120 and the second insulating layer 125. The second width d2 of the cross section having the largest first width d1 in the boundary region and narrowing toward the upper surfaces of the insulating layers 120 and 125 to form the exposed surfaces of the insulating layers 120 and 125. ) Has the smallest width so that the cross section of via 115 may represent a hexagon.

The first width d1 and the second width d2 of the via 115 may satisfy about 20 μm to 100 μm .

The vias 115 may be formed of an alloy including copper as the conductive vias 115.

The via 115 is buried in the first insulating layer, and is formed under the first part 115a and the first part 115a formed of an alloy including copper, and the second insulating layer ( A second part 115b embedded in the second metal part 115b, and formed between the first part 115a and the second part 115b and embedded in the first metal part 115a. And the third part 115c formed of a metal different from the first and second parts 115a and 115b.

The third part 115c is formed in the central region of the via 115, and a lower surface of the third part 115c has a first width d1, which is the largest width of the via 115, and includes nickel and iron. , Cobalt, molybdenum, or chromium, and may be formed of an alloy including etch selectivity with the first and second parts 115a and 115b.

At this time, the thickness of the first part 115a and the second part 115b is 20 to 70 μm , and the thickness of the third part 115c satisfies 5 to 70 μm .

The inner circuit layer 111 is formed on the second insulating layer 125, and the thickness of the circuit pattern may be about 6 to 30 μm , a width of about 50 μm or less, preferably 30 μm or less. It is implemented in a fine pattern to have a width of.

The internal circuit layer 111 may have a rectangular cross section.

In this case, the internal circuit layer 111 is formed of the same material as the third part 115c of the via 115.

Pattern grooves 121 and 126 are formed on upper surfaces of the first and second insulating layers 125 to form via pads 135 and 145 and circuit patterns 131 connected to the vias 115. have.

The pattern grooves 121 and 126 are filled with external circuit layers 131, 135, and 145, respectively.

The external circuit layers 131, 135, and 145 fill the first external circuit layers 131, which fill the pattern grooves 121 and 126 formed on the first insulating layer 120, which is the upper portion of the core insulating layer. 135 and the second external circuit layer 145 which fills the pattern grooves 121 and 126 formed in the lower portion of the second insulating layer 125 which is the lower portion of the core insulating layer.

The external circuit layers 131, 135, and 145 may be formed as a single layer as illustrated in FIG. 2, but may be formed as a lower seed layer and an upper plating layer. The seed layer may be thinly formed along the side and bottom surfaces of the pattern grooves 121 and 126 and may be formed by, for example, electroless plating or sputtering.

In addition, the seed layer may be formed of an alloy containing copper, nickel, palladium, chromium and the like.

A plating layer electroplated on the seed layer and formed of an alloy including at least one of copper, silver, gold, nickel, and palladium is formed to fill the pattern grooves 121 and 126.

In this case, the pattern grooves 121 and 126 formed in the first and second insulating layers 120 and 125 may have a rectangular cross-sectional shape according to a manufacturing method, and are curved, preferably U-shaped. Can be.

In the above description, each of the external circuit layers 131, 135, and 145 embedded in the upper and lower parts of the core insulating layer is formed. However, the present invention is not limited thereto, and an upper insulating layer covering the external circuit layers 131, 135, and 145 is formed. Multi-layered circuit boards may be formed by forming the first and second insulating layers 120 and 125, respectively, and forming circuit layers on the upper insulating layers, respectively.

As described above, the printed circuit board 100 of the present invention can form a circuit layer having a number of 2n + 1 (n is a positive integer) by forming the internal circuit layer 111 embedded in the core insulating layer. The insulating layer is formed to have the same number based on the core insulating layer so that the printed circuit board does not bend to one side.

Therefore, an odd number of circuit layers can be formed without increasing the number of insulating layers, and heat dissipation is ensured by forming vias 115 formed of a conductive material in the core insulating layer.

In addition, a fine circuit pattern may be realized by forming a groove in the insulating layer and plating the outer circuit layer.

Hereinafter, a method of manufacturing the printed circuit board of FIG. 2 will be described with reference to FIGS. 3 to 15.

When the process starts, a conductive metal substrate 110 is prepared as shown in FIG. 3.

The metal substrate 110 may be formed of an alloy containing copper, the copper material may be used both a rolled foil, an electrolytic foil, the thickness of the metal substrate 110 varies in accordance with the specifications of the product required Can be used. In this case, the metal substrate 110 has a laminated structure of the first metal layer 110a, the second metal layer 110b, and the third metal layer 110c.

The first metal layer and the third metal layer 110a and 110c may have the same or similar thicknesses and may be formed of the same material.

The first and third metal layers 110a and 110c may be formed of an alloy layer including copper, and the second metal layer 110b formed between the first and third metal layers 110a and 110c may be formed of the first and third metal layers 110a and 110c. The third metal layers 110a and 110c are formed of different metals having etch selectivity.

The second metal layer 110b may be formed of an alloy including nickel, iron, cobalt, molybdenum, or chromium, and the thickness of the first metal layer and the second metal layers 110a and 110c is 20 to 70 μm, and the second The thickness of the metal layer 110b satisfies 5 to 70 μm.

In the present invention, the total thickness of the metal substrate 110 is preferably 80 μm to 170 μm. The substrate 110 of copper material cleans the surface by performing a surface cleaning operation including pickling and washing with water.

Next, as shown in FIG. 4, the photosensitive film 116 is attached onto the upper surface of the metal substrate 110.

The photosensitive film 116 is to form an etching pattern for etching the metal substrate 110, the thickness of the photosensitive film 116 varies from 15㎛ to 30㎛, both UV exposure type and LDI exposure type Available.

Next, as shown in FIG. 5, the photosensitive film 116 is exposed and developed to form a photosensitive pattern (not shown), and the metal substrate 110 is etched using a mask to etch the first part of the via 115. 115a).

A portion of the metal substrate 110 is wet etched by a wet etchant such as copper chloride or iron chloride to form a first part 115a of the via 115, and the first metal layer 110a and the second metal layer 110b are mutually etched. By the other etching selectivity, the first part 115a is formed by etching only the first metal layer 110a.

After etching the first part 115a and the internal circuit layer 111 of the via 115, the photosensitive pattern is peeled off using a NaOH diluent.

Next, as shown in FIG. 6, the photosensitive film 117 is formed on the entire surface of the first part 115a and the exposed second metal layer 110b.

In order to form the internal circuit layer 111 with the second metal layer 110b, a portion of the photosensitive film 117 on the second metal layer 110b is exposed and developed to form the photosensitive pattern 118 of FIG. 7. The second metal layer 110b is selectively etched using the photosensitive pattern 118 as a mask to form the third circuit 115c of the internal circuit layer 111 and the via 115.

In this case, the first part 115a of the via 115 functions as an etching mask of the third part 115c by the etching selectivity of the first metal layer 110a and the second metal layer 110b.

When the third metal layer 110c below the second metal layer 110b is exposed, etching stops to form the internal circuit layer 111, and the formed internal circuit layer 111 has a rectangular cross section.

Next, as shown in FIG. 8, the first insulating layer 120 is formed to fill the first and third parts 115a and the internal circuit layer 111 of the via 115.

The first insulating layer 120 is formed using a thermosetting or thermoplastic resin in which solid components such as glass fibers are not formed or formed, and the thickness of the first insulating layer 120 is about 30 μm to 80 μm. Can be.

Next, as shown in FIG. 9, a photosensitive film 136 is formed on the lower surface of the first insulating layer 120 and the metal substrate 110.

The photosensitive film 136 formed under the metal substrate 110 may be a matrix forming a photosensitive pattern for forming the second part 115b of the via 115 and the internal circuit layer 111. The photosensitive film 136 on the insulating layer 120 functions as a protective film for protecting the upper layer in the photosensitive pattern formation below the metal substrate 110 and the etching process of the metal substrate 110.

Therefore, the photosensitive film 136 on the first insulating layer 120 may be omitted.

Next, as shown in FIG. 10, the photosensitive film 136 under the metal substrate 110 is developed to form a photosensitive pattern, and the metal substrate 110 is etched using the photosensitive pattern as a mask to form the vias 115. The second part 115b is formed below the first part 115a.

As described above, the via 115 has an upper portion and a lower portion divided into first parts 115a to third parts 115b to be etched to have a first width d1 having the largest central shape. As it gets closer to, it has a hexagonal cross section that becomes narrower in width.

When the second part 115b of the via 115 is formed, the photosensitive pattern is peeled off, and as shown in FIG. 11, the second insulating layer 125 so that the second part 115b of the via 115 is buried. Laminated.

Next, as shown in FIG. 12, pattern grooves 121 and 126 are formed in the surfaces of the first and second insulating layers of the upper and lower parts.

The pattern grooves 121 and 126 may include via pad grooves exposing the vias and circuit pattern grooves 121 and 126 for filling circuit patterns.

In order to form the pattern grooves 121 and 126 in the first and second insulating layers, an excimer laser using a pattern mask and a UV-YAG laser that can be used without a mask may be used.

  When using an excimer laser, any one of XeCl (308 nm), KrF (248 nm), and ArF (193 nm) may be used as a source, and when the pattern grooves 121 and 126 are formed in the first and second insulating layers, the pattern grooves may be used. The cross sections of (121, 126) have a V-shaped or inverted square shape depending on the line / space and vibration depth of the circuit.

On the other hand, when using a UV-YAG laser, the cross section of the pattern grooves 121 and 126 has a curved shape, and preferably may be formed in a U shape.

Next, as shown in FIG. 13, plating layers 130 and 140 filling the pattern grooves 121 and 126 are formed.

In detail, electroless plating is performed to form seed layers on the entire surfaces of the first and second insulating layers 120 and 125. Before the seed layer is formed, a pretreatment such as a degreasing process, a soft etching process, a precatalyst process, a catalyst treatment process, and an activator process is performed. It can be formed by electroless plating.

On the other hand, sputtering for forming a copper metal layer on the insulating layers 120 and 125 by impinging the ion target (eg Ar +) of the gas generated by the plasma or the like to the copper target without performing electroless plating. Can also be used.

In addition, as the seed layer, a metal other than copper, for example, nickel-palladium alloy (Ni-Pd) or nickel-chromium alloy (Ni-Cr), may be formed by an electroless plating method or a sputtering method.

Electroplating is performed on the seed layer to fill the pattern grooves 121 and 126, and the conductive plating layers 130 and 140 are formed on the front surfaces of the first and second insulating layers 120 and 125.

The plating layers 130 and 140 may be formed of an alloy containing copper, silver, gold, nickel, or palladium, and preferably plate an alloy containing copper.

In the method of forming the electroplating layers 130 and 140, the substrate is eroded into the copper plating working chamber and then electrolytic copper plating is performed using a direct current or pulse rectifier. In such electrolytic plating, it is preferable to use a method of calculating copper to be plated by applying an appropriate current to a DC or pulse rectifier.

As described above, the plating layers 130 and 140 of FIG. 13 may be obtained by performing electroless plating and electroplating. Alternatively, the pattern grooves 121 and 126 may be filled by electroless plating of a conductive metal.

Next, as shown in FIG. 14, in order to remove unnecessary plating layers 130 and 140, all plating layers 130 and 140 and seed layers are removed until the surfaces of the first and second insulating layers 120 and 125 are exposed. do.

Thus, the buried external circuit layers 131, 135, and 145 formed only in the pattern grooves 121 and 126 are formed, and the plating layers 130 and 140 may be removed by flash etching, and the plating layer to be removed ( If the thickness of the 130 and 140 is large, a half etching process before the flash etching may be added as necessary.

Finally, as shown in FIG. 15, the process is completed by filling the circuit patterns 131 of the external circuit layers 131, 135, and 145 and forming the coverlay 150 to expose the pads 135 and 145. .

As described above, the via substrate is drilled to form a via hole, and the via hole is plated and embedded to form a via. Instead, the metal substrate 110 is etched to form a via 115, and the via 115 is buried. By forming the insulating layers 120 and 125, the manufacturing cost is reduced, and the manufacturing step is reduced by forming the internal circuit layer 111 on the same metal substrate as the vias 115.

Hereinafter, a printed circuit board according to a second exemplary embodiment of the present invention will be described with reference to FIG. 16.

Referring to FIG. 16, the printed circuit board 200 according to the present invention includes a core insulating layer formed by the first insulating layer 120 and the second insulating layer 125, and vias formed in the core insulating layer. 115), an internal circuit layer 112 formed in the core insulating layer, and first and second external circuit layers 131 and 135 formed in the first and second insulating layers 120 and 125, respectively. , 145).

The first insulating layer 120 is formed on the second insulating layer 125, and may be formed through another insulating layer therebetween.

The material forming the first and second insulating layers 120 and 125 may be a resin material including a solid component such as glass fiber, and the first and second insulating layers 120 and 125 may be formed of the same material. Can be.

The stacked structure of the first insulating layer 120 and the second insulating layer 125 forms a core insulating layer, and the thickness of the core insulating layer may be about 60 μm to 140 μm . Vias 115 and internal circuit layers 112 are formed in the core insulating layer.

The via 115 is a conductive via 115 penetrating from the first insulating layer 120 to the second insulating layer 125, and the first insulating layer 120 and the second insulating layer 125. It has the largest width in the boundary region, and the width becomes narrower toward the upper surface of each insulating layer, so that the cross section may exhibit a hexagon.

The first width d1 and the second width d2 of the via 115 may satisfy about 20 μm to 100 μm .

The vias 115 may be formed of an alloy including copper as the conductive vias 115.

The via 115 is buried in the first insulating layer 120, and is formed under the first part 115a and the first part 115a, which is formed of an alloy including copper, and the second part. It is embedded in the insulating layer 125, and is formed between the second part 115b formed of the same metal as the first part 115a, and between the first part 115a and the second part 115b. And a third part 115c formed of a metal different from the first and second parts 115a and 115b.

The third part 115c is formed in the central region of the via 115, and a lower surface of the third part 115c has a first width d1, which is the largest width of the via 115, and includes nickel and iron. , Cobalt, molybdenum, or chromium, and may be formed of an alloy including etch selectivity with the first and second parts 115a and 115b.

At this time, the thickness of the first part 115a and the second part 115b is 20 to 70 μm , and the thickness of the third part 115c satisfies 5 to 70 μm .

The inner circuit layer 112 may have a rectangular cross section and may be formed in a fine pattern having a width of about 60 μm or less, preferably 50 μm or less.

In this case, the internal circuit layer 112 is formed of the same material as the third part 115c of the via 115.

Pattern grooves 121 and 126 are formed on upper surfaces of the first and second insulating layers 125 to form via pads 135 and 145 and circuit patterns 131 connected to the vias 115. have.

The pattern grooves 121 and 126 are filled with external circuit layers 131, 135, and 145, respectively.

The external circuit layers 131, 135, and 145 fill the first external circuit layers 131, which fill the pattern grooves 121 and 126 formed on the first insulating layer 120, which is the upper portion of the core insulating layer. 135 and the second external circuit layer 145 which fills the pattern grooves 121 and 126 formed in the lower portion of the second insulating layer 125 which is the lower portion of the core insulating layer.

The external circuit layers 131, 135, and 145 may be formed as a single layer as illustrated in FIG. 2, but may be formed as a lower seed layer and an upper plating layer. The seed layer may be thinly formed along the side and bottom surfaces of the pattern grooves 121 and 126 and may be formed by, for example, electroless plating or sputtering.

In addition, the seed layer may be formed of an alloy containing copper, nickel, palladium, chromium and the like.

A plating layer electroplated on the seed layer and formed of an alloy including at least one of copper, silver, gold, nickel, and palladium is formed to fill the pattern grooves 121 and 126.

In this case, the pattern grooves 121 and 126 formed in the first and second insulating layers 120 and 125 may have a rectangular cross-sectional shape according to a manufacturing method, and are curved, preferably U-shaped. Can be.

In the printed circuit board 200 of FIG. 16, the circuit pattern of the internal circuit layer 112 has a polygonal cross section and borders the first and second insulating layers 120 and 125 like the via 115. It may be a polygon formed symmetrically in the axis, preferably square or hexagon. In other words, a portion of the internal circuit layer 112 may be embedded in the first insulating layer 120, and the rest of the internal circuit layer 112 may be embedded in the second insulating layer 125.

Even when the internal circuit layer 112 is formed as shown in FIG. 16, it may be formed using the manufacturing method of FIGS. 3 to 15, and the second part 115b of the via 115 in the processes of FIGS. 9 and 10. When forming, regions to be buried in the second insulating layer 125 of the internal circuit layer 112 may be formed together.

As described above, the printed circuit board 200 of the present invention can form a circuit layer having a number of 2n + 1 (n is a positive integer) by forming the internal circuit layer 112 embedded in the core insulating layer. The insulating layer is formed with the same number based on the core insulating layer so that the printed circuit board does not bend to one side.

Therefore, an odd number of circuit layers can be formed without increasing the number of insulating layers, and heat dissipation is ensured by forming vias 115 formed of a conductive material in the core insulating layer.

In addition, the bending of the metal substrate is prevented in the process by forming the intermediate layer of the metal from each other.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

Printed Circuit Board 100, 200
Via 115
Internal circuitry 111
First Insulation Layer 120
Second Insulation Layer 125

Claims (18)

Core insulation layer,
At least one via penetrating the core insulating layer,
An internal circuit layer embedded in the core insulating layer,
A pattern groove formed on an upper surface or a lower surface of the core insulating layer, and
An external circuit layer filling the pattern groove
/ RTI >
The via includes a first part, a second part below the first part, and a third part disposed between the first and second parts and formed of a metal different from the metal of the first and second parts. Circuit board. The method of claim 1,
The core insulating layer comprises a first insulating layer filling the first and third parts of the via, and
And a second insulating layer filling the second part of the via under the first insulating layer. The method of claim 2,
The inner circuit layer is formed of the same material as the third part of the via. The method of claim 1,
The first part and the second part of the via are formed of the same material. The method of claim 1,
The inner circuit layer is a printed circuit board having a rectangular cross section. The method of claim 2,
And the inner circuit layer is embedded in the first insulating layer. The method of claim 1,
The printed circuit board
A printed circuit board comprising a circuit layer having a number of 2n + 1 (n is a positive integer) including the inner circuit layer and the outer circuit layer. The method of claim 1,
Printed circuit board has a U-shaped cross section of the pattern groove. Preparing a metal substrate on which a first metal layer, a second metal layer, and a third metal layer are stacked;
Etching the first metal layer of the metal substrate to form a first part of a via,
Etching the second metal layer of the metal substrate to form a connection portion and an internal circuit layer under the second part of the via;
Etching the third metal layer of the metal substrate to form a second part under the connection portion of the via;
Forming an insulating layer filling the via;
Forming a pattern groove on a surface of the upper or lower portion of the insulating layer, and
Plating an conductive material to form an external circuit layer filling the pattern groove
And a step of forming the printed circuit board. 10. The method of claim 9,
Wherein forming the insulating layer comprises:
Forming a first insulating layer filling the first part of the via, the connecting portion, and the internal circuit layer; and
And forming a second insulating layer filling the second part of the via. 10. The method of claim 9,
Preparing the metal substrate,
The method of claim 1, wherein the first to third metal layers are formed of metals having different etching selectivities. 10. The method of claim 9,
Forming the external circuit layer,
Forming the pattern groove on the upper or lower surface of the insulating layer by using a laser;
Electroless plating along the surface of the pattern groove to form a seed layer, and
And embedding the pattern groove by electroplating the conductive material on the seed layer. 10. The method of claim 9,
And a width of an interface between the first part and the second part of the via is greater than a width of the interface between the insulating layer and the insulating layer. 10. The method of claim 9,
And a width of an interface between the second part and the third part of the via is greater than a width of the interface between the insulating layer and the insulating layer. 10. The method of claim 9,
Forming the second part of the via,
And wet etching the lower portion of the metal substrate to form a second part of the via and simultaneously form a lower portion of the internal circuit layer. 10. The method of claim 9,
The inner circuit layer is a width of 50 μm or less manufacturing method of a printed circuit board. 10. The method of claim 9,
Forming the pattern groove,
A method of manufacturing a printed circuit board using the excimer laser to form the pattern groove on the surface of the insulating layer. 10. The method of claim 9,
Forming the pattern groove,
Method of manufacturing a printed circuit board to form the pattern groove on the surface of the insulating layer using a UV-YAG laser.

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