KR20020049729A - Method for manufacturing BGA substrate having via hole - Google Patents

Method for manufacturing BGA substrate having via hole Download PDF

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Publication number
KR20020049729A
KR20020049729A KR1020000078996A KR20000078996A KR20020049729A KR 20020049729 A KR20020049729 A KR 20020049729A KR 1020000078996 A KR1020000078996 A KR 1020000078996A KR 20000078996 A KR20000078996 A KR 20000078996A KR 20020049729 A KR20020049729 A KR 20020049729A
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South Korea
Prior art keywords
adhesive
insulating member
conductive foil
substrate
via hole
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KR1020000078996A
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Korean (ko)
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최문환
박성우
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김 무
주식회사 아큐텍반도체기술
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Priority to KR1020000078996A priority Critical patent/KR20020049729A/en
Publication of KR20020049729A publication Critical patent/KR20020049729A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: A method for fabricating a substrate for a ball grid array(BGA) semiconductor package is provided to reduce fabricating cost and to improve yield, by chemically etching an insulation film and adhesive to form a via hole. CONSTITUTION: The adhesive(12) is coated on an outer surface of an insulation member(11) constituting a base. A conductive film(14) is laminated on the adhesive. Photoresist is applied on the conductive film at the side of the adhesive and on both surfaces of the insulation member. An exposure and developing process is performed regarding both resist by using an exposure apparatus. The conductive film and the insulation member are sequentially etched to form an interconnection pattern and a solder ball mounting region. The adhesive and the photoresist are delaminated. A via hole and an interconnection pattern are formed in the insulation member.

Description

비지에이 반도체 패키지용 기판 제조 방법{Method for manufacturing BGA substrate having via hole}Method for manufacturing BGA substrate having via hole}

본 발명은 반도체 BGA패키지 중 유연성 기질재료(flexible substrate)를 제조하는 방법에 관한 것으로서, 보다 상세하게는, 가요성 BGA 기판(flexible BGA substrate)을 제조함에 있어, 절연체 필름 및 접착제를 화학적으로 식각하는 방법을 이용하여 비아홀(via hole)을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a flexible substrate in a semiconductor BGA package. More particularly, the present invention relates to chemically etching an insulator film and an adhesive in manufacturing a flexible BGA substrate. It relates to a method of forming via holes using the method.

일반적으로, BGA 기판은 2층(Cu/PI) 또는 3층(Cu/adh./PI) 구조로 되어 있는데 배선 패턴(bonding land)과 솔더 볼 장착 영역(ball land) 의 전도를 위해 비아홀을 형성한다(여기에서, 2층은 구리 및 폴리이미드이고, 3층은 그 중간에 접합제가 개재된 것을 의미).In general, BGA substrates have a two-layer (Cu / PI) or three-layer (Cu / adh. / PI) structure, which forms via holes for conducting bonding patterns and solder ball lands. (In this case, two layers are copper and polyimide, and three layers mean that a binder is interposed in the middle).

종래의 BGA용 배선 부재의 제조 방법에 있어서는, 폴리이미드 부재 등 절연 부재에 블라인드 비아홀을 형성하는 방식으로, 금형 펀치법이 주로 사용되고 있었다.In the conventional manufacturing method of the wiring member for BGA, the metal mold | die punch method was mainly used by the method of forming a blind via hole in insulation members, such as a polyimide member.

도1은 금형 펀치법을 이용한 종래의 BGA용 배선 부재의 제조 방법을 예시하고 있다. 금형 펀치 기법에 의하면, 폴리이미드 부재 등의 절연 부재(11)의 한쪽면에 접착제(12)를 피복하고(S101), 이어서, 접착제(12)를 갖는 절연 부재(11)에 금형펀치로 관통홀(13)을 형성하고(S102), 그 후, 접착제(12) 쪽에 동박 등의 도전박(14)을 피복하여 관통홀(13)의 한 쪽을 막고, 블라인드 비아홀(15)을 형성한다(S103).Fig. 1 illustrates a conventional method for producing a wiring member for BGA using the die punch method. According to the die punch technique, an adhesive 12 is coated on one surface of an insulating member 11 such as a polyimide member (S101), and then through a hole punch in the insulating member 11 having the adhesive 12 with a mold punch. (13) is formed (S102), and then the conductive foil 14 such as copper foil is coated on the adhesive 12 to block one side of the through hole 13, thereby forming a blind via hole 15 (S103). ).

이어서, 접착제(12) 쪽의 도전박(14)에 감광성 레지스트를 도포하고, 노광기로 노광하여 알칼리 현상한 후, 식각하여 소정의 패턴(21) 및 비아홀 랜드(22)를 형성한다. 그 다음, 절연을 위한 배선 패턴에 포토 솔더레지스트를 도포하여 배선패턴(21)을 보호하고, 비아홀 랜드(22)의 뒷면에 금도금(21)을 실시하여 BGA용 배선 부재(18)를 제조한다. 이와같이 하여 제조된 BGA용 배선 부재(18)의 블라인드 비아홀(15)에 리플로우 노(爐)에 의하여 솔더볼(17)을 형성하여 BGA용 배선 부재(18)가 프린트 기판 등과 접속할 수 있도록 구성한다(S104).Next, the photosensitive resist is apply | coated to the electrically conductive foil 14 of the adhesive agent 12 side, and it exposes by an exposure machine, alkali-develops, and then etches to form the predetermined pattern 21 and the via hole land 22. Next, a photo solder resist is applied to the wiring pattern for insulation to protect the wiring pattern 21, and gold plating 21 is applied to the back surface of the via hole land 22 to manufacture the wiring member 18 for BGA. The solder ball 17 is formed in the blind via hole 15 of the BGA wiring member 18 thus manufactured by a reflow furnace so that the BGA wiring member 18 can be connected to a printed board or the like ( S104).

상기한 바와 같이, 2층의 경우에는, 절연체 필름위에 구리 씨앗층(Cu seed layer)을 형성한 후 전기도금으로 구리층을 형성시키고, 절연체 필름을 화학적으로 식각하여 비아홀을 형성한다.As described above, in the case of two layers, a copper seed layer is formed on the insulator film, and then a copper layer is formed by electroplating, and the insulator film is chemically etched to form via holes.

또, 3층의 경우처럼 접합제층(adhesive layer)이 있는 경우 펀칭(punching)을 하거나 레이저 가공(laser drilling) 기법을 사용해 비아홀을 형성한 후, 접착제층을 이용해 구리층과 라미네이션(lamination) 시키고 있다. 그러나 이러한 방법들은 2층 구조를 제조할 경우, 구리 씨앗층(Cu seed layer)을 형성하기 위해 CVD 또는 PVD 등의 고가의 장비로 인한 초기 비용이 많이 소요되고, 다양한 구리합금을 사용하는데 제약이 있어왔다.In addition, as in the case of the three layers, if an adhesive layer is present, via holes are formed by punching or laser drilling, and then laminated with a copper layer using an adhesive layer. . However, these methods have a high initial cost due to expensive equipment such as CVD or PVD to form a copper seed layer when manufacturing a two-layer structure, and there are limitations in using various copper alloys. come.

또한, 3층 구조 제조의 경우에도 펀칭 공구(punching tool)의 잦은 교체로 인한 비용의 증가가 상당하고 펀칭 시 발생되는 찌끼(burr)로 인한 불량률이 높은 단점이 있고 좁은 피치를 갖는 제품의 경우 레이저 가공을 해야 하는데 이는 새로운 공정(desmear 등)의 추가를 가져오는 등의 단점을 내포하고 있었다.In addition, even in the case of manufacturing a three-layer structure, the cost increase due to frequent replacement of the punching tool is considerable, and the defect rate due to the burrs generated during punching is high. Machining must be done, which has the disadvantages of adding new processes (desmear, etc.).

따라서, 본 발명은 상술한 문제점을 감안하여 이루어진 것으로서, 본 발명의 목적은 반도체 BGA패키지 중 유연성 기질재료(substrate)를 제조하는 기법에서의 접착제를 포함하는 3층 구조를 갖는 BGA 기판을 제조함에 있어, 절연체 필름 및 접착제를 화학적으로 식각하는 방법을 이용하여 비아홀을 형성함으로써, 이를 통해 생산 비용을 절감하고 생산 수율을 향상시킬 수 있는 BGA 반도체 패키지용 기판 제조 방법을 제공함에 있다.Accordingly, the present invention has been made in view of the above-described problems, and an object of the present invention is to manufacture a BGA substrate having a three-layer structure including an adhesive in a technique for manufacturing a flexible substrate material in a semiconductor BGA package. By forming a via hole using a method of chemically etching the insulator film and the adhesive, thereby providing a method for manufacturing a substrate for a BGA semiconductor package that can reduce the production cost and improve the production yield.

이와 같은 목적을 달성하기 위하여 본 발명에 의한 BGA 반도체 패키지용 기판 제조방법은, BGA 반도체 패키지용 기판 제조 방법에 있어서,In order to achieve the above object, the BGA semiconductor package substrate manufacturing method according to the present invention is a BGA semiconductor package substrate manufacturing method,

상기한 절연 부재의 한쪽 외측면에 접착제를 피복하는 단계;Coating an adhesive on one outer side of the insulating member;

상기한 접착제 피복면 상에 도전박을 라미네이트시키는 단계;Laminating the conductive foil on the adhesive coated surface;

상기한 접착제 쪽의 도전박과 절연부재 양면에 감광성 레지스트를 도포하는 단계;Coating a photosensitive resist on both sides of the conductive foil and the insulating member toward the adhesive;

상기 레지스트를 노광기로 노광 현상 후 도전박과 절연 부재를 순차로 식각하여 배선 패턴과 솔더볼 장착 영역을 형성하는 단계; 및Forming an interconnection pattern and a solder ball mounting region by sequentially etching the resist with an exposure machine and then etching the conductive foil and the insulating member in sequence; And

상기 접착제와 감광성 레지스트를 박리하는 단계를 포함하는 것을 특징으로 하는 절연 부재에 비아홀을 형성함과 아울러 상기한 절연 부재의 적어도 한쪽 면에 소정의 배선 패턴을 설치하여 BGA 반도체 패키지용 기판을 이루는 것을 특징으로 한다.Peeling the adhesive and the photosensitive resist, and forming a via hole in at least one surface of the insulating member and forming a substrate for a BGA semiconductor package. It is done.

이하, 본 발명의 일실시예에 관하여 첨부한 도면을 참조하여 상세하게 설명한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

본 발명은 상기의 목적을 달성하기 위하여, 구리를 절연체와 접착제를 이용해 라미네이션시키고 구리와 절연체의 일면위에 포토레지스트를 양면 도포하여 감광, 현상시킨 후 구리를 식각하여 일정 패턴을 갖는 구리층을 형성시켜 배선 패턴을 형성시키는 공정과 폴리이미드와 접착제층을 화학적 식각하여 솔더볼 장착 영역을 형성하는 공정을 포함한다. 이후, 포토 레지스트를 박리하고 니켈등의 적절한 확산 방지층과 금 이나 금 합금 또는 팔라듐 이나 팔라듐 합금 또는 은 이나 은 합금층등의 산화 방지 및 솔더 볼 장착을 용이하게 하는 금속층을 형성한다.In order to achieve the above object, the present invention is to laminate copper using an insulator and an adhesive, and to apply photoresist on both sides of the copper and the insulator to photosensitive and develop the copper layer to form a copper layer having a predetermined pattern. And forming a solder ball mounting region by chemically etching the polyimide and the adhesive layer. The photoresist is then peeled off to form a suitable diffusion barrier layer such as nickel and a metal layer that facilitates oxidation prevention and solder ball mounting, such as gold or gold alloys or palladium or palladium alloys or silver or silver alloy layers.

본 발명에서 절연체로는 UBE사의 Upilex 계열, DuPont사의 Kapton 계열, Allied chemical사의 Apical, Novax, BT-epoxy, glass epoxy 등을, 구리로는 ED(electrodeposit) 또는 RA(rolled & annealed) 구리를 사용한다.In the present invention, the insulator is Uile's Upilex series, DuPont's Kapton series, Allied Chemical's Apical, Novax, BT-epoxy, glass epoxy, etc., and copper is used as ED (electrodeposit) or RA (rolled & annealed) copper. .

도 1은 종래의 금형 펀치 기법을 활용한 BGA용 기판 제조 공정도,1 is a BGA substrate manufacturing process using the conventional mold punching method,

도 2는 본 발명의 일 실시예에 따른 에칭 기법을 활용한 기판 제조 공정도.Figure 2 is a substrate manufacturing process using the etching technique in accordance with an embodiment of the present invention.

도 3는 본 발명의 다른 실시예에 따른 에칭 기법을 활용한 기판 제조 공정도.Figure 3 is a substrate manufacturing process utilizing the etching technique in accordance with another embodiment of the present invention.

< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>

11 : 절연부재 12 : 접착제11 insulation member 12 adhesive

13 : 관통공 14 : 도전박13: through hole 14: conductive foil

15 : 비아홀 21 : 배선 패턴15: via hole 21: wiring pattern

이하 본 발명을 아래의 실시예를 통해 설명하고자 하나, 본 발명이 아래 실시예에 국한 된 것은 아니다.Hereinafter, the present invention will be described through the following examples, but the present invention is not limited to the following examples.

〔실시예 1〕EXAMPLE 1

도 2에 도시된 바와 같이, 50㎛ 두께의 폴리이미드 필름 상부면에 12㎛ 두께의 접착제가 붙어있는 원자재 위에 18㎛ 두께의 ED Cu(전기동)를 라미네이션시키고 큐어링(curing)시킨다.As shown in FIG. 2, 18 μm thick ED Cu (electrophoretic) is laminated and cured on a raw material having a 12 μm thick adhesive attached to a 50 μm thick polyimide film upper surface.

다음에, 구리와 폴리이미드 일면에 포토레지스트를 양면 도포하고 감광한 후 현상하여 일정 패턴을 형성한다.Next, photoresist is coated on both sides of copper and polyimide, photosensitive, and then developed to form a predetermined pattern.

또, 이어서 구리를 식각하고 폴리이미드와 접착제층을 화학적으로 제거하여 배선 배턴과 솔더 볼 장착 영역을 형성시킨다.The copper is then etched and the polyimide and adhesive layer chemically removed to form the wiring baton and solder ball mounting area.

이후, 포토레지스트를 박리한 후 적절한 전처리를 거쳐 니켈도금을 하고 금이나 팔라듐 또는 금 합금이나 팔라듐 합금 도금을 실시하여 배선에 대한 본딩과 솔더 볼 접착에 유리한 도금층을 형성시킨다.Thereafter, after the photoresist is peeled off, nickel plating is performed through appropriate pretreatment, and gold, palladium, gold alloy, or palladium alloy plating is performed to form a plating layer advantageous for bonding to the wiring and bonding of solder balls.

〔실시예 2〕EXAMPLE 2

실시예 1의 원자재 위에 18㎛두께의 전기동을 라미네이션 시키고 큐어링한다.The copper of 18 micrometers thick is laminated and cured on the raw material of Example 1.

다음에, 구리의 상부면에 포토레지스트를 도포하고 감광, 현상 후 구리를 식각하여 배선 패턴을 형성한다.Next, a photoresist is applied to the upper surface of copper, and copper is etched after photosensitive and developing to form a wiring pattern.

또, 폴리이미드 일면위에 포토레지스트를 도포하고 감광, 현상후 폴리이미드로 이루어진 절연부재를 식각한다.In addition, a photoresist is applied on one surface of the polyimide, and the insulating member made of polyimide is etched after photosensitive and developing.

이후, 접착제를 제거하고 포토 레지스트 박리 후, 적절한 전처리를 거쳐 니켈 도금후 금 도금을 실시한다.Thereafter, the adhesive is removed, the photoresist is peeled off, and then the nickel plating is performed after nickel plating through appropriate pretreatment.

여기에서, 폴리이미드 식각 후 구리면쪽의 접착제를 보호하기 위해 백코팅(back coating)을 실시해도 된다.Here, in order to protect the adhesive on the copper surface after polyimide etching, you may perform back coating.

〔실시예 3〕EXAMPLE 3

50㎛ 두께의 폴리이미드 필름 상부면에 12㎛ 두께의 접착제가 붙어있는 원자재 위에 36㎛두께의 RA Cu(어닐링 구리)를 라미네이션시키고 큐어링시킨다.A 36 μm thick RA Cu (annealed copper) is laminated and cured on a raw material having a 12 μm thick adhesive attached to a 50 μm thick polyimide film top surface.

다음에, 구리와 폴리이미드 일면에 포토레지스트를 양면 도포하고 감광한 후 현상하여 일정 패턴을 형성한다.Next, photoresist is coated on both sides of copper and polyimide, photosensitive, and then developed to form a predetermined pattern.

또, 구리를 식각하고 폴리이미드와 접착제층을 화학적으로 제거하여 배선 패턴과 솔더 볼 장착 영역을 형성시킨다.In addition, copper is etched and the polyimide and the adhesive layer are chemically removed to form wiring patterns and solder ball mounting regions.

이후, 포토레지스트를 박리한 후 적절한 전처리를 거쳐 니켈도금을 하고 금이나 팔라듐 또는 금 합금이나 팔라듐 합금 도금을 실시하여 배선에 대한 본딩과 솔더 볼 접착에 유리한 도금층을 형성시킨다.Thereafter, after the photoresist is peeled off, nickel plating is performed through appropriate pretreatment, and gold, palladium, gold alloy, or palladium alloy plating is performed to form a plating layer advantageous for bonding to the wiring and bonding of solder balls.

이하, 상기한 실시예들을 자세히 설명한다.Hereinafter, the above embodiments will be described in detail.

먼저, 도 2에 도시된 바와 같이, 본 발명의 일실시예에서는, 기질을 이루는 절연 부재의 한쪽 외측면에 접착제를 피복하고, 이 접착제 피복면 상에 도전박을 라미네이트시킨다(S301).First, as shown in FIG. 2, in one embodiment of the present invention, an adhesive is coated on one outer surface of the insulating member forming a substrate, and a conductive foil is laminated on the adhesive coated surface (S301).

또, 상기한 접착제 쪽의 도전박과 절연부재 양면에 감광성 레지스트를 도포하고, 상기 양쪽 레지스트를 노광기로 노광 현상한다(S302).Moreover, photosensitive resist is apply | coated to both surfaces of the said electrically conductive foil and the insulating member of the said adhesive agent side, and both said resists are exposed and developed by the exposure machine (S302).

또한, 상기 도전박과 절연 부재를 순차로 식각하여 배선 패턴과 솔더볼 장착 영역을 형성한다(S303).In addition, the conductive foil and the insulating member are sequentially etched to form a wiring pattern and a solder ball mounting region (S303).

또, 상기 접착제와 감광성 레지스트를 박리한다(S304).In addition, the adhesive and the photosensitive resist are peeled off (S304).

이로써, 기판에 대하여 배선 패턴과 솔더볼 장착 영역을 형성하게 된다.As a result, the wiring pattern and the solder ball mounting region are formed on the substrate.

한편, 본 발명의 다른 실시예에서는, 도 3에 도시된 바와 같이, 기질을 이루는 절연 부재의 한쪽 외측면에 접착제를 피복하고, 이 접착제 피복면 상에 도전박을 라미네이트시킨 후, 이 도전박 상에 감광성 레지스트를 도포한다(S501).On the other hand, in another embodiment of the present invention, as shown in Fig. 3, an adhesive is coated on one outer surface of the insulating member forming a substrate, and the conductive foil is laminated on the adhesive coated surface, and then the conductive foil phase A photosensitive resist is applied to the film (S501).

이어서, 상기 도전박 쪽의 레지스트를 노광기로 노광 현상한 후 도전박과 레지스트를 식각한다(S502).Subsequently, after exposing and developing the resist of the said conductive foil side by an exposure machine, an electrically conductive foil and a resist are etched (S502).

이로써, 기판에 대하여 배선 패턴을 형성하게 된다(S503).As a result, a wiring pattern is formed on the substrate (S503).

또, 상기 절연 부재의 다른 한쪽 외측면에 감광성 레지스트를 도포한다(S504).Moreover, a photosensitive resist is apply | coated to the other outer side surface of the said insulating member (S504).

다음에, 상기 절연부재 쪽의 감광성 레지스트를 노광 현상 후 절연부재와 접착제를 식각한다(S505).Next, after the exposure development of the photosensitive resist on the insulating member side, the insulating member and the adhesive are etched (S505).

이때, 도전박 쪽의 노출된 접착제도 함께 식각된다.At this time, the exposed adhesive on the conductive foil side is also etched.

이로써, 기판에 대하여 솔더볼 장착 영역을 형성하게 된다(S506).As a result, a solder ball mounting region is formed on the substrate (S506).

한편, 도 3에 도시된 바와, 상기한 실시예들에서, 폴리이미드 등의 접합부재의 노광 현상 단계 이후, 구리와 같은 도전박 쪽의 접착제를 보호하기 위해 백코팅(back coating)을 실시해도 좋다(S505').Meanwhile, as shown in FIG. 3, in the above embodiments, after the exposure development step of the bonding member such as polyimide, back coating may be performed to protect the adhesive on the conductive foil side such as copper. (S505 ').

이와 같이, 백 코팅을 실시한 후, 기판을 에칭하게 되면, 도전박 쪽의 접착제는 그대로 남고 백 코팅부와 절연부재 쪽의 감광성 레지스트가 박리되게 된다(S506').As described above, when the substrate is etched after the back coating, the adhesive on the conductive foil side remains as it is and the photosensitive resist on the back coating portion and the insulating member side is peeled off (S506 ').

따라서, 상기한 실시예들에 의하면, 3층 구조 제조의 경우에도 잦은 펀칭 공구(punching tool) 교체로 인한 비용의 증가를 규제할 수 있음과 아울러, 펀칭 시 발생되는 찌끼(burr)로 인해 불량화되는 것을 방지하여 신뢰성의 증대를 도모할 수 있게 되는 것이다.Therefore, according to the embodiments described above, even in the case of manufacturing the three-layer structure, it is possible to regulate the increase in the cost due to the frequent punching tool replacement, and also the defect caused by the burrs generated during the punching. It is possible to prevent increase in reliability and to increase reliability.

앞에서 설명한 바와 같이 본 발명에 의한 반도체 기판 제조 기법에 의하면, 절연체 필름 및 접착제를 화학적으로 식각하는 기법을 이용하여 비아홀을 형성함으로써, 이를 통해 생산 비용을 절감하고 생산 수율을 향상시킬 수 있는 BGA 반도체 패키지용 기판 제조 방법을 제공하는 등의 매우 뛰어난 효과가 있다.As described above, according to the method of manufacturing a semiconductor substrate according to the present invention, a via hole is formed by using a method of chemically etching an insulator film and an adhesive, thereby reducing a production cost and improving a production yield. There is an excellent effect such as providing a method for producing a substrate for use.

Claims (3)

BGA 반도체 패키지용 기판 제조 방법에 있어서, 기질을 이루는 절연 부재의 한쪽 외측면에 접착제를 피복하고, 이 접착제 피복면 상에 도전박을 라미네이트시키는 단계와,A method of manufacturing a substrate for a BGA semiconductor package, comprising: coating an adhesive on one outer surface of an insulating member forming a substrate, and laminating a conductive foil on the adhesive coated surface; 상기한 접착제 쪽의 도전박과 절연부재 양면에 감광성 레지스트를 도포하고, 상기 양쪽 레지스트를 노광기로 노광 현상하는 단계와,Applying a photosensitive resist on both sides of the conductive foil on the adhesive side and the insulating member, and exposing and developing both resists with an exposure apparatus; 상기 도전박과 절연 부재를 순차로 식각하여 배선 패턴과 솔더볼 장착 영역을 형성하는 단계와,Sequentially etching the conductive foil and the insulating member to form a wiring pattern and a solder ball mounting region; 상기 접착제와 감광성 레지스트를 박리하는 단계를 포함하여, 절연 부재에 비아홀 및 배선 패턴을 형성하는 것을 특징으로 하는 BGA 반도체 패키지용 기판 제조방법.Peeling the adhesive and the photosensitive resist, Forming a via hole and a wiring pattern in the insulating member, characterized in that the substrate manufacturing method for a BGA semiconductor package. 기질을 이루는 절연 부재의 한쪽 외측면에 접착제를 피복하고, 이 접착제 피복면 상에 도전박을 라미네이트시킨 후, 이 도전박 상에 감광성 레지스트를 도포하는 단계;Coating an adhesive on one outer side of the insulating member constituting the substrate, laminating the conductive foil on the adhesive coated surface, and then applying a photosensitive resist onto the conductive foil; 상기 도전박 쪽의 레지스트를 노광기로 노광 현상한 후 도전박과 레지스트를 식각하여 배선 패턴을 형성하는 단계;Exposing and developing the resist on the conductive foil side using an exposure apparatus to form a wiring pattern by etching the conductive foil and the resist; 상기 절연 부재의 다른 한쪽 외측면에 감광성 레지스트를 도포하는 단계; 및Applying a photosensitive resist to the other outer side surface of the insulating member; And 상기 절연부재 쪽의 감광성 레지스트를 노광 현상 후 절연부재와 접착제를식각하여 솔더볼 장착 영역을 형성하는 단계;Forming a solder ball mounting region by etching the insulating member and the adhesive after developing the photosensitive resist on the insulating member; 를 포함하여, 절연 부재에 비아홀 및 배선 패턴을 형성하는 것을 특징으로 하는 BGA 반도체 패키지용 기판 제조방법.A method of manufacturing a substrate for a BGA semiconductor package comprising: forming a via hole and a wiring pattern in an insulating member. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기한 접합제의 노광 현상 단계 이후, 상기 식각 공정에서의 도전박 쪽의 접착제 보호를 위해 백코팅을 실시하는 단계를 추가로 포함하는 것을 특징으로 하는 BGA 반도체 패키지용 기판 제조방법.After the exposure development step of the bonding agent, further comprising the step of performing a back coating to protect the adhesive on the conductive foil side in the etching process.
KR1020000078996A 2000-12-20 2000-12-20 Method for manufacturing BGA substrate having via hole KR20020049729A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040015953A (en) * 2002-08-14 2004-02-21 삼성테크윈 주식회사 Film substrate for semiconductor package and method for manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040015953A (en) * 2002-08-14 2004-02-21 삼성테크윈 주식회사 Film substrate for semiconductor package and method for manufacturing the same

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