KR101231343B1 - The printed circuit board and the method for manufacturing the same - Google Patents

Abstract

The present invention relates to a printed circuit board, wherein the substrate includes a core insulating layer, at least one via penetrating through the core insulating layer, an internal circuit layer embedded in the core insulating layer, and an upper or lower portion of the core insulating layer. An adhesive layer exposing the via, and an external circuit layer formed on the adhesive layer, wherein the via includes a first part, a second part below the first part, and the first and second parts. And at least one barrier layer formed between the third part and the first to third parts, and formed of a metal different from the first to third parts. Therefore, the process can be reduced by forming the inner circuit layer and the via at the same time, and by providing the circuit layer of the odd layer, it is possible to provide a light and thin printed circuit board.

Description

[0001] The present invention relates to a printed circuit board and a method of manufacturing the same,

The present invention relates to a printed circuit board and a method of manufacturing the same.

Printed Circuit Boards (PCBs) are like copper on electrically insulating substrates.

Is formed by printing a circuit line pattern with a conductive material, and refers to a board immediately before mounting an electronic component. That is, it means the circuit board which fixed the mounting position of each component, and printed and fixed the circuit pattern which connects components to the flat surface surface, in order to mount many electronic elements of various types densely on a flat plate.

Such printed circuit boards generally include a single-layer PCB and a build-up board in which multilayered PCBs are formed, that is, multilayer PCB substrates.

These build-up boards and multilayer PCB boards manufacture boards one by one,

By evaluating the quality, the yield of the overall multilayer PCB board can be increased, and the interlayer wiring can be improved.

By connecting precisely, it is possible to manufacture high density compact PCBs. In this build-up process, a connection line of a wiring is formed between the layers and the layers are connected through via holes between the layers. In order to form such a via hole, a very fine diameter can be realized using a laser rather than a conventional mechanical drill.

1 is a cross-sectional view of a conventional multilayer printed circuit board.

Referring to FIG. 1, a conventional multilayer printed circuit board 10 includes a core insulating layer 1, internal circuit pattern layers 3 and 4 formed on and under the core insulating layer 1, and the internal circuit. Upper and lower insulating layers 5 and 6 filling the pattern layers 3 and 4 and external circuit pattern layers 7 and 8 formed on the upper and lower insulating layers 5 and 6 are included.

In the core insulating layer 1 and the upper and lower insulating layers 5 and 6, conductive vias 2 and conductive via holes electrically connecting the internal circuit pattern layers 3 and 4 and the external circuit pattern layers 7 and 8 are formed. It is.

In the conventional multilayer printed circuit board 10 described above, a process of forming an even number of circuit pattern layers (four layers are formed in the illustrated figure) centering on the core insulating layer 1 is generally performed. A process of electrically connecting two layers corresponding to the outer layers by using a drill or a laser is performed. However, since the number of circuit pattern layers is limited to an even number, there is a problem in that the thickness of the substrate is increased so that it is difficult to apply to a substrate such as a portable electronic device or a semiconductor chip that is aimed at a light and small thickness.

The embodiment provides a printed circuit board having a new structure and a method of manufacturing the same.

The embodiment provides a printed circuit board including an odd number of circuit layers and a method of manufacturing the same.

Embodiments may include a core insulating layer, at least one via penetrating through the core insulating layer, an internal circuit layer embedded in the core insulating layer, and an adhesive layer formed on or under the core insulating layer to expose the via. And an external circuit layer formed on the adhesive layer, wherein the via includes a first part, a second part under the first part, a third part between the first and second parts, and the first part. A printed circuit board is formed between the third to third parts and includes at least one barrier layer formed of a metal different from the first to third parts.

In some embodiments, a core insulating layer, at least one via penetrating through the core insulating layer, an internal circuit layer embedded in the core insulating layer, and an upper or lower portion of the core insulating layer may be exposed to expose the via. A printed circuit comprising an adhesive layer, and an external circuit layer formed on the adhesive layer, the circuit layer having a number of 2n + 1 (n is a positive integer) including the internal circuit layer and the external circuit layer. Provide a substrate.

On the other hand, the method of manufacturing a printed circuit board according to the embodiment comprises the steps of preparing a metal substrate having a barrier layer laminated between the first metal layer, the second metal layer and the third metal layer and the first to third metal layer, the metal substrate Etching the first metal layer to form a first part of the via, etching the second metal layer of the metal substrate to form a connection portion and an inner circuit layer below the first part of the via, the metal Etching the third metal layer of the substrate to form a second part below the connection portion of the via, forming an insulating layer to fill the via, forming an adhesive layer on or below the insulating layer, And forming an outer circuit layer on the adhesive layer.

According to the present invention, a process can be reduced by simultaneously forming an inner circuit layer and a via, and a thin and thin printed circuit board can be provided by forming an odd layer circuit layer.

In addition, by forming a buried via in the insulating layer of the multilayer printed circuit board, heat dissipation may be improved, and a cost may be reduced by not using a plating method when forming a buried via.

In addition, by forming a via and an internal arc layer using a metal substrate on which a plurality of metals are stacked, it is possible to prevent the warpage of the substrate during the process.

In addition, by forming a primer resin layer between the insulating layer and the external circuit layer to secure the plating adhesion, the external circuit layer can be formed by the SAP process.

1 is a cross-sectional view of a printed circuit board according to the prior art.
2 is a cross-sectional view of a printed circuit board according to a first embodiment of the present invention.
3 to 19 are flowcharts for describing a method of manufacturing the printed circuit board of FIG. 2.
20 is a cross-sectional view of a printed circuit board according to a second exemplary embodiment of the present invention.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

Throughout the specification, when a part is said to "include" a certain component, it means that it can further include other components, without excluding other components unless specifically stated otherwise.

In order to clearly illustrate the present invention in the drawings, thicknesses are enlarged in order to clearly illustrate various layers and regions, and parts not related to the description are omitted, and like parts are denoted by similar reference numerals throughout the specification .

Whenever a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case where it is "directly on" another portion, but also the case where there is another portion in between. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.

The present invention provides a printed circuit board having an odd number of circuit layers, which can form a multilayer circuit board without using a plating method by simultaneously etching the buried via and the internal circuit layer.

Hereinafter, a printed circuit board according to an exemplary embodiment of the present invention will be described with reference to FIGS. 2 to 19.

2 is a cross-sectional view of a printed circuit board according to an embodiment of the present invention.

Referring to FIG. 2, the printed circuit board 100 according to the present invention includes a core insulating layer formed by the first insulating layer 120 and the second insulating layer 125, and vias formed in the core insulating layer. 115), an internal circuit layer 111 formed in the core insulating layer, and first and second external circuit layers 131 and 135 formed on the first and second insulating layers 120 and 125, respectively. , 145).

The first insulating layer 120 is formed on the second insulating layer 125, and may be formed through another insulating layer (not shown).

The first and second insulating layers 120 and 125 may be a thermosetting or thermoplastic polymer substrate, a ceramic substrate, or an organic-inorganic composite material substrate, and may include an epoxy-based insulating resin when the polymer resin is included. Alternatively, polyimide resins may be included. In addition, the material forming the first and second insulating layers 120 and 125 may be a resin material including a solid component such as glass fiber.

The first and second insulating layers 120 and 125 may be formed of the same material.

Each of the first insulating layer 120 and the second insulating layer 125 may have a thickness of about 30 μm to 80 μm .

The thickness of the core insulating layer, which is a laminated structure of the first insulating layer 120 and the second insulating layer 125, may be about 60 μm to 160 μm, preferably about 60 μm to 140 μm.

Adhesive layers 160 and 165 are formed on a surface of the core insulating layer, that is, on an upper portion of the first insulating layer 120 and a lower portion of the second insulating layer 125.

The adhesive layers 160 and 165 may be a primer resin layer including silane to enhance adhesion between the first and second insulating layers 120 and 125 and the circuit layers 131, 135 and 145. , Thickness less than 10 μ m.

Vias 115 and internal circuit layers 111 are formed in the core insulating layer.

The via 115 is a conductive via 115 penetrating from the first insulating layer 120 to the second insulating layer 125, and the first insulating layer 120 and the second insulating layer 125. The second width d2 of the cross section having the largest first width d1 in the boundary region and narrowing toward the upper surfaces of the insulating layers 120 and 125 to form the exposed surfaces of the insulating layers 120 and 125. ) Has the smallest width so that the cross section of via 115 may represent a hexagon.

The first width d1 and the second width d2 of the via 115 may satisfy about 20 μm to 100 μm .

The vias 115 may be formed of an alloy including copper as the conductive vias 115.

The via 115 is buried in the first insulating layer 120, and is formed under the first part 115a and the first part 115a, which is formed of an alloy including copper, and the second part. It is embedded in the insulating layer 125, and is formed between the second part 115b formed of the same metal as the first part 115a, and between the first part 115a and the second part 115b. And a third part 115c formed of the same metal as the first and second parts 115a and 115b.

The vias 115 have barrier layers 115d and 115e formed between the first to third parts 115a, 115b, and 115c.

That is, a first barrier layer 115d is formed between the first part and the third parts 115a and 115c, and a second barrier layer is formed between the third part and the second parts 115b and 115c. 115e) is formed.

The first and second barrier layers 115d and 115e are formed of different metals from the first to third parts 115a, 115b and 115c, and both metals have different etching selectivity.

The third part 115c is formed in the central region of the via 115, and a lower surface of the third part 115c or a lower surface of the second barrier layer 115e has the largest width of the via 115. It may have a width d1.

The first to third parts 115a, 115b, and 115c may be formed of an alloy including copper, and the first and second barrier layers 115d and 115e may be nickel, iron, cobalt, molybdenum, chromium, or the like. It may be formed of an alloy containing palladium.

At this time, the thickness of the first part 115a and the second part 115b is 20 to 70 μm , and the thickness of the third part 115c satisfies 5 to 70 μm .

The first and second barrier layers 115d are smaller than the thickness of the third part 115c and may preferably have a thickness range of 10 μm or less.

The internal circuit layer 111 is formed on the second insulating layer 125, and the thickness of the circuit pattern may be about 5 to 30 μm , a width of about 50 μm or less, preferably 30 μm or less. It is implemented in a fine pattern to have a width of.

The internal circuit layer 111 may have a rectangular cross section.

In this case, the internal circuit layer 111 is formed of the same material as the third part 115c of the via 115, and a part of the second barrier layer 115e is formed under the internal circuit layer 111.

The second barrier layer 115e may be omitted.

External circuit layers 131, 135, and 145 including via pads 135 and 145 and circuit patterns 131 connected to the vias 115 are formed on upper surfaces of the first and second insulating layers 125. Each is formed.

The external circuit layers 131, 135, and 145 may be formed on the first external circuit layers 131 and 135 formed on the core insulating layer and the second external circuit layers 145 formed on the lower portion of the core insulating layer. It is defined as

The external circuit layers 131, 135, and 145 are formed by plating by a semi-additive process (SAP) method.

In the above description, one external circuit layer 131, 135, and 145 is formed above and below the core insulating layer. However, the present invention is not limited thereto, and the upper insulating layer may be embedded in the external circuit layer 131, 135, and 145. Is formed on the first and second insulating layers 120 and 125, respectively, and a circuit layer is formed on the upper insulating layer, respectively, to form a multilayer circuit board.

As described above, the printed circuit board 100 of the present invention can form a circuit layer having a number of 2n + 1 (n is a positive integer) by forming the internal circuit layer 111 embedded in the core insulating layer. The insulating layer is formed to have the same number based on the core insulating layer so that the printed circuit board does not bend to one side.

Therefore, an odd number of circuit layers can be formed without increasing the number of insulating layers, and heat dissipation is ensured by forming vias 115 formed of a conductive material in the core insulating layer.

In addition, the adhesive layers 160 and 165 of the premier resin are formed between the insulating layers 120 and 125 and the external circuit layers 131, 135, and 145, thereby smoothly plating the external circuit layers 131, 135, and 145. As a result, adhesion between the insulating layers 120 and 125 and the external circuit layers 131, 135 and 145 is improved.

Hereinafter, a method of manufacturing the printed circuit board of FIG. 2 will be described with reference to FIGS. 3 to 19.

When the process starts, a conductive metal substrate 110 is prepared as shown in FIG. 3.

The metal substrate 110 may be formed of an alloy containing copper, the copper material may be used both a rolled foil, an electrolytic foil, the thickness of the metal substrate 110 varies in accordance with the specifications of the product required Can be used. In this case, the metal substrate 110 has a laminated structure of the first metal layer 110a, the second metal layer 110b, and the third metal layer 110c.

The first to third metal layers 110a, 110b, and 110c may have the same or similar thicknesses and may be formed of the same material.

The first to third metal layers 110a, 110b, and 110c may be formed of an alloy layer containing copper. First and second barrier metal layers 110d between the first to third metal layers 110a, 110b, and 110c formed of metals having different etching selectivities from the first to third metal layers 110a, 110b, and 110c. , 110e).

The first and second barrier metal layers 110d and 110e may be formed of an alloy including nickel, iron, cobalt, molybdenum, chromium, or palladium, and the thickness of the first and second barrier metal layers 110d and 110e. May be formed thinner than the thickness of the second metal layer 110b.

In the present invention, the total thickness of the metal substrate 110 is preferably 80 μm to 170 μm. The substrate 110 of copper material cleans the surface by performing a surface cleaning operation including pickling and washing with water.

Next, as shown in FIG. 4, the photosensitive film 116 is attached onto the upper surface of the metal substrate 110.

The photosensitive film 116 is to form an etching pattern for etching the metal substrate 110, the thickness of the photosensitive film 116 varies from 15㎛ to 30㎛, both UV exposure type and LDI exposure type Available.

Next, as shown in FIG. 5, the photosensitive film 116 is exposed and developed to form a photosensitive pattern (not shown), and the metal substrate 110 is etched using a mask to etch the first part of the via 115. 115a).

A portion of the metal substrate 110 is wet etched by a wet etchant such as copper chloride or iron chloride to form the first part 115a of the via 115, and the first metal layer 110a and the first barrier metal layer 110d may be formed. The first part 115a is formed by etching only the first metal layer 110a by different etching selectivities.

After etching the first part 115a of the via 115 as shown in FIG. 5, the photosensitive pattern is peeled off using a NaOH diluent.

Next, as shown in FIG. 6, the photosensitive film 117 is formed on the entire surface of the first part 115a and the exposed first barrier metal layer 110d.

In order to form the internal circuit layer 111 with the second metal layer 110b, a portion of the photosensitive film 117 on the first barrier metal layer 110d is exposed and developed to expose the photosensitive pattern 118 of FIG. 7. The first barrier metal layer 110d is etched using the photosensitive pattern 118 as a mask to form a mask pattern.

Next, the second metal layer 110b under the mask pattern 119 is selectively etched using an etchant different from the etching solution on which the mask pattern 119 is formed, so that the first region 111a of the internal circuit layer 111 of FIG. ) And the third part 115c of the via 115.

When the second barrier metal layer 110e below the second metal layer 110b is exposed, etching stops to form a first region 111a of the internal circuit layer 111, and a first region of the formed internal circuit layer 111. The region 111a has a rectangular cross section having a mask pattern 119 thereon.

Next, as shown in FIG. 9, when the mask pattern 119 and the exposed second barrier metal layer 110e are removed, the internal circuit layer 111 is formed of the second metal layer 110b. And a second region 111b formed of the second barrier metal layer 110e.

 Next, as shown in FIG. 10, the first insulating layer 120 is formed to fill the first and third parts 115a and 115c and the internal circuit layer 111 of the via 115.

The first insulating layer 120 is formed using a thermosetting or thermoplastic resin in which solid components such as glass fibers are not formed or formed, and the thickness of the first insulating layer 120 is about 30 μm to 80 μm. Can be.

Next, an adhesive layer 160 and a copper foil layer 161 are formed on the first insulating layer 120.

The copper foil layer 161 is to be a parent of the SAP process, the adhesive layer 160 is formed to be attached on the first insulating layer 120, the adhesive layer 160 is formed of a premier resin.

The adhesive layer 160 is a primer resin containing silane, and the copper foil layer 161 and the adhesive layer 160 may be a PCF (Primer Coated Copper Foil) in which the primer resin layer is coated on the copper foil layer 161. have.

In this case, an upper surface of the via 115 is pressed through the adhesive layer 160 to be in contact with the copper foil layer 161.

Next, as shown in FIG. 11, a photosensitive film 136 is formed on the upper surface of the copper foil layer 161 and the lower surface of the metal substrate 110.

The photosensitive film 136 formed under the metal substrate 110 may be a matrix forming a photosensitive pattern for forming the second part 115b of the via 115 and the internal circuit layer 111. The photosensitive film 136 on the upper portion of the metal substrate 110 functions as a protective film for protecting the copper foil layer 161 during the formation of the photosensitive pattern under the metal substrate 110 and the etching of the metal substrate 110.

Therefore, the photosensitive film 136 on the copper foil layer 161 may be replaced with a protective film or a protective organic layer, and may be omitted.

Next, as shown in FIG. 12, the photosensitive film 136 under the metal substrate 110 is developed to form a photosensitive pattern, and the metal substrate 110 is etched using the photosensitive pattern as a mask to form the vias 115. The second part 115b is formed below the first part 115a.

The etching is performed until the second barrier metal layer 110e is exposed so that the second barrier metal layer 110e is exposed on the lower surface of the internal circuit layer 111.

As described above, the via 115 has an upper portion and a lower portion divided into first parts 115a to third parts 115b to be etched to have a first width d1 having the largest central shape. As it gets closer to, it has a hexagonal cross section that becomes narrower in width.

When the second part 115b of the via 115 is formed, the photosensitive pattern is peeled off, and as shown in FIG. 13, the second insulating layer 125 so that the first part 115a of the via 115 is buried. And the adhesive layer 165 and the copper foil layer 166 are formed on the second insulating layer 125.

The thickness and material of the second insulating layer 125 and the copper foil layer 166 may be the same as the first insulating layer 120 and the copper foil layer 161 on the first insulating layer 120.

Next, as shown in FIG. 14, the upper and lower copper foil layers 161 and 166 are removed to expose the lower adhesive layers 160 and 165.

In this case, the copper foil layers 161 and 166 may be full-etched to proceed with the SAP process, and may proceed with a desmear process to remove foreign substances and give roughness of the adhesive layers 160 and 165.

Next, as shown in FIG. 15, the seed layer 132 is formed by electroless plating on the adhesive layers 160 and 165.

The seed layer 132 may be formed by electroless plating of copper. The seed layer 132 may be formed to have a uniform thickness of 3 μm or less on the adhesive layers 160 and 165 and on the upper and lower surfaces of the exposed vias 115.

Next, as illustrated in FIG. 16, a photosensitive pattern 148 is formed on the seed layer 132 to form the external circuit layers 131, 135, and 145.

The photosensitive pattern 148 is formed by attaching a photosensitive film and then exposing and developing it according to a circuit design.

Next, as shown in FIG. 17, the plating layers 130 and 140 are formed by performing electroplating on the seed layer 132 exposed by the photosensitive pattern 148.

It is preferable to use a method of depositing a conductive metal such as copper by applying an appropriate current to a rectifier of a direct current or pulse / reverse method by calculating an area to be plated and electroplating.

Next, as shown in FIG. 18, the photosensitive pattern 148 is peeled off, and the plating layers 130 and 140 and the seed layer 132 under the photosensitive pattern 148 are flash etched to form the lower adhesive layers 160 and 165. And the external circuit layers 131, 135, and 145 are formed.

In this case, the pads 135 and 145 and the circuit pattern 131 are formed on the first insulating layer 120 and are connected to the first part 115a of the via 115. The lower pad 145 and the lower pad connected to the first external circuit layers 131 and 135 including the upper pad 135 and the upper circuit pattern 131 and the second part 115b of the via 115. The second external circuit layer 145 includes a pad 145 and a lower circuit pattern (not shown).

Finally, as shown in FIG. 19, the process is completed by filling the circuit patterns 131 of the external circuit layers 131, 135, and 145 and forming the coverlay 150 to expose the pads 135 and 145. .

As described above, the via substrate is drilled to form a via hole, and the via hole is plated and embedded to form a via. Instead, the metal substrate 110 is etched to form a via 115, and the via 115 is buried. By forming the insulating layers 120 and 125, the manufacturing cost is reduced, and the manufacturing step is reduced by forming the internal circuit layer 111 on the same metal substrate as the vias 115.

In addition, fine patterns may be formed by forming the external circuit layers 131, 135, and 145 by using an SAP process.

Hereinafter, a printed circuit board according to a second exemplary embodiment of the present invention will be described with reference to FIG. 20.

Referring to FIG. 20, the printed circuit board 200 according to the present invention includes a core insulating layer formed by the first insulating layer 120 and the second insulating layer 125, and vias formed in the core insulating layer. 115), an internal circuit layer 112 formed in the core insulating layer, and first and second external circuit layers 131 and 135 formed on the first and second insulating layers 120 and 125, respectively. , 145).

The first insulating layer 120 is formed on the second insulating layer 125, and may be formed through another insulating layer therebetween.

The material forming the first and second insulating layers 120 and 125 may be a resin material including a solid component such as glass fiber, and the first and second insulating layers 120 and 125 may be formed of the same material. Can be.

The stacked structure of the first insulating layer 120 and the second insulating layer 125 forms a core insulating layer, and the thickness of the core insulating layer may be about 60 μm to 140 μm .

Adhesive layers 160 and 165 are formed on a surface of the core insulating layer, that is, on an upper portion of the first insulating layer 120 and a lower portion of the second insulating layer 125.

The adhesive layers 160 and 165 are to enhance adhesion between the first and second insulating layers 120 and 125 and the circuit layers 131, 135 and 145 above, and may be a primer resin layer including silane. Can be less than 10 μm in thickness. Vias 115 and internal circuit layers 112 are formed in the core insulating layer.

The via 115 is a conductive via 115 penetrating from the first insulating layer 120 to the second insulating layer 125, and the first insulating layer 120 and the second insulating layer 125. It has the largest width in the boundary region, and the width becomes narrower toward the upper surface of each insulating layer, so that the cross section may exhibit a hexagon.

The first width d1 and the second width d2 of the via 115 may satisfy about 20 μm to 100 μm .

The vias 115 may be formed of an alloy including copper as the conductive vias 115.

The via 115 is buried in the first insulating layer 120, and is formed under the first part 115a and the first part 115a, which is formed of an alloy including copper, and the second part. It is embedded in the insulating layer 125, and is formed between the second part 115b formed of the same metal as the first part 115a, and between the first part 115a and the second part 115b. And a third part 115c formed of the same metal as the first and second parts 115a and 115b.

The vias 115 have barrier layers 115d and 115e formed between the first to third parts 115a, 115b, and 115c.

That is, a first barrier layer 115d is formed between the first part and the third parts 115a and 115c, and a second barrier layer is formed between the third part and the second parts 115b and 115c. 115e) is formed.

The first and second barrier layers 115d and 115e are formed of different metals from the first to third parts 115a, 115b and 115c, and both metals have different etching selectivity.

The third part 115c may be formed in a central region of the via 115, and a bottom surface of the third part 115c may have a first width d1 that is the largest width of the via 115.

The first to third parts 115a, 115b, and 115c may be formed of an alloy including copper, and the first and second barrier layers 115d and 115e may be nickel, iron, cobalt, molybdenum, chromium, or the like. It may be formed of an alloy containing palladium.

At this time, the thickness of the first part 115a and the second part 115b is 20 to 70 μm , and the thickness of the third part 115c satisfies 5 to 70 μm .

The first and second barrier layers 115d are smaller than the thickness of the third part 115c and may preferably have a thickness range of 10 μm or less.

External circuit layers 131, 135, and 145 including via pads 135 and 145 and circuit patterns 131 connected to the vias 115 are formed on upper surfaces of the first and second insulating layers 125. Each is formed.

The outer circuit layers 131, 135, and 145 are formed on surfaces of the first and second insulating layers 120 and 125, and the inner circuit layers 112 are formed on the first and second insulating layers 120 and 125. It is formed between.

The external circuit layers 131, 135, and 145 may be formed through an SAP process.

In the printed circuit board 200 of FIG. 20, the circuit pattern of the internal circuit layer 112 has a quadrangular cross section and borders the first and second insulating layers 120 and 125 like the vias 115. It may be a quadrangle symmetrically formed in the axis, the region buried in the first insulating layer 120 is formed of the same material as the third part (115c) of the via 115, the second insulating layer ( The region buried in 125 is formed of the same material as the third part 115c of the via 115.

Even when the internal circuit layer 112 is formed as shown in FIG. 20, it may be formed using the manufacturing method of FIGS. 3 to 19, and the second part 115b of the via 115 may be formed in the process of FIGS. 12 and 13. When forming, regions to be buried in the second insulating layer 125 of the internal circuit layer 112 may be formed together.

As described above, the printed circuit board 200 of the present invention can form a circuit layer having a number of 2n + 1 (n is a positive integer) by forming the internal circuit layer 112 embedded in the core insulating layer. In addition, the insulating layer is formed with the same number based on the core insulating layer to prevent the bending of the printed circuit board.

Therefore, an odd number of circuit layers can be formed without increasing the number of insulating layers, and heat dissipation is ensured by forming vias 115 formed of a conductive material in the core insulating layer.

In addition, the bending of the metal substrate is prevented in the process by forming the intermediate layer of the metal from each other.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

Printed Circuit Board 100, 200
Via 115
Internal circuitry 111
First Insulation Layer 120
Second Insulation Layer 125

Claims (18)

Core insulation layer,
At least one via penetrating the core insulating layer,
An internal circuit layer embedded in the core insulating layer,
An adhesive layer formed on or below the core insulating layer and exposing the via;
An external circuit layer formed on the adhesive layer
/ RTI >
The via is formed between a first part, a second part below the first part, a third part between the first and second parts, and the first to third parts, and the first to third parts. A printed circuit board comprising at least one barrier layer formed of a part and a different metal. The method of claim 1,
The core insulating layer comprises a first insulating layer filling the first and third parts of the via, and
And a second insulating layer filling the second part of the via under the first insulating layer. The method of claim 2,
The inner circuit layer is formed of the same material as the third part of the via. The method of claim 1,
The first to third parts of the via are formed of the same material. The method of claim 1,
The inner circuit layer is a printed circuit board having a rectangular cross section. The method of claim 1,
The barrier layer may include a first barrier layer formed between the first part and the third part, and
And a second barrier layer formed between the third part and the second part, wherein the first and second barrier layers are formed of the same material. The method of claim 1,
The adhesive layer is a printed circuit board containing a primer resin. Core insulation layer,
At least one via penetrating the core insulating layer,
An internal circuit layer embedded in the core insulating layer,
An adhesive layer formed on or below the core insulating layer and exposing the via;
An external circuit layer formed on the adhesive layer
/ RTI >
A printed circuit board comprising a circuit layer having a number of 2n + 1 (n is a positive integer) including the inner circuit layer and the outer circuit layer. Preparing a metal substrate having a barrier layer laminated between a first metal layer, a second metal layer and a third metal layer, and the first to third metal layers;
Etching the first metal layer of the metal substrate to form a first part of a via,
Etching the second metal layer of the metal substrate to form a connection portion and an internal circuit layer under the first part of the via;
Etching the third metal layer of the metal substrate to form a second part under the connection portion of the via;
Forming an insulating layer filling the via;
Forming an adhesive layer on or below the insulating layer, and
Forming an outer circuit layer on the adhesive layer
And a step of forming the printed circuit board. 10. The method of claim 9,
Wherein forming the insulating layer comprises:
Forming a first insulating layer filling the first part of the via, the connecting portion, and the internal circuit layer; and
And forming a second insulating layer filling the second part of the via. 10. The method of claim 9,
Preparing the metal substrate,
And forming the barrier layer from a material having an etch selectivity different from that of the first to third metal layers. 10. The method of claim 9,
Wherein the step of forming the adhesive layer comprises:
A method of manufacturing a printed circuit board comprising the step of attaching the adhesive layer bonded to the copper foil layer on the upper or lower portion of the insulating layer. The method of claim 12,
Wherein forming the external circuit layer comprises:
Removing the copper foil layer,
Forming an electroless plating layer on the adhesive layer;
Forming a photosensitive pattern on the electroless plating layer, and
And electroplating the photosensitive pattern with a mask to form the external circuit layer. The method of claim 13,
Wherein forming the external circuit layer comprises:
After the electroplating, a method of manufacturing a printed circuit board by flash etching until the electroless plating layer is removed. 10. The method of claim 9,
Preparing the metal substrate,
The method of claim 1, wherein the first metal layer and the third metal layer are formed of the same metal layer. 10. The method of claim 9,
Forming the second part of the via,
And wet etching the third metal layer of the metal substrate to form a second part of the via and to form a lower portion of the internal circuit layer. 10. The method of claim 9,
The inner circuit layer,
A method for manufacturing a printed circuit board comprising a circuit pattern having a thickness of 5 to 30 μm and a width of 50 μm or less. 10. The method of claim 9,
And the first metal layer to the third metal layer are formed of an alloy containing copper, and the barrier layer is formed of an alloy containing nickel.

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