JPH05218642A - Manufacture of circuit board - Google Patents
Manufacture of circuit boardInfo
- Publication number
- JPH05218642A JPH05218642A JP4256390A JP25639092A JPH05218642A JP H05218642 A JPH05218642 A JP H05218642A JP 4256390 A JP4256390 A JP 4256390A JP 25639092 A JP25639092 A JP 25639092A JP H05218642 A JPH05218642 A JP H05218642A
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- conductive layer
- layer
- conductive
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Insulated Metal Substrates For Printed Circuits (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は高発熱部品を実装するの
に適した高い放熱性を有する金属基材をベースとする回
路基板の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a circuit board based on a metal base material having a high heat dissipation property, which is suitable for mounting high heat generating components.
【0002】[0002]
【従来の技術】従来、高発熱部品が実装される回路基板
には例えば、特開昭59−168696号公報に示され
ているような、銅、アルミニウム等の金属基材の上に絶
縁層を介して第一の銅箔パターン層を形成し、この金属
基材上の所望の部分に有機絶縁物を被覆し、スルーホー
ルを穿設した銅張絶縁物を位置合わせしてこの金属基材
上に積層し、この後銅張絶縁物のスルーホールを導通さ
せると共に銅張絶縁物の表面層にエッチングを施して第
二の銅箔パターン層を形成させて二層の金属基材をベー
スとする回路基板を完成するというものがある。2. Description of the Related Art Conventionally, a circuit board on which high heat-generating components are mounted has an insulating layer on a metal base material such as copper or aluminum as disclosed in JP-A-59-168696. A first copper foil pattern layer is formed on the metal base material, a desired portion of the metal base material is covered with an organic insulating material, and a copper clad insulation material having a through hole is aligned with the metal base material. Then, the through hole of the copper clad insulator is made conductive, and the surface layer of the copper clad insulator is etched to form a second copper foil pattern layer to form a two-layer metal base material. There is one that completes a circuit board.
【0003】[0003]
【発明が解決しようとする課題】しかしながら、上記従
来の方法は金属基材の上に絶縁層を介して第一の銅箔パ
ターン層を形成した上に、ついでスルーホールを穿設し
た銅張絶縁物を位置合わせして積層し、スルーホールを
導通させると共に銅張絶縁物の表面層にエッチングを施
して第二の銅箔パターン層を形成させるという製造方法
であり、工程が複雑になるという問題がある。スルーホ
ールの穿設以外の各工程での処理は金属基材上での処理
となり、その重量および剛性により搬送、保持が困難と
なる。更には、第二の銅箔パターン層を形成するエッチ
ング等の薬液に対する金属基材の保護等の対策が必要と
なる。However, the above-mentioned conventional method is a copper clad insulation in which a first copper foil pattern layer is formed on a metal base material via an insulating layer and then through holes are formed. It is a manufacturing method that aligns and stacks the objects, conducts the through holes and performs etching on the surface layer of the copper clad insulator to form the second copper foil pattern layer, which complicates the process There is. Processing in each step other than through-hole drilling is processing on a metal base material, and it is difficult to carry and hold it due to its weight and rigidity. Furthermore, it is necessary to take measures such as protection of the metal base material against chemicals such as etching for forming the second copper foil pattern layer.
【0004】本発明は上記問題点の解決をし、簡単な製
法で放熱性のよい回路基板の製造方法を提供することを
目的とするものである。An object of the present invention is to solve the above problems and to provide a method for manufacturing a circuit board having a good heat dissipation by a simple manufacturing method.
【0005】[0005]
【課題を解決するための手段】本発明は上記目的を達成
するため以下のような手段を有するものである。The present invention has the following means in order to achieve the above object.
【0006】特許請求の範囲第1項に示すように、金属
基材上に第一の絶縁層を介して第一の導電層を形成し、
前記第一の導電層上に、第二の絶縁層と第二の導電層と
を同時に貼り付ける回路基板の製造方法としたことを特
徴とする。As set forth in claim 1, a first conductive layer is formed on a metal substrate through a first insulating layer,
A method of manufacturing a circuit board is characterized in that a second insulating layer and a second conductive layer are simultaneously attached on the first conductive layer.
【0007】又、特許請求の範囲第2項に示すように、
第二の絶縁層が窓明き部を有する絶縁体フィルムであ
り、第二の導電層がその上に形成された導電体よりなる
回路パターンである回路基板の製造方法としたことを特
徴とする。Further, as set forth in claim 2,
The second insulating layer is an insulator film having a window opening, the second conductive layer is a circuit pattern made of a conductor formed on the second conductive layer is a method for manufacturing a circuit board, characterized in that ..
【0008】[0008]
【作用】特許請求の範囲第1項に示すように、金属基材
上に第一の絶縁層を介して第一の導電層を形成し、前記
第一の導電層上に、第二の絶縁層と第二の導電層とを同
時に貼り付ける回路基板の製造方法としたことにより、
又、特許請求の範囲第2項に示すように、第二の絶縁層
が窓明き部を有する絶縁体フィルムであり、第二の導電
層がその上に形成された導電体よりなる回路パターンで
ある回路基板の製造方法としたことにより、第二の導電
層の形成処理がエポキシ樹脂等の樹脂から成る絶縁薄層
上での処理となりフィルム状で軽量ワークでの処理が可
能となる。又、エッチング等での薬液に対する金属基材
の保護等の問題がなく加工が簡単となる。According to the first aspect of the present invention, a first conductive layer is formed on a metal substrate via a first insulating layer, and a second insulating layer is formed on the first conductive layer. By using the method of manufacturing a circuit board in which the layer and the second conductive layer are simultaneously attached,
Further, as described in claim 2, the second insulating layer is an insulator film having a window opening, and the second conductive layer is a circuit pattern made of a conductor formed thereon. According to the method of manufacturing a circuit board as described above, the process for forming the second conductive layer is performed on an insulating thin layer made of a resin such as epoxy resin, and a film-like lightweight work can be performed. Further, there is no problem such as the protection of the metal base material against the chemical solution by etching or the like, and the processing becomes simple.
【0009】[0009]
【実施例】以下、本発明の第一の実施例につき図1及び
図2を参照し、詳細に説明する。図1において11は
銅、アルミニウムといった良熱伝導性金属基材である。
この金属基材11の上に第一の絶縁層12を形成する。
この第一の絶縁層12は例えばエポキシ樹脂あるいはエ
ポキシ樹脂を含浸したガラス繊維であり、ロールコータ
ー、フローコーター等での塗布法、スクリーン印刷法あ
るいはシート状プリプレグの貼り付け法等により形成す
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described in detail below with reference to FIGS. In FIG. 1, 11 is a metal base material having good thermal conductivity such as copper or aluminum.
The first insulating layer 12 is formed on the metal base 11.
The first insulating layer 12 is, for example, epoxy resin or glass fiber impregnated with epoxy resin, and is formed by a coating method such as a roll coater or a flow coater, a screen printing method, or a sheet-like prepreg attaching method.
【0010】この第一の絶縁層12の上に銅等からなる
第一の導電層24、34を形成する。この第一の導電層
24、34の形成方法としては、パターン状に銅箔を打
ち抜いたものを貼り付ける方法、全面に銅箔を貼り付け
エッチングによりパターンを形成する方法、あるいはス
テンレス板等の上に図1のようなパターンの電気銅めっ
きを行い、第一の絶縁層12上に転写、貼り付ける方法
等がある。この第一の導電層24、34として上記の方
法により、厚みが0.03mm程度から3mm程度まで
任意のものを作ることができる。この中で銅の厚みの薄
いものは前記エッチングまたは電気めっきをして転写す
る方法により形成する。First conductive layers 24 and 34 made of copper or the like are formed on the first insulating layer 12. The method for forming the first conductive layers 24 and 34 is as follows: a method in which a copper foil is punched out in a pattern shape is attached, a method in which a copper foil is attached to the entire surface and etching is performed to form a pattern, 1 is subjected to electrolytic copper plating in a pattern as shown in FIG. 1 and then transferred or attached onto the first insulating layer 12. As the first conductive layers 24, 34, an arbitrary layer having a thickness of about 0.03 mm to about 3 mm can be manufactured by the above method. Among them, the thin copper is formed by the above-mentioned etching or electroplating method and transferring.
【0011】この後、導電層のパターン間および基板端
部、つまり図1の銅箔のない部分19に樹脂を塗布し、
表面の段差を極力なくすようにする。樹脂材料は第一の
絶縁層12と同じエポキシ樹脂である。塗布にはディス
ペンサーまたはスクリーン印刷法を用いる。このように
して、ほぼ段差のない状態にしてその上に、第二の絶縁
層20及び第二の導電層13を形成する。Thereafter, a resin is applied between the patterns of the conductive layer and the end portions of the substrate, that is, the portion 19 without the copper foil in FIG.
Try to eliminate the steps on the surface as much as possible. The resin material is the same epoxy resin as the first insulating layer 12. A dispenser or a screen printing method is used for coating. In this way, the second insulating layer 20 and the second conductive layer 13 are formed on the second insulating layer 20 with almost no step.
【0012】図3はその第二の絶縁層20及び第二の導
電層13の形成の実施例を示したものである。第二の絶
縁層20及び第二の導電層13を、前もって、絶縁体フ
ィルム(第二の絶縁層)20上に形成しそれを前記第一
の導電層24、34の上に貼り付ける。図1に示すよう
に絶縁体フィルム(第二の絶縁層)20には第二の導電
層13と窓明き部54、64、74、84が形成されて
いる。この第二の導電層13の回路パターンは全面に貼
り付けられた銅箔をエッチングすることにより形成する
ことができる。この場合、金属基材がないことによって
エッチング処理の薬液に対する特別の保護の必要が生じ
ない。FIG. 3 shows an embodiment of forming the second insulating layer 20 and the second conductive layer 13. The second insulating layer 20 and the second conductive layer 13 are formed in advance on the insulator film (second insulating layer) 20 and attached onto the first conductive layers 24 and 34. As shown in FIG. 1, the insulating film (second insulating layer) 20 is provided with the second conductive layer 13 and window openings 54, 64, 74, 84. The circuit pattern of the second conductive layer 13 can be formed by etching a copper foil attached to the entire surface. In this case, since there is no metal base material, there is no need for special protection against etching chemicals.
【0013】このような回路基板に半導体チップをボン
ディングする場合はボンディングのランド部に金めっき
等の電気めっきを行う。前記窓明き部54、64、7
4、84および第二の導電層13上のボンディングのラ
ンド部に金めっきを行う。つまり、部分的にめっきをし
たい所を残してめっきレジストを印刷し、窓明きされた
部分に電気めっきを行う。この電気めっきが金めっきの
場合、正確にはニッケルめっきをした後、重ねて金めっ
きを行う。この後、めっきレジストを除去し、回路基板
を形成することができる。When a semiconductor chip is bonded to such a circuit board, electroplating such as gold plating is performed on the land portion for bonding. The window opening parts 54, 64, 7
Gold plating is performed on the bonding land portions 4, 84 and the second conductive layer 13. That is, the plating resist is printed while leaving a portion where plating is desired to be performed, and electroplating is performed on the window-opened portion. When this electroplating is gold plating, precisely, after nickel plating, gold plating is performed again. After that, the plating resist can be removed to form a circuit board.
【0014】次に、このようにして製造した回路基板へ
の高発熱部品(半導体チップ)の実装につき説明する。
第一の導電層の金めっきをしたランド部に半導体チップ
のダイボンディングを行う。この後、ダイボンディング
された半導体チップを起点として、第一の導電層又は第
二の導電層の金めっきをしたランド部を終点とするよう
なワイヤボンディングを行う。又、第一の導電層と第二
の導電層との間の接続は各々の金めっきをしたランド部
間でワイヤボンディングを行うことにより実施される。Next, mounting of high heat-generating components (semiconductor chips) on the circuit board manufactured in this way will be described.
The semiconductor chip is die-bonded to the gold-plated land portion of the first conductive layer. After this, wire bonding is performed starting from the die-bonded semiconductor chip and ending with the gold-plated land portion of the first conductive layer or the second conductive layer. The connection between the first conductive layer and the second conductive layer is made by wire bonding between the gold-plated lands.
【0015】図2は第一の導電層24、34形成の別の
実施例を示したものである。図2に示すように、第一の
導電層24、34の厚みの大きいものは銅板を打ち抜い
たものを第一の絶縁層12に貼り付ける方法により形成
する。図2において118は最終的には外部端子となる
部分である。この後、第一の実施例と同様に、この第一
の導電層24、34上に第二の導電層13を絶縁体フィ
ルム(第二の絶縁層)20上に形成したもの貼り付け
る。FIG. 2 shows another embodiment of forming the first conductive layers 24 and 34. As shown in FIG. 2, the first conductive layers 24, 34 having a large thickness are formed by a method in which a punched copper plate is attached to the first insulating layer 12. In FIG. 2, reference numeral 118 is a portion that will eventually become an external terminal. Then, as in the first embodiment, the second conductive layer 13 formed on the insulating film (second insulating layer) 20 is attached onto the first conductive layers 24 and 34.
【0016】次に、別の実施例について説明する。図4
において11は銅、アルミニウムといった良熱伝導性金
属基材である。この金属基材11の上に第一の絶縁層1
2を形成する。形成方法はスクリーン印刷法であり、材
料はエポキシ樹脂である。この第一の絶縁層12の印刷
の際に、部分的に絶縁層のない窓明き部44を形成す
る。Next, another embodiment will be described. Figure 4
11 is a metal base material having good heat conductivity such as copper or aluminum. The first insulating layer 1 is formed on the metal base material 11.
Form 2. The forming method is a screen printing method, and the material is an epoxy resin. During the printing of the first insulating layer 12, the window opening portion 44 partially having no insulating layer is formed.
【0017】この第一の絶縁層12の上に銅等からなる
第一の導電層34を形成する。形成方法は図2の第一の
導電層24、34の形成と同じ方法である。この後、導
電層のパターン間および基板端部、つまり図4の銅箔の
ない部分19に樹脂を塗布し、表面の段差を極力なくす
ようにする。樹脂材料は第一の絶縁層12と同じく、エ
ポキシ樹脂である。塗布にはディスペンサーまたはスク
リーン印刷法を用いる。このようにして、ほぼ段差のな
い状態にする。A first conductive layer 34 made of copper or the like is formed on the first insulating layer 12. The forming method is the same as the forming method of the first conductive layers 24 and 34 of FIG. After that, resin is applied between the patterns of the conductive layer and the end portion of the substrate, that is, the portion 19 without the copper foil in FIG. 4, so as to eliminate the surface step as much as possible. The resin material is an epoxy resin like the first insulating layer 12. A dispenser or a screen printing method is used for coating. In this way, there is almost no step.
【0018】この場合の第二の絶縁層(フィルム)およ
び第二の導電層は前述のような方法により形成し、第一
の導電層24、34の上に貼りつける。この第二の絶縁
層(フィルム)に設けた窓明き部で、金属基材11また
は第一の導電層34を部分的に露出させるように窓明き
部54、64、74、84が形成される。従って、図4
の基板の上に第二の絶縁層、第二の導電層を形成したも
のでは、金属基材11または第一の導電層34が露出す
る構造となる。In this case, the second insulating layer (film) and the second conductive layer are formed by the method as described above and attached on the first conductive layers 24 and 34. The window opening portions 54, 64, 74, 84 are formed so that the metal substrate 11 or the first conductive layer 34 is partially exposed at the window opening portion provided in the second insulating layer (film). To be done. Therefore, FIG.
In the case where the second insulating layer and the second conductive layer are formed on the substrate, the structure is such that the metal base material 11 or the first conductive layer 34 is exposed.
【0019】その後、半導体チップ等がボンディングさ
れるボンディングのランド部に金めっき等の電気めっき
を行う。従って、このボンディングのランド部は部分的
に第一の絶縁層のない窓明き部44、第二の絶縁層の窓
明き部54、64、74、84および第二の導電層13
上のボンディングのランド部となり、金属基材11およ
び第一の導電層上に半導体チップのダイボンディングを
行うことができる。必要に応じては第二の導電層13上
にも半導体チップのダイボンディングを行うことができ
る。After that, electroplating such as gold plating is performed on the bonding land portion to which the semiconductor chip or the like is bonded. Therefore, the land portion of this bonding partially includes the window opening portion 44 without the first insulating layer, the window opening portions 54, 64, 74, 84 of the second insulating layer and the second conductive layer 13.
It becomes a land portion for the upper bonding, and the die bonding of the semiconductor chip can be performed on the metal base material 11 and the first conductive layer. If necessary, the semiconductor chip can be die-bonded on the second conductive layer 13 as well.
【0020】[0020]
【発明の効果】これまでに述べたような構成とすること
により以下に述べる効果が得られる。[Effects of the Invention] With the above-mentioned structure, the following effects can be obtained.
【0021】特許請求の範囲第1項に示すように、金属
基材上に第一の絶縁層を介して第一の導電層を形成し、
前記第一の導電層上に、第二の絶縁層と第二の導電層と
を同時に貼り付ける回路基板の製造方法としたことによ
り、又、特許請求の範囲第2項に示すように、第二の絶
縁層が窓明き部を有する絶縁体フィルムであり、第二の
導電層がその上に形成された導電体よりなる回路パター
ンである回路基板の製造方法としたことにより、第二の
導電層の形成処理がエポキシ樹脂等の樹脂から成る絶縁
薄層上での処理となりフィルム状で軽量の処理が可能と
なる。又、エッチング等での薬液に対する金属基材の保
護等の問題がなく加工が簡単となる。As described in claim 1, a first conductive layer is formed on a metal substrate via a first insulating layer,
By using the method for manufacturing a circuit board in which the second insulating layer and the second conductive layer are simultaneously attached on the first conductive layer, as described in claim 2, The second insulating layer is an insulator film having a window opening portion, and the second conductive layer is a circuit pattern made of a conductor formed on the second conductive layer. The conductive layer is formed on the insulating thin layer made of a resin such as an epoxy resin, so that a film-like and lightweight process can be performed. Further, there is no problem such as the protection of the metal base material against the chemical solution by etching or the like, and the processing becomes simple.
【図1】本発明の第一の実施例の回路基板の製法で、第
一の導電層を形成した段階を示す斜視図である。FIG. 1 is a perspective view showing a step of forming a first conductive layer in a method for manufacturing a circuit board according to a first embodiment of the present invention.
【図2】本発明の別の実施例で、第一の導電層を形成す
る別の方法を示す斜視図である。FIG. 2 is a perspective view showing another method of forming the first conductive layer according to another embodiment of the present invention.
【図3】本発明の第一の実施例の回路基板の製法で、第
一の導電層を形成した回路基板の上に第二の絶縁層およ
び第二の導電層を貼り合わせる前のを状態を示す斜視図
である。FIG. 3 shows a state before the second insulating layer and the second conductive layer are attached onto the circuit board having the first conductive layer formed by the method for manufacturing the circuit board according to the first embodiment of the present invention. It is a perspective view showing.
【図4】本発明の別の実施例の回路基板の製法で、第一
の導電層を形成した段階を示す斜視図である。FIG. 4 is a perspective view showing a step of forming a first conductive layer in a method for manufacturing a circuit board according to another embodiment of the present invention.
11 金属基材 12 第一の絶縁層 13 第二の導電層 20 第二の絶縁層(絶縁体フィルム) 24 第一の導電層 34 第一の導電層 44 第一の絶縁層の窓明き部 54 第二の絶縁層の窓明き部 64 第二の絶縁層の窓明き部 74 第二の絶縁層の窓明き部 84 第二の絶縁層の窓明き部 DESCRIPTION OF SYMBOLS 11 Metal base material 12 1st insulating layer 13 2nd conductive layer 20 2nd insulating layer (insulator film) 24 1st conductive layer 34 1st conductive layer 44 Window opening part of 1st insulating layer 54 second insulating layer window opening portion 64 second insulating layer window opening portion 74 second insulating layer window opening portion 84 second insulating layer window opening portion
Claims (2)
導電層を形成し、前記第一の導電層上に、第二の絶縁層
と第二の導電層とを同時に貼り付けることを特徴とする
回路基板の製造方法。1. A first conductive layer is formed on a metal substrate via a first insulating layer, and a second insulating layer and a second conductive layer are simultaneously formed on the first conductive layer. A method for manufacturing a circuit board, which comprises attaching the circuit board.
ィルムであり、第二の導電層がその上に形成された導電
体よりなる回路パターンであることを特徴とする特許請
求の範囲第1項に記載の回路基板の製造方法。2. The second insulating layer is an insulating film having a window opening, and the second conductive layer is a circuit pattern made of a conductive material formed thereon. 2. A method for manufacturing a circuit board as set forth in claim 1.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4256390A JPH07123187B2 (en) | 1992-09-25 | 1992-09-25 | Circuit board manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4256390A JPH07123187B2 (en) | 1992-09-25 | 1992-09-25 | Circuit board manufacturing method |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1141357A Division JPH0744322B2 (en) | 1989-06-02 | 1989-06-02 | Circuit board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH05218642A true JPH05218642A (en) | 1993-08-27 |
JPH07123187B2 JPH07123187B2 (en) | 1995-12-25 |
Family
ID=17292015
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4256390A Expired - Fee Related JPH07123187B2 (en) | 1992-09-25 | 1992-09-25 | Circuit board manufacturing method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07123187B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102007049939A1 (en) | 2006-10-18 | 2008-07-31 | Yazaki Corp. | Method for producing a printed circuit board |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62217698A (en) * | 1986-03-19 | 1987-09-25 | 昭和電工株式会社 | Metal base multilayer printed board |
JPH036096A (en) * | 1989-06-02 | 1991-01-11 | Matsushita Electric Works Ltd | Circuit board |
-
1992
- 1992-09-25 JP JP4256390A patent/JPH07123187B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62217698A (en) * | 1986-03-19 | 1987-09-25 | 昭和電工株式会社 | Metal base multilayer printed board |
JPH036096A (en) * | 1989-06-02 | 1991-01-11 | Matsushita Electric Works Ltd | Circuit board |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102007049939A1 (en) | 2006-10-18 | 2008-07-31 | Yazaki Corp. | Method for producing a printed circuit board |
US8110118B2 (en) | 2006-10-18 | 2012-02-07 | Yazaki Corporation | Method of manufacturing circuit board |
DE102007049939B4 (en) * | 2006-10-18 | 2017-08-31 | Yazaki Corporation | Method for producing a printed circuit board |
Also Published As
Publication number | Publication date |
---|---|
JPH07123187B2 (en) | 1995-12-25 |
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