JPH01260581A - Graphic processing method - Google Patents

Abstract

PURPOSE:To reduce memory capacity required for a data qualification processing by substituting only graphic data in the neighborhood of the outer periphery of a block for the block of graphic data in an integrated circuit, and applying the data qualification processing on the graphic data in the integrated circuit including substituted graphic data. CONSTITUTION:All of the graphic data 10 in the integrated circuit to be qualified are provided with circuit blocks A12, circuit blocks B14, circuit blocks C16, circuit blocks D18, circuit block E20, and circuit blocks F22. At least one block of the graphic data 10 in the integrated circuit is substituted by only the graphic data in the neighborhood of the outer periphery of the block, for example, the block A12 is substituted by the block A'32, and the data qualification processing is applied on the graphic data 30 in the integrated circuit including the substituted graphic data. In such a way, it is possible to reduce the memory capacity in the data qualification processing for the graphic data in the whole of highly integrated circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a graphic processing method for verifying graphic data of an integrated circuit.

Conventional technology Conventionally, data verification processes such as geometric rule checks and electrical rule checks for the graphical data of integrated circuits composed of multiple circuit blocks and interconnections between blocks have been performed on all graphical data of each block and between blocks. This was done for all the graphic data of the integrated circuit, including the wiring diagram data.

Problems to be Solved by the Invention However, if the method of performing data verification processing as described above on all the graphical data of an integrated circuit is applied to the graphical data of recent extremely highly integrated circuits, However, there is a problem in that the memory capacity required during data verification processing becomes extremely large, and in the worst case, the data verification processing is interrupted due to insufficient memory capacity.

In addition, in order to improve this problem, there is a method of performing data verification processing on each block's graphic data and inter-block wiring diagram data, but in this method, the boundary between each block and inter-block wiring is The problem was that it was not possible to verify the data.

The present invention solves these problems and makes it possible to reduce the amount of memory used in data verification processing of graphic data for the entire highly integrated circuit, and to verify data at the boundary between each block and the wiring between the blocks. The purpose is to improve.

Means for Solving the Problems The present invention replaces at least one block of graphic data of an integrated circuit constituted by a plurality of circuit blocks and inter-block wiring with only graphic data near the outer periphery of the block. This graphic processing method is characterized in that data verification processing is performed on graphic data of an integrated circuit including graphic data that has been generated.

Function: The graphic processing method of the present invention replaces at least one block of graphic data of an integrated circuit constituted by blocks of a plurality of circuits and wiring between blocks, with only graphic data near the outer periphery of the block, and By performing data verification processing on the graphical data of the integrated circuit, including graphical data that has been It is possible to verify data at the boundary between one cock and the wiring between blocks.

Embodiment FIG. 1(a) and FIG. 1(b) show an embodiment of the present invention. In FIG. 1(a), 10 is all the graphical data of the unverified integrated circuit,] 2 is the circuit block A, 14 is the circuit block B, 16 is the circuit block I] C118 is the circuit block D
, 20 is a circuit block E, and 22 is a circuit block F. In FIG. 1(b), 32 is a circuit block A, a block A' containing only graphic data in an area near the outer periphery that is a certain width inside the block outer periphery of 1.2, 34 is a circuit block B],
4 is a block C containing only graphic data in an area near the outer periphery that is a certain width inside the block outer periphery, and 36 is a block C that contains only graphic data in an area near the outer periphery that is a certain width inside the block outer periphery of circuit blocks C1 and 6. ', 38 is a block containing only graphical data in an area near the outer periphery within a certain width from the block outer periphery of circuit block LJ block 1) 18;
40 is a block E' containing only graphic data in an area near the outer periphery within a certain width from the block outer periphery of the circuit block E20.
, 42 is from the outer periphery of the circuit block F22.
There is a block F containing only graphic data in the area near the outer periphery inside the constant width, and 30 is all the graphic data 10 of the integrated circuit, block A12 is block A'32, block B'-4 is block B'34 Then, block C16 is changed to block C'36, and block D-18 is changed to block D'.
38 is the graphic data of the integrated circuit after replacing the block E20 with the block E'40 and the block F22 with the block F'42.

When performing a geometric rule check on all the graphic data 10 of the integrated circuit shown in FIG.
65 circuit block D182 circuit block E20. A geometrical check is performed on each circuit block of the circuit block F22. Thereafter, a geometric rule check is performed on the graphic data 30 of the replaced integrated circuit shown in FIG. 1(b).

When the graphic processing method of this embodiment as described above is carried out, the maximum amount of data when performing a geometric rule check on all the graphic data 10 of an integrated circuit is as follows:
122 circuit block B14゜circuit block C165 circuit block D182 circuit block E202 circuit block F
22, the largest one of the graphic data 30 of the replaced integrated circuit is 7. However, this maximum amount of data is usually one size smaller than the amount of all graphic data 10 of an integrated circuit. Therefore, it is possible to considerably reduce the memory capacity required for geometrical rule checking of all the graphical data 10 of this integrated circuit, and it is also possible to verify data at the boundaries between each circuit block and inter-block wiring.

As described in detail, according to the present invention, at least one block of graphic data of an integrated circuit constituted by a plurality of circuit blocks and inter-block wiring is replaced with only graphic data near the outer periphery of the block. However, by performing data verification processing on the graphic data of the integrated circuit that includes this replaced graphic data, the amount of data during data verification can be reduced, and the memory capacity required for data verification processing can be significantly reduced. It is possible to reduce the number of blocks and to verify data at the boundary between each block and the inter-block wiring, and its practical effects are extremely large.

[Brief explanation of the drawing]

FIG. 1 is a mask pattern diagram for explaining a graphic processing method according to an embodiment of the present invention.

Claims (1)

[Claims] At least one block of graphic data of an integrated circuit constituted by blocks of a plurality of circuits and wiring between the blocks is replaced with only graphic data near the outer periphery within the block, and the replaced graphic data is included. A graphic processing method characterized in that data verification processing is performed on graphic data of the integrated circuit.