JPH0247773A - Graphic processing method - Google Patents
Graphic processing methodInfo
- Publication number
- JPH0247773A JPH0247773A JP63198203A JP19820388A JPH0247773A JP H0247773 A JPH0247773 A JP H0247773A JP 63198203 A JP63198203 A JP 63198203A JP 19820388 A JP19820388 A JP 19820388A JP H0247773 A JPH0247773 A JP H0247773A
- Authority
- JP
- Japan
- Prior art keywords
- cell
- data
- cells
- graphic data
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003672 processing method Methods 0.000 title claims description 7
- 238000013524 data verification Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 description 3
- CIWBSHSKHKDKBQ-JLAZNSOCSA-N Ascorbic acid Chemical compound OC[C@H](O)[C@H]1OC(=O)C(O)=C1O CIWBSHSKHKDKBQ-JLAZNSOCSA-N 0.000 description 1
- 238000013144 data compression Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は集積回路の図形データのデータ検証時の図形処
理方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a graphic processing method for verifying graphic data of an integrated circuit.
従来の技術
従来、くり返しセルを有する集積回路の図形データに対
する幾河学的ルールチエツクや電気的ルールチエツクや
接続照合などのデータ検証処理は集積回路の全図形デー
タに対しておこなわれていた。2. Description of the Related Art Conventionally, data verification processes such as geometrical rule checks, electrical rule checks, and connection verification for graphical data of integrated circuits having repeating cells have been performed on all graphical data of integrated circuits.
発明が解決しようとする課題
しかしながら、上記のようなデータ検証処理を集積回路
の全図形データに対しておこなうという方法を、最近の
非常に高集積化された集積回路の図形データに対して適
用すると、データ検証処理時に必要なメモリ容量が非常
に膨大となり、最悪の場合にはメモリ容量不足によりデ
ータ検証処理が中断してしまうという問題点があった。Problems to be Solved by the Invention However, if the method of performing data verification processing as described above on all the graphical data of an integrated circuit is applied to the graphical data of recent extremely highly integrated circuits, However, there is a problem in that the memory capacity required during data verification processing becomes extremely large, and in the worst case, the data verification processing is interrupted due to insufficient memory capacity.
また、仮にメモリ容量が十分にあり、データ検証処理が
可能であるとしても、そのデータ検証処理時間が非常に
膨大なものとなってしまうという問題点があった。Further, even if there is sufficient memory capacity and data verification processing is possible, there is a problem in that the data verification processing time will be extremely long.
本発明はこのような問題点を解消し、高集積化された集
積回路全体の図形データのデータ検証処理におけるメモ
リ使用量の軽減とその処理時間の短縮を可能とすること
を目的とする。SUMMARY OF THE INVENTION An object of the present invention is to solve these problems and to make it possible to reduce the amount of memory used and the processing time in data verification processing of graphic data of the entire highly integrated circuit.
課題を解決するための手段
本発明は、集積回路の図形データ中の、くり返し使用さ
れているセルについて１個のセルを残して他のセルを除
去してデータ圧縮をおこなった図形データに対してデー
タ検証処理をおこなうことを特徴とする図形処理方法で
ある。Means for Solving the Problems The present invention provides a data compression method for graphic data of integrated circuits that is compressed by removing cells that are repeatedly used, leaving only one cell. This is a graphic processing method characterized by performing data verification processing.
作用
本発明の図形処理方法は集積回路の図形データ中の、く
り返し使用されているセルについて１個のセルを残して
他のセルを除去してデータ圧縮をおこなった図形データ
に対してデータ検証処理をおこなうことにより、データ
検証処理時に必要となるメモリ容量を減少することとそ
のデータ検証処理時間を短縮することができる。Operation The graphic processing method of the present invention performs data verification processing on graphic data that has been compressed by removing cells that are repeatedly used from graphic data of an integrated circuit, leaving only one cell. By performing this, it is possible to reduce the memory capacity required during data verification processing and shorten the data verification processing time.
実施例
第１図（ａ）と第１図（ｂ）と第１図（Ｃ）に本発明の
一実施例を示す。Embodiment An embodiment of the present invention is shown in FIG. 1(a), FIG. 1(b), and FIG. 1(C).
第１図（ａ）と第１図（ｂ）と第１図（Ｃ）のｌＯはセ
ルＡ。1O in FIG. 1(a), FIG. 1(b), and FIG. 1(C) is cell A.
１２はセルＢ、１４はセルＣ２１６はセルＤ、１８はセ
ルＥ、２０はセルＦ、２２はセルＧ、２４はセルＨ１２
６はセルＩ、３０はセルｂ、３２はセルｄ、３４はセル
ｅ、３６はセルｆ、３８はセルｈである。12 is cell B, 14 is cell C, 16 is cell D, 18 is cell E, 20 is cell F, 22 is cell G, 24 is cell H12
6 is cell I, 30 is cell b, 32 is cell d, 34 is cell e, 36 is cell f, and 38 is cell h.
第１図（ａ）に示すように、集積回路の全図形データが
１個のセルＡ１０．セルＣ１４，セルＧ２２゜セル１２
６と、複数個（り返し並べられたセルＢ１２、セルＤ１
６．セルＥ１８．セルＦ２０．セルＨ２４により構成さ
れている。この集積回路の全図形データの幾何学的ルー
ルチエツクをおこなう際に、複数個（り返し並べられた
セルＢ１２゜セルＤ１６．セルＥ１８．セルＦ２０．セ
ルＨ２４の各セルについて、１個のセルのみを残して他
を除去する。しかるのちに除去した部分のデータ圧縮を
おこない第１図（ｂ）に示すような図形データを構成し
、この図形データに対して幾何学的ルールチエツクをお
こなう。As shown in FIG. 1(a), all the graphic data of the integrated circuit is stored in one cell A10. Cell C14, Cell G22゜Cell 12
6, and multiple cells (cell B12, cell D1 arranged repeatedly)
6. Cell E18. Cell F20. It is composed of cell H24. When performing a geometric rule check of all the graphical data of this integrated circuit, only one cell is checked for each cell (cell B12, cell D16, cell E18, cell F20, cell H24, which are arranged repeatedly). The removed portion is then compressed to form graphic data as shown in FIG. 1(b), and a geometric rule check is performed on this graphic data.
上記のようにすべての種類のセルについて１セルだけ残
して再度構成した図形データに対して幾何学的ルールチ
エツクをおこなったのでは同一種類のセル間での幾何学
的ルールチエツクが不十分な場合がある。このような場
合は第１図（Ｃ）に示すように、２つのセルｂ３０でセ
ルＢ１２を、２つ、のセルｄ３２でセルＤ１４を、４つ
のセルｅ３４でセルＥ１８を、２つのセルｆ３６でセル
Ｆ２０を、２つのセルｈ３８でセルＨ２４を構成すれば
各同一種類のセル間での幾何学的ルールチエツクを完全
におこなうことができる。If you perform a geometric rule check on the reconfigured figure data leaving only one cell for all types of cells as described above, the geometric rule check between cells of the same type is insufficient. There is. In such a case, as shown in FIG. 1(C), two cells b30 are used for cell B12, two cells d32 are used for cell D14, four cells e34 are used for cell E18, and two cells f36 are used for cell B12. By configuring the cell F20 and the cell H24 with two cells h38, it is possible to completely perform a geometric rule check between cells of the same type.
以上のような本実施例の図形処理方法をおこなうと、複
数個くり返し並べられたセルについては１個のみとなる
ため、それだけ幾何学的ルールチエツクの際のデータ量
を軽減することができる。従って、この集積回路に対す
る幾何学的ルールチエツクにおいて必要となるメモリ容
量をかなり減少することと、その処理時間を短縮するこ
とができる。When the graphic processing method of this embodiment as described above is carried out, a plurality of cells that are repeatedly arranged are reduced to only one, and the amount of data for geometric rule checking can be reduced accordingly. Therefore, it is possible to considerably reduce the memory capacity required for geometric rule checking on this integrated circuit, and to shorten the processing time.
発明の詳細
な説明したように、本発明によれば、集積回路の図形デ
ータ中の、（り返し使用されているセルについて１個の
セルを残して他のセルを除去してデータ圧縮をおこなっ
た図形データに対してデータ検証処理をおこなうことに
より、データ検証処理時に必要となるメモリ容量を減少
することとそのデータ検証処理時間を短縮することがで
き、その実用的効果は極めて大きいものである。As described in detail, the present invention compresses graphic data of an integrated circuit by leaving one cell that is used repeatedly and removing other cells. By performing data verification processing on the graphic data that has been created, the memory capacity required for data verification processing can be reduced and the data verification processing time can be shortened, and its practical effects are extremely large. .
第１図は本発明の一実施例の図形処理方法を説明するた
めの集積回路図形データのレイアウト図である。
１０・・・・・・セルＡ、１２・・・・・・セルＢ、１
４・・・・・・セルＣ１１６・・・・・・セルＤ、１８
・旧・・セルＥ、２０・・・・・・セルＦ、１２・・・
・・・セルＧ、２４・・・・・・セルＨ１２６・・・・
・・セルＩ、３０・・・・・・セルｂ、３２・・・・・
・セルｄ、３４・・・・・・セルｅ、３６・・・・・・
セルｆ、３８・・・・・・セルｈ０FIG. 1 is a layout diagram of integrated circuit graphic data for explaining a graphic processing method according to an embodiment of the present invention. 10...Cell A, 12...Cell B, 1
4...Cell C116...Cell D, 18
・Old...Cell E, 20...Cell F, 12...
...Cell G, 24...Cell H126...
...Cell I, 30...Cell B, 32...
・Cell d, 34... Cell e, 36...
Cell f, 38...Cell h0
Claims (1)
ルについて、１個のセルを残して他のセルを除去してデ
ータ圧縮をおこなった図形データに対してデータ検証処
理をおこなうことを特徴とする図形処理方法。The present invention is characterized in that data verification processing is performed on graphic data that has been compressed by removing cells that are repeatedly used in graphic data of an integrated circuit, leaving only one cell. Graphic processing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63198203A JPH0247773A (en) | 1988-08-09 | 1988-08-09 | Graphic processing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63198203A JPH0247773A (en) | 1988-08-09 | 1988-08-09 | Graphic processing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0247773A true JPH0247773A (en) | 1990-02-16 |
Family
ID=16387198
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63198203A Pending JPH0247773A (en) | 1988-08-09 | 1988-08-09 | Graphic processing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0247773A (en) |
-
1988
- 1988-08-09 JP JP63198203A patent/JPH0247773A/en active Pending
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