JPH034372A - Layout device for lsi function cell - Google Patents

Abstract

PURPOSE:To obtain a layout with short wiring length and to prevent a waste layout space occurring by deciding a rough element arranging position and a rough inter-element wiring path in a function cell with the short wiring length and with few crossing. CONSTITUTION:Firstly, the rough element arranging position and rough inter- element wiring path 6 is obtained with a circuit drawing information storage part 1 so as to reduce the wiring length and the number of times of crossing as for as possible by referring to a design circuit diagram. Next, the shape of each function cell is decided so as to reduce the area of the entire chip, and the width W of the function cell is decided with a setting processor 7 refer ring to the shape. Next, a waste area is eliminated by compressing a rough layout in a direction intersecting orthogonally to a cell size designation direction, and the arranging position of each cell is compressed 8 in the cell size designa tion direction so as to be set within set width. And such operation is repeated by the decision 10 of the sequence of the arrangement of the element and detail arrangement 11, and all the elements can be set within the cell size with compaction 14 under the condition with the short wiring length and few cross.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an apparatus for high-density layout of functional cells used in LSI chip pattern design.

(Conventional technology) When laying out functional cells, it is necessary to determine the placement positions of elements and the routes for inter-element wiring (wiring), but conventionally placement and wiring were each done in separate processing phases. .

This is because layout problems are usually very large-scale combinatorial problems, so to reduce their complexity,
The process is divided into two stages: placement and wiring.

For example, Nagao et al., "Module Design Support System for Analog LSI", Proceedings of the 1989 Institute of Electronics, Information and Communication Engineers Spring National Conference, Bart 1.5A-
In 7-3 (PP396-397), element arrangement and inter-element wiring are performed in separate phases.

With this method, it is not possible to determine detailed wiring routes and secure accurate wiring space at the element placement stage, so it is often impossible to expect a high wiring rate through automatic wiring programs, and unwired areas often occur.

Therefore, it is necessary to connect unwired wires, and it is necessary to repeatedly correct the arrangement position, peel off existing wires, change the route, rewire, etc., and there is a problem that pattern design takes a long time.

In addition, since the placement and wiring results were corrected after the placement was completed, it was difficult to obtain the high-density layout that was originally envisioned when the wiring was completed.

In particular, when designing an analog functional cell in which various element shapes exist, the above-mentioned situation becomes conspicuous because the element density within the cell is greatly affected by the combination of element shapes.

(Problems to be Solved by the Invention) As described above, in the conventional method, layout was performed in two stages: placement and wiring. However, in order to perform a high-density functional cell layout, it is necessary to perform a high-element-density layout at the placement stage, and at the same time, it is important to secure accurate wiring space and plan the wiring routes. . Furthermore, when considering placement and wiring at the same time, the complexity of the layout increases, so there is a need for a method that does not increase processing time exponentially with respect to the scale of the problem.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide an LSI functional cell layout device that can layout functional cells with high element density and high wiring rate in a short time. It is about providing.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the LSI functional cell layout device of the present invention lays out elements and inter-element wiring in functional cells used in LSI pattern design. An LSI functional cell layout device that roughly lays out the positions of the elements and the routes of the inter-element wiring so that the length of the wiring within the functional cell is short and there are fewer intersections. - a size setting means for setting the size of the functional cell in either the vertical direction or the horizontal direction; and means for compressing the general layout in a direction orthogonal to the direction set by the size setting means. , means for compressing the general layout compressed in one direction in a direction set by the size setting means so that it fits within the size set by the size setting means, and determining a detailed arrangement order of the elements. means for setting a detailed arrangement of the elements so that the inside of the functional cell is high-density and securing a space necessary for the inter-element wiring; and means for performing the inter-element wiring in detail; The device includes means for compressing the elements arranged in detail and the interconnections between the elements.

(Function) In the LSI functional cell layout apparatus of the present invention, the approximate element placement positions and the approximate inter-element wiring routes within the functional cell, where the wiring length is short and there are few intersections, are first determined.

Although this allows a layout with short wiring lengths, the density of elements within the cell is not necessarily high because there are various element shapes and their combinations generate wasted layout space.

Next, set the size (width or height) of the functional cell,
Compress the wasted free space that exists in the direction perpendicular to it,
After removing as much as possible, the arrangement position of each element is proportionally compressed in the specified direction so that it fits within the set cell size.

By doing this, the conditions of short wiring length and few intersections are maintained, all elements fit within the specified cell size, and waste areas existing in the direction perpendicular to the specified direction can be roughly removed. However, there is overlap between the elements in the designated direction.

Therefore, next, the element arrangement position and wiring space for eliminating this overlap and realizing high element density are determined for each element according to the determined element arrangement order. Here, a high wiring rate is guaranteed by the automatic wiring program and a high-density element arrangement is realized by securing an accurate wiring space and preparing the wiring route 4-1 at the same time as determining the arrangement position of the elements.

Algorithms related to these placements and routings can use highly computationally efficient methods, so even when compared to placing and routing using conventional algorithms, they can be done in the same practical amount of time. It can be processed with

When comparing the results obtained by the present invention with those obtained by the conventional placement method, a high level of interconnection can be expected during detailed inter-element interconnection, so that the processing time for completing the interconnection can be shortened with less effort in dialog correction.

In addition, since there is no need to make major changes or corrections to the element placement position that occur when modifying unwired areas, the results of the combination of element shapes that have been increased in density at the wiring stage can be used as they are at the wiring completion stage. This makes it possible to realize a higher-density functional cell layout than in the past.

(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing the configuration of an LSI functional cell layout device according to an embodiment of the present invention.

The circuit diagram information storage unit 1 stores coordinate information of elements and wiring symbols of an LSI circuit diagram to be designed.

The element library information storage section 2 stores information regarding each element used in layout design of an LSI chip.

The inter-element connection information storage section 3 stores information regarding connections between elements.

The layout result information storage unit 4 stores layout results obtained by each processing device, and reads and writes them as necessary.

The layout result display device 5 displays the layout results.

The rough placement/wiring processing device 6 performs rough placement of elements and rough wiring between elements.

The cell size setting processing device 7 sets either the width or the height of the cell.

The general layout compression processing device 8 compresses the general layout in a direction orthogonal to the direction set by the cell size setting processing device 7.

The proportional compression processing device 9 compresses the general layout in the direction set by the cell size setting processing device 7 so as to fit within the size set by the placement position cell size setting processing device 7.

The arrangement order determination processing device 10 determines the order of element arrangement.

The detailed placement processing device 11 determines detailed placement positions of elements.

The wiring space securing processing device 12 secures wiring space.

The detailed wiring processing device 13 performs detailed wiring.

The compaction processing device 14 compresses the layout by compaction.

The apparatuses from the above-mentioned rough placement/wiring processing device 6 to the compaction processing device are performed by software.

The dialogue modification processing device 15 performs dialogue modification processing for manually modifying the layout result.

Next, the operation of this embodiment will be explained. FIG. 2 is a flowchart showing the operation of this embodiment, and FIG. 3 is a flowchart showing the operation of this embodiment.
FIG. 3 is an explanatory diagram of each processing step of element arrangement.

First, for example, with reference to a design circuit diagram, approximate element placement positions and approximate inter-element wiring routes are obtained so that the wiring length is as short as possible and the number of intersections is reduced (step 201
, Fig. 3(a)).

Next, the area of the entire chip should be as small as possible.
Roughly determine the shape of each functional cell.

Using this as a reference, determine the size of the functional cell.

That is, one of the cell width (X-axis direction) or height (Y-axis direction) (for example, width w (X-axis direction)) is set (step 202).

Here, the width of the cell and the height of the cell are defined as, when the length of one side of the cell on the -dimensional plane is the width of the cell, the length of the side perpendicular to the length of the side of the cell on the -dimensional plane is defined as the height of the cell.

Next, the rough layout is compressed in a direction (Y-axis direction) orthogonal to the cell size designation direction to remove useless areas (step 203, FIG. 3(b)).

Then, the arrangement position of each element is adjusted in the cell size specified direction (X-axis direction) so that it fits within the width W set in step 202.
(Step 204, FIG. 3(C)).

Through these operations, the conditions of short wiring length and few intersections are preserved, all elements fit into the specified cell size, and the wasted area existing in the direction (Y-axis direction) perpendicular to the cell size specification direction is saved. It can be roughly removed. However, elements may overlap in the cell size designation direction (X-axis direction).

Therefore, in order to eliminate such overlap between elements and achieve high element density, the element arrangement order is determined, and the element arrangement position and wiring space are determined for each element according to the determined element arrangement order.

Regarding the order of element arrangement, as shown in FIG. 4, for example, with reference to the roughly arranged state, the elements are arranged in order from the bottom according to the horizontal layer so that the wiring length is as short as possible. That is, the arrangement of the cells 40, 41, 42, 43, and 44 at the bottom of the state shown in FIG. 3(C) is determined first.

In this way, the order of element arrangement is determined (step 2
05). Through such processing, detailed placement positions can be determined so as not to destroy the relative positional relationship of elements that was considered at the time of rough placement, and as a result, wiring lengths can be shortened and intersections can be reduced.

Next, we will discuss the detailed placement position determination of elements and the securing of wiring space.

FIG. 5 is an explanatory diagram when determining the detailed arrangement position of elements. FIG. 5(a) corresponds to FIG. 3(c). Then, as shown in FIG. 5(b), the ceiling data A
Place the inner elements on the bottom. In this case, the element arrangement positions are determined so that the lower horizontal layer has a higher density in order.

FIG. 5(c) is a diagram showing a state in which the ceiling data A is all placed on the lower side and becomes the floor data B, and the rearrangement of the elements is completed.

Let us now consider a situation where processing is halfway through and the next selected element is to be placed. For example, as shown in FIG. 3(d), consider a situation where the element 51 is moved and its arrangement is determined.

First, space for wiring not connected to this element 51 is secured. At this time, in order to secure as wide an area as possible in which elements can be placed, the wiring is spread out to the left and right (third
Figure (e)).

Next, secure space for the wiring connected to the element so that it can be placed anywhere (Figure 3 (f)
).

Next, candidate locations for arranging the elements are selected.

Placement candidate locations can be determined by, for example, taking the OR shape of the placed elements and wiring routes placed on the lower side (floor data B) and the elements before placement placed on the upper side (ceiling data A), and then selecting the shape change points as candidates. Make it. Here, selecting the shape change point as a candidate means that, as shown in FIG. 6, when a certain element 51 is moved to be adjacent to another element 52, as shown in FIG.
There is no wasted space as shown in Figure 6(c)(d).
), the elements 51 are arranged as shown in FIG.

When such shape change points are used as candidates, there are many candidates, so the optimal candidate location is selected using an evaluation function.

FIG. 7 is an explanatory diagram of this evaluation function. Figure 7(a)
As shown in FIG.
Assume that there are three placement candidate locations 51a, 51b, and 51c.

For the evaluation function, as shown in FIG. 7(b), the arrangement of the element 51 is selected such that the unevenness on the upper side and the lower side match and the entire element 51 has a nearly rectangular shape.

In the figure, the arrangement of the elements 51 is determined so that hl=h2-h3 holds as much as possible.

That is, the elements 51 are respectively 51a and 51b.

By comparing hl, h2, h3, etc. when placed in 51c, the optimum position candidate is selected so that the unevenness on the upper side and the lower side match as much as possible.

In FIG. 3, the element 51 is temporarily placed using the shape change point method (FIG. 3(g)), and the estimated value of the roughness at the temporarily placed position is determined according to the evaluation function.

Since there are usually a plurality of temporary locations, a plurality of evaluation values can be obtained, but the location with the largest evaluation value is selected to obtain the space necessary for wiring.

Finally, the element placement position is registered, the wiring route is determined accordingly, and the unnecessary wiring space is removed (FIG. 3(h)).

In this way, the detailed placement position of the element is determined,
You can get the space you need for wiring. (Step 206)
.

Repeat this process until the placement positions of all elements are determined.
That is, the processing of steps 205 and 206 is repeated to complete the arrangement determination.

Thereafter, detailed wiring is performed (step 207), compaction is performed (step 208), and a high-density functional cell layout is performed.

Figure 8 compares and explains the layout according to the conventional method and the present example. Figure 8 (a) shows the conventional method, in which wiring space is not secured, so unwired areas occur. There was a high possibility that this would occur, and after placing the elements, it was necessary to modify the dialogue for unwired wires.

However, as shown in FIG. 8(b), in this embodiment, the space C necessary for the wiring is secured in addition to the arrangement of the elements, so that the wiring can be easily connected at a high density.

In addition, since there is no need to make major changes or corrections to the element placement position when modifying unwired areas, the results of the combination of element shapes that have been increased in density at the placement stage can be utilized as they are at the wiring completion stage. This makes it possible to realize a higher-density functional cell layout than in the past.

In this embodiment, the size in the X-axis direction is determined first, but the size in the Y-axis direction may be determined first.

[Effects of the Invention] As described above in detail, according to the present invention, a layout of functional cells with high element density and high wiring rate can be performed in a short time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an LSI functional cell layout device according to an embodiment of the present invention, FIG. 2 is a flowchart showing the processing of this layout device, and FIG. 3 is each process of element placement. 4 is an explanatory diagram of the process, FIG. 4 is an explanatory diagram of the element arrangement order, FIG. 5 is an explanatory diagram of the element arrangement process, and FIG.
7 is an explanatory diagram of the evaluation function, and FIG. 8 is a diagram illustrating the layout results of the conventional method and the present invention.

Claims (1)

[Claims] An LSI functional cell layout device that lays out elements and inter-element wiring in a functional cell used in LSI pattern design, wherein the length of the wiring in the functional cell is short and there are few intersections. means for schematically laying out the positions of the elements and the routes of the inter-element interconnections so that the size of the functional cell is set in either the vertical direction or the horizontal direction; means for compressing in a direction perpendicular to the direction set by the setting means; and a direction set by the size setting means so that the general layout compressed in one direction fits within the size set by the size setting means. a means for determining a detailed arrangement order of the elements, a means for setting the detailed arrangement of the elements so that the functional cell is densely packed, and reducing the space required for the inter-element wiring. 1. A layout device for an LSI functional cell, comprising: means for arranging the inter-element wiring in detail; and means for compressing the precisely arranged elements and the inter-element wiring.