JPH04255074A - Automatic arrangement/wiring system for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce design manhour and to shorten a designing period by automatically generating a through pass testing circuit for testing the wiring of a printed substrate and a through pass test testing pattern and merging a function test testing pattern. CONSTITUTION:A through pass testing circuit automatic generator 4 automatically generates a through pass testing circuit based upon through pass testing mode/terminal corresponding information 2. An automatic arranging/wiring processor 6 executes automatic wiring processing based upon the output 5 of the circuit 4 and supplies circuit connecting information 7 to a logical simulator 12. A through pass testing circuit test pattern automatic generator 8 automatically generates a test pattern. The output 9 of the generator 8 and function test testing pattern information 3 are merged by a test pattern merging device 10 and test pattern information 11 is supplied to the logical simulator 12. Thus, mask pattern information 14 is formed by executing mask pattern processing.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic placement and routing system for semiconductor integrated circuits, and more particularly to an automatic placement and routing system for semiconductor integrated circuits having an automatic insertion device for printed circuit board wiring test circuits.

0002

[Prior Art] Conventional automatic placement and routing systems for semiconductor integrated circuits, when performing automatic placement and routing processing, include a through-pass test circuit in the circuit connection information from the beginning, perform logic simulation based on this, and obtain mask pattern information. It looks like this.

FIG. 3 is a block diagram of an automatic placement and wiring system for semiconductor integrated circuits, showing an example of such a conventional system. As shown in FIG. 3, the conventional automatic placement and routing system 15A for semiconductor integrated circuits inputs circuit connection information 5 with through-pass test circuit to an automatic placement and routing processing device 6, and creates circuit connection information 7 containing placement and routing information. . This circuit connection information 7 containing layout and wiring information is input to the logic simulator 12 together with the test pattern information 9 containing the through-pass test circuit test pattern to confirm the function, and then the mask pattern processing device 13 outputs mask pattern information 14.

Of these, the automatic placement and wiring processing device 6 determines the optimal placement of a plurality of independent functional blocks shown in the circuit connection information 5 on the semiconductor substrate based on the placement and wiring rules for the semiconductor substrate. do. Moreover, this wiring is done so that there are no unwired lines between all the functional blocks, and the circuit connection information 7 containing placement and wiring information is output. Further, the mask patterning processing device 13 converts the circuit connection information including the layout and wiring information into actual size, and outputs the mask pattern information 14.

[0005]

SUMMARY OF THE INVENTION In the above-mentioned conventional automatic placement and wiring system, a designer uses the circuit connection information corresponding to the circuit connection information with through-pass test circuit 5 and the test pattern information with test pattern with through-pass test circuit test pattern 9.
From the time of creating the test pattern, it is necessary to create a through-pass test circuit and a through-pass test test pattern in addition to the originally desired functions. Therefore, there are disadvantages in that the design period becomes longer and the burden on the designer increases.

An object of the present invention is to provide an automatic placement and routing system for semiconductor integrated circuits that can shorten the design period and reduce the number of design steps to reduce the burden on the designer.

[0007]

[Means for Solving the Problems] The automatic placement and wiring system for semiconductor integrated circuits of the present invention is an automatic through-pass test circuit generator that automatically generates test circuits for through-path tests for performing printed circuit board wiring tests in semiconductor integrated circuits. an automatic placement and routing processing device that automatically performs placement and routing processing based on circuit connection information from the through-pass test circuit automatic generation device; and a through-pass test circuit test pattern automatic generation device that automatically generates a test pattern for the through-pass test circuit; and a test pattern merging device that merges functional test test patterns based on the test pattern information.

[0008]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an automatic placement and routing system for semiconductor integrated circuits showing one embodiment of the present invention. As shown in FIG. 1, in this embodiment, circuit connection information 1 and through-pass test mode terminal correspondence information 2 are input to a through-pass test circuit automatic generator 4 to create circuit connection information 5 with through-pass test circuit. Next, this circuit connection information 5 is processed by an automatic placement and wiring processing device 6 to create circuit connection information 7 containing placement and wiring information. Further, the above-mentioned through-pass test mode terminal correspondence information 2 is input to the through-pass test test pattern automatic generator 8, and through-pass test circuit test pattern information 9 is created. This through-pass test circuit test pattern information 9 is input to the test pattern merging device 10 together with the functional test test pattern information 3, and test pattern information 11 with through-pass test test pattern is created. Next, the logic simulator 12 executes a logic simulation using the circuit connection information 7 containing the layout and wiring information and the test pattern 11 with the through-pass test pattern to confirm the validity of the logic. After such logical confirmation, mask pattern information 14 is obtained by the mask patterning processing device 13 as an output of the automatic placement and routing system 15.

FIG. 2 is an input/output buffer circuit diagram serving as a database for the through-pass test circuit automatic generator shown in FIG. As shown in FIG. 2, the input buffer unit 16 with through-pass test circuit of the automatic through-pass test circuit generator 4 is an AN between an input signal from an input terminal and a through-pass control signal.
It takes the D logic and outputs it to the normal circuit, and also passes the input signal to the through-pass circuit 17. Further, the output buffer section 18 with through-pass test circuit inputs the signal from the normal circuit, and also inputs the input signal passed from the input buffer 16 via the through-pass circuit 17 under the control of the through-pass control signal, and outputs it to the output terminal. Output to. These input/output buffers 16 and 18 are prepared as a database of the through-pass test circuit automatic generator 4.

[0011]

As explained above, the automatic placement and routing system for semiconductor integrated circuits of the present invention automatically generates through-pass test circuits and through-pass test test patterns for printed circuit board wiring tests, thereby enabling designers to conduct through-pass tests. It is no longer necessary to create test patterns for circuit and through-pass tests, which reduces the burden on designers, reduces man-hours, and shortens the design period.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an automatic placement and routing system for semiconductor integrated circuits showing an embodiment of the present invention.

FIG. 2 is an input/output buffer circuit diagram serving as a database of the through-pass test circuit automatic generator shown in FIG. 1;

FIG. 3 is a configuration diagram of an automatic placement and routing system for semiconductor integrated circuits, which is a conventional example.

[Explanation of symbols]

1 Circuit connection information 2 Through-pass test mode terminal correspondence information 3
Functional test test pattern information 4 Through-path test circuit automatic generator 5 Circuit connection information with through-path test circuit 6 Automatic placement and wiring processing device 7 Circuit connection information with placement and wiring information 8 Through-path test circuit test pattern automatic generation device 9
Through pass test circuit test pattern information 10
Test pattern merging device 11 Test pattern information with through-pass test test pattern 12 Logic simulator 13 Mask patterning processing device 14 Mask pattern information 15 Automatic placement and routing system 16 Input buffer unit 17 Through-pass circuit 18 Output buffer unit

Claims (2)

[Claims] 1. A through-pass test circuit automatic generator that automatically generates a test circuit for a through-pass test for performing a printed circuit board wiring test in a semiconductor integrated circuit; An automatic placement and routing processing device that performs placement and routing processing, an automatic through-pass test circuit test pattern generation device that automatically generates test patterns for the through-pass test circuit, and a test pattern merging device that merges functional test test patterns based on the test pattern information. An automatic placement and routing system for semiconductor integrated circuits, comprising: 2. A logic simulator that confirms the validity of logic based on circuit connection information containing placement and routing information from the automatic placement and routing device and test pattern information with through-pal test test patterns from the test pattern merging device; Claim 1, further comprising: a mask patterning processing device that performs mask patterning processing based on the output of the simulator and outputs mask pattern information.
The automatic placement and routing system for semiconductor integrated circuits described above.