JPS6395580A - Determining system for lsi terminal position - Google Patents

Abstract

PURPOSE:To arrange LSI terminals most suitably for minimum logical modification, to reduce designing man-hour and to shorten a designing period by ranking LSI terminals in terms of the allowance of signal delay time and changing first positions of the terminals with the highest allowances. CONSTITUTION:The position of the LSI terminal is divided into n-blocks. Such decision is made to which block among the plural divided blocks the LSI terminal on a logical path troubled in terms of signal delay time is moved in order to obtain a minimum rectangular distance between parts. Then the LSI terminals in each block are ranked in terms of the allowance of signal delay time. The terminal on the defective path is replaced with the terminal with the highest allowance in the sense of signal delay time in the block with the minimum rectangular distance between part terminals on the defective path. Cell arrangement and wiring processing are done again, and signal delay time is checked. At that time, if the defect is not sorted out, the position terminal is replaced with the terminal with top priority in another block, and the optimum terminal position is determined by checking signal delay time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an LSI terminal position determination method, and in particular to an LSI terminal position determination method.
This paper relates to an optimal terminal position determination method for a synchronous logic circuit in a printed circuit board equipped with a synchronous logic circuit.

[Conventional technology]

Conventionally, systems such as computers are constructed by mounting a plurality of parts such as LSIs or ICs on a printed circuit board and connecting the plurality of printed circuit boards on which the parts are mounted. In such a system configuration, there are a logical design and an implementation design.

In logic design, a designer designs the logic of each LSI, creates a logic circuit model on a simulator, inputs a test pattern, and observes the operation. This simulator is generally implemented using software on a computer, but
Recently, dedicated hardware logic simulation machines have appeared to increase speed.

Based on the logic information obtained in the logic design described above, a mounting design is started for arranging parts such as LSI on a printed circuit board. However, since LSI terminal position determination is done by the LSI alone, if the ILS is mounted on a printed circuit board and wiring is done between the LSI and LS'I or between the IC and LSI, synchronization will occur. In the case of logic circuits that operate normally, signal delay time defects may occur.

A logic circuit that operates synchronously is configured as shown in FIG. 4, for example. Here, after the signals of the front-stage latches 40 and 41 are outputted by the clock T, they are propagated through the combinational circuit 42 and stored in the rear-stage latches 43 and 44 by the clock T. Front stage latch 40.41 and rear stage latch 43.44
The relationship between the clock signals input to is as shown in FIG. The signal delay time when the signal output from the front-stage latch 40.41 propagates through the combinational circuit 42 and arrives at the rear-stage latch 43.44 must be smaller than the reference value D2. If the signal delay time is greater than D2, the second logic circuit will malfunction, and it is necessary to design the signal delay time to within D2.

Additionally, as a means to prevent the above-mentioned signal delay time failure, L
There is a method of shortening the wiring length without changing the SI terminal position. As an example of this kind ('ma.

It is known that the wiring length is shortened by adding diagonal patterns to the conventional wiring pattern, which is only in the X and Y directions (FUJITSU 1986-
(See March issue rFAcOM M-780 Development DA System pp, 135-139).

[Problems to be Solved by the Invention] In the conventional LSI terminal position determination method described above, if a signal delay time failure occurs in a logic circuit on a printed circuit board on which an LSI is mounted, the terminal position of the mounted LSI is changed. death,
The length of wiring connecting LSIs may be shortened. Positioning of LSI terminals on a printed circuit board in order to increase the length of the LSI interconnection lines has only been done manually and requires a large amount of manual labor. Then, the wiring length on the printed circuit board was manually positioned to be as short as possible. However, this method has the problem that it requires a large amount of man-hours to manually determine the terminal positions of the LSI, and also does not take into account the signal delay time that is affected by the terminal positions.

The purpose of the present invention is to solve such conventional problems and to
If a signal delay time defect occurs on a printed circuit board equipped with I, it is possible to optimize the placement of LSI terminals with minimal logic changes, reducing design man-hours.

The second objective is to provide an LSI terminal position determination method that can shorten the design period.

[Means for solving problems]

In order to solve the above problems, the present invention calculates the signal delay time of the logic path between the component terminals using a simulator or the like on a printed circuit board on which components such as LSIs and ICs whose mounting locations are predetermined are mounted. , If the signal delay time exceeds the standard value, from the above signal delay time calculation results, so that the wiring length connecting the component terminals is the shortest,
Rank LSI terminals by signal delay time margin,
The terminal position is exchanged starting from the terminal with the larger margin, and the LSI
The feature is that the terminal placement position is determined.

[Effect]

If a signal delay time defect occurs on a printed circuit board equipped with parts such as LSIs, the way to eliminate the signal delay time defect without changing the logic is to first shorten the wiring length between the parts. There is a method to shorten the wiring length even if the LSI placement position is changed, but changing the LSI placement position has a large effect on the mutual signal delay time. Therefore, in the present invention, by changing the terminal positions of the LSI without changing the layout of the LSI, the wiring length between components can be made as short as possible, and signal delay time defects can be resolved without changing the logic.

[Example] Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a terminal position changing system showing one embodiment of the present invention.

In Figure 1, 11 is an LSI (hereinafter referred to as an IC).
A design file that stores logical information such as connection information between a bin (terminal) with an LSI and a bin (terminal) with an LSI;
12 is the placement information of each LS■ on the printed circuit board before changing the terminal position, each LS x'o>terminal position information, LSI-L
12' is a design file that stores mounting information such as wiring information between SIs, 12' is a design file that stores mounting information after terminal position changes, and 13 is a terminal position change system that performs position change processing of LSI terminals or C terminals. be. Here, input design file (implementation information) 12 and output design file 12
' are the same, only the terminal position has been updated.

FIG. 2 is a processing flowchart of the terminal position changing system of FIG. 1. The terminal position changing process will be explained below with reference to FIG.

The logic information of design file 1 and the mounting information of design file 12 are input to the terminal position change system 13, and the signal delay time of the synchronization circuit on the printed circuit board on which LSI etc. is mounted is calculated, and signal delay time defects are detected. Suppose this occurs.

First, the terminal positions of the LSI are changed so that the number of processing procedures is reduced.
Divide the LSI terminal into blocks, and decide which block should change the terminal position of the LSI terminal on the logical path where the signal delay time is defective so that the rectangular distance between the parts will be the shortest ( Step 201). On this occasion,
The component terminal position on one side is fixed, and the component quantity rectangular distance for determining the block position to be changed is between the block center position and the LSI terminal on the defective path.

Next, all LSI terminals in each block are ranked in descending order of signal delay time (step 202). The terminal on the defective path is replaced with the terminal with the highest signal delay time margin rank in the block where the rectangular distance between component terminals on the defective path is the shortest (step 203
). Thereafter, the cell placement and wiring within the LSI are redone (step 204), and the signal delay time is checked (step 205). At this time, if the defect has not been resolved, the terminal position to be replaced is exchanged with the highest rank terminal in another block, and the optimum terminal position is determined while checking the signal delay time as before.

Thereafter, the mounting information file in which the terminal position has been changed is updated (step 206).

In this way, after the processing of one LSI is completed, the other LSI
Processing will proceed to . Thereby, signal delay time defects can be eliminated as much as possible by changing the terminal positions of the LSI.

FIG. 3 is a diagram showing a specific example for explaining the LSI terminal position determination method of the present invention. Hereinafter, terminal position determination will be explained using this specific example.

In FIG. 3(a), it is assumed that the front-stage latch and rear-stage latch paths indicated by F and -F are paths with defective signal delay times. On the other hand, the wiring lengths connecting LSII and LSI2 are P, -P,
The terminals are located far apart from each other. Therefore, the terminal positions of P and P are changed using the following method so that the wiring length between P and -P is the shortest.

First, fix the terminal position of LSI2, and
First, the terminal positions are divided into n blocks as shown in FIG. 3(b). Next, the center coordinates and LS of the divided blocks
A block having the shortest rectangular distance from terminal P of I2 is determined. Assuming that the block shown in FIG. 3(b) is determined, the signal delay time margin is determined for each terminal within the block and ranked. As a result, the highest rank terminal in b and the LSII terminal P are exchanged. The printed circuit board after replacement becomes as shown in FIG. 3(c). At this stage, cell placement and wiring within the LSII is executed, and then wiring processing on the printed circuit board is executed. Thereafter, the signal delay time is checked again to confirm the validity of the logic operation after the terminal positions have been exchanged. Here, if the path failure indicated between F and -F has not been resolved, the terminal position of LSII is fixed, and the terminal position exchange process moves to LSI2. The same processing as that performed on the LSII is performed on the LSI2, and as a result, the terminal position P2 of the LSI2 is determined as shown in FIG. 3(d).

Through the above processing, in the path of F, -F.

The wiring length connecting LSII and LSI2 can be minimized, and signal delay time defects can be eliminated as much as possible.

In this way, in this embodiment, the designer minimizes the signal delay time rate h check in logic changes that require consideration by the designer, and reduces signal delay time defects as much as possible by shortening the wiring length. Since it is possible to solve the problem without thinking about it, it is possible to significantly shorten the design man-hours and design period.

〔Effect of the invention〕

As explained above, according to the present invention, when a signal delay time failure occurs on a printed circuit board equipped with an LSI, it is possible to optimally arrange LSI terminals with minimal logic changes, thereby reducing design man-hours and design period. It will be possible to shorten it.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a terminal position changing system showing an embodiment of the present invention, FIG. 2 is a flowchart showing the processing of the terminal position changing system of FIG. 1, and FIG. 3 is an LSI terminal position determination method of the present invention. FIG. 4 is a configuration diagram of a synchronous logic circuit, and FIG. 5 is a timing chart showing the operation of FIG. 4. 11: Design file (logical information), 12, 1.2' design file (implementation information), 13: Terminal position change system. Figure 2 Figure 3 Figure 3 Figure 4 Figure 5 (Standard 1 item)

Claims (1)

[Claims] 1. As a result of calculating the signal delay time of the logic path between the component terminals using a simulator, etc. on a printed circuit board on which components such as LSI and IC are mounted in a predetermined mounting location, the signal delay time exceeds the standard value. Depending on the
In order to minimize the wiring length between the component terminals, rank the LSI terminals based on the signal delay time calculation results above and replace the terminal positions starting with the terminals with the highest margin. , an LSI terminal position determination method characterized by determining the placement position of LSI terminals.