JPH04172564A - Method for inspecting layout pattern - Google Patents

Abstract

PURPOSE:To reduce preparation and to increase efficiency by storing a data base at the time of the completion of the inspection at a cell level for each cell and unnecessitating the generation and extraction necessary for inspecting the connection of the inside of a cell with an external wiring. CONSTITUTION:For the cell where the test at the cell level is completed, a data base 7 at the time of the completion is stored in a cell information 8 for each cell. The comparison inspection is performed by extracting a layout pattern data 1 and the device information, circuit connection information, etc., of a circuit diagram 2 via a layout inspecting module 5 with the use of a rule 4 treating this information as the information of a hierarchical cell and comparing and inspecting the layout pattern data 1 other than the hierarchical cell and the device information, circuit connection information, etc., of the circuit diagram data 2. As for the hierarchical cell, the connection of the inside of the hierarchical cell with the external wiring is tested with the use of the cell information stored in the cell information storage module 8 and an inspection result 6 is generated. Thus, the reduction of the work and the increase of efficiency can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a design verification method for layout pattern data of a semiconductor integrated circuit.

[Conventional technology]

Figure @4 is a block explanatory diagram showing a conventional layout pattern verification method.

In the figure, +II#-1t layout pattern data, I! I#: 1 circuit diagram data, 13) is cell external connection information generated or extracted from layout pattern data + 11, (4) is hierarchical cell information for cells that perform hierarchical processing on cell external connection information (3) In addition, layout butter/data for parts other than this layer cell... and circuit diagram data 1! ) verification rules for performing comparative verification of device information, circuit connection information, etc., 1111 extracts device information 1 circuit connection information, etc. according to the layout pattern data... and circuit diagram data (21 to verification rule 14). 16) Comparative Verification Row - For cells in the 1st layer, the cell's external connection information +31 is used to verify the connection between the 1st floor 1st layer leakage and external wiring, and further generate verification results.16) is the verification result generated by layout verification module Jl.

Next, the operations 1C and IIh will be explained using the flowchart shown in FIG.

First, the layout pattern data I11 of step 5
The next cell's external i connection information (31) generated or extracted in step 2 is
The layout verification module 61 uses the verification rule (4) to compare and verify the layout pattern data (1) of the parts other than the hierarchical cells and the circuit diagram data (!) of step 8. Extract device information, circuit connection information, etc. from pattern data II+ and circuit diagram data +21, compare and verify them (step 4), and extract cell external connection information til for hierarchical cells.
Verify the connection between the 1st layer cell and external wiring using +.
Furthermore, a Vc verification result 161 is generated (steps 5 and 6).

[Problem to be solved by the invention]

Since the conventional layout pattern verification method is configured as described above, when performing one-layer layout pattern verification, the external connection information of the cell necessary for verifying the connection between the internal wiring of the hierarchical cell and the external wiring.

The layout pattern must be generated or extracted from the layout pattern data, and this generation and extraction is done manually, which is time-consuming, and errors may occur during the generation and extraction, which reduces the efficiency of the preparation work until the layout pattern verification is executed. The problem was that it was extremely bad.

This invention was made to solve the above-mentioned problems, and it is possible to reduce the preparation work for generating or extracting the external connection information of the cell necessary for verifying the connection between the inside of the cell and the external wiring. The purpose is to obtain a layout pattern verification method.

[Means to solve the problem]

The layout pattern verification method according to the present invention applies to cells for which cell level verification has been completed.

The database at the time of completion is stored in the cell information storage module for each cell, and this cell f'llll! 1 is treated as the information of the cell C (layer cell) that performs hierarchical processing, and further uses verification rules to compare and verify the layout pattern data of parts other than the layer cells and the device information 1 route connection information of the circuit diagram data. Then, a layout verification module performs comparative verification, and for hierarchical cells, the connection verification between the inside of the first-level cell and the external wiring is performed using the external S connection information of the cell stored for each cell. This is what I did.

[Effect]

The layout pattern verification method according to the present invention stores a database at the time of completion for each cell in a cell fill storage module for cells for which verification has been completed in a cell repeater, and uses this stored cell information to check the internal and external wiring of the cell. Connection verification is performed, and further comparison verification is performed regarding layout pattern data of parts other than cells and device information, 5-route connection information, etc. of circuit diagram data. This eliminates the need to generate or extract external connection information within a cell from layout pattern data.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

Fig. wJ1 is a block explanatory diagram showing a layout pattern verification method that is an embodiment of the present invention. , +81i-1 A database of cells that have completed cell level verification (7) A cell information storage module that stores each cell (41 is a cell information storage module (8)
The cell information stored in is treated as the information of cells that perform hierarchical processing (hierarchical cells), and furthermore, the layout pattern data 111 of the parts other than the hierarchical cells and the device information of the circuit diagram data + 21 are compared and verified. Verification rules for +611j layout pattern data 111 and circuit diagram data (!I to verification rule 14)
Accordingly, the device information 1 route connection information etc. are extracted and compared and verified.For layer cells, the connection between the inside of the 9 layer cells and external wiring is verified using the cell information stored for each cell.
This is a verification result generated by a +61i layout verification module ll11, which is a layout verification module that generates a Vc verification result.

Next, the operation will be explained using the flowchart shown in FIG.

First, in step 1, for cells that have been completely verified at the cell level, the database (7) at the time of completion is stored in the cell information storage module (8) for each cell.Step 3) This stored cell information is subjected to hierarchical processing ( Furthermore, using the verification rule 141 for comparing and verifying the layout pattern data ill of step 8 and the circuit diagram data of step 21 (device information 1 route connection information of step 21, etc.) , Layout verification module, 6), layout pattern data (!
1 and circuit diagram data (2), device information, 1-route connection information, etc. are extracted and compared and verified (step 5), and the 1-jit layer cell is stored in the cell refresh memory module (8) and the next cell information is stored. The connection verification between the inside of the first layer cell and the external wiring is performed using the method, and the verification result 1B) is generated (steps 6 and 7).

FIG. 8 is an explanatory diagram of external connection information of cells in the layout pattern data of FIG. 1. In the figure, field is layout pattern data, I9) is hierarchical cell, +
lQl is external connection information of the cell, and 1JII is external wiring.

In other words, in hierarchical layout pattern verification, hierarchical cell (9)
In order to verify internal and external wiring, layer cell (9)
External connection information 1101 such as internal wiring information and pin information is required, and this information was realized in the main implementation by having a database at the time when cell level verification was completed.

〔Effect of the invention〕

As described above, according to the present invention, by storing the base at the time when verification is completed at the cell level for each cell, the base at the time when verification is completed at the cell level is stored. There is no need to generate or extract cell information.

This has the effect of reducing the preparatory time required to perform hierarchical layout pattern verification and improving the efficiency of design verification of layout pattern data.

[Brief explanation of drawings]

FIG. 1 is a block explanatory diagram of a layout pattern verification method according to an embodiment of the present invention, FIG. 2 is a flowchart showing the operation of FIG. FIG. 4 is a block explanatory diagram of a conventional layout pattern verification method. FIG. 6 is a flowchart showing the operation of FIG. 4. In the figure, 111 is layout pattern data. 12) is the circuit diagram data, (4) is the verification rule, l11)
#-t layout verification module, 161q verification result,
17) is a database of cells that have been fully verified at the cell level. t81t1 cell information storage module, (91 is a hierarchical cell, +101 is external connection information, and 11υ is external wiring +II. In Figure 1, the same reference numeral indicates the same or corresponding part t.

Claims (1)

[Claims] For cells that have completed cell level verification, there is a cell information storage module that stores a database at the time of completion for each cell, and a cell that performs hierarchical processing on this stored cell information is treated as a hierarchical cell. A verification rule for comparing and verifying device information, circuit connection information, etc. of layout pattern data and circuit diagram data of other parts, the comparison verification is performed using this verification rule, and the hierarchical cells are stored for each cell. Using cell information, verify the connection between the hierarchical cells and external wiring,
A layout pattern verification method further comprising a layout verification module that generates and stores verification results.