JPH0862820A - Formation of exposure data - Google Patents

Abstract

PURPOSE: To make it possible to freely set shapes of frames in compliance with patterns and to surely avert generation of the patterns crossing these frames. CONSTITUTION: This method for forming exposure data made into a hierarchical structure includes a first step for setting the first frame to be completed in one hierarchy, a second step for extracting the specific patterns belonging to one hierarchy and crossing the first frame, a third step for setting the second frame around the extracted specific patterns and a fourth step for setting the third frame by combining the first frame and the second frame.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure data generation method, and more particularly to an exposure data generation method having a hierarchical structure. The amount of exposure data has become extremely huge as the scale and density of semiconductor integrated circuits increase. For example, in the case of a 4M bit memory, it is about 8 in P (poly) layer.
The number of patterns is 10 million, which is equivalent to about 30 windings of a magnetic tape (MT). This means that the conventional method of performing graphic processing after performing the expansion processing has already reached its limit, and some kind of device for reducing the exposure data amount is required.

[0002]

2. Description of the Related Art Some semiconductor integrated circuits have a highly repeatable data structure. A memory is typically provided with a large number of memory cells corresponding to the storage capacity, but these cells have the same structure. Therefore, using this data structure, processing is performed in hierarchical units,
If the exposure data itself has a hierarchical structure, the amount of exposure data can be significantly reduced.

FIG. 13A shows a DRAM (dynamic random).
access memory) is a hierarchical structure diagram. A is a parent structure of the entire chip, and this parent structure A includes a structure B of a memory cell having a predetermined capacity and a structure C of a peripheral circuit. Adjust the number of structures B to D
Although the capacity of the entire RAM is secured, it is not necessary to make the lower layer (structure D of a memory cell of several bits) subordinate to all structures B. This is because the structure B has the same structure altogether, and if the lower layer is subordinate to only the representative structure B, the other structures B can be obtained by the mirror of the representative structure B.
Therefore, the lower layer does not have to be subordinate to all the structures B, and the amount of exposure data can be significantly reduced.

By the way, in such graphic data processing in units of layers, it is necessary to set a frame (also called a frame) for distinguishing layers. For example, in the example of FIG. 13B, a frame U of an upper layer (chip layer), a frame M of a middle layer (schedule layer) and a frame L of a lower layer (group layer).
Are set respectively.

[0005]

However, in such a conventional exposure data generation method, since the shape of the frame is a simple rectangular shape, a pattern that crosses the frame may occur. In this pattern portion, There is a problem that the exposure accuracy is impaired. 14 and 15 are explanatory diagrams of conventional defects. In FIG. 14, 5 to 13 are patterns such as semiconductor element figures having the same area, 14 is a frame,
Eight patterns 5, 6 except one pattern 9 in the center
7, 8, 10, 11, 12 and 13 cross the frame 14. For simplification of description, each of the patterns 5, 7, 11 and 13 that cross the corner portion of the frame 14 has a quarter of its area located inside the frame 14 and crosses the straight portion of the frame 14. It is assumed that half of the area of each of the patterns 6, 8, 10 and 12 is located inside the frame 14. Frame 1
The inside of 4 is the exposure area.

Since the exposure amount exponentially increases as the irradiation area (pattern area) decreases, in the example of FIG. 14, the exposure amount for the central pattern 9 is larger than that of the frame 14. Exposure for each pattern 5, 7, 11 and 13 across the corner of the
Patterns 6, 8, 10 and 12 across the straight line portion of 4
The amount of exposure to is explosively increased.

Therefore, the transfer size of the finally obtained exposure pattern to the resist is as shown in FIG.
Compared with the size of the central pattern 9, the size of each pattern 5, 7, 11 and 13 that crosses the corner portion of the frame 14, and each pattern 6 that crosses the straight portion of the frame 14,
The size of 8, 10 and 12 increases significantly.
This is because the amount of exposure to the pattern portion that crosses the frame 14 is enormous, so that the scattering of electrons on the resist increases.

[0008]

[Purpose] Therefore, an object of the present invention is to allow the shape of a frame to be freely set in accordance with a pattern, thereby reliably avoiding the generation of a pattern that crosses the frame.

[0009]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention is a method for generating hierarchically structured exposure data as shown in the principle diagram of FIG. A first step of setting one frame, a second step of extracting a specific pattern belonging to the one hierarchy and crossing the first frame, and a second step around the extracted specific pattern. The method is characterized by including a third step of setting a frame and a fourth step of setting the third frame by combining the first frame and the second frame.

Alternatively, in the fourth step, two intersections of the first frame and the second frame are obtained, and a line segment connecting the two intersections and a second segment inside the first frame are obtained. The line segment of the frame is deleted, and the line segments of the first frame and the second frame are connected to each other to set the third frame. Or, setting a fourth frame that is completed within the layer one above the one layer,
The second step, the third step and the fourth step are executed in an area between the fourth frame and the first frame.

[0011]

In the present invention, all patterns belonging to one layer are designated by one frame (third frame). Therefore, since there is no pattern that crosses the frame, the transfer size of the exposure pattern can be optimized and good exposure accuracy can be obtained.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. 2 to 6 are views showing a first embodiment of the exposure data generating method according to the present invention. In FIG. 2, 20-2
8, 30 to 39 are, for example, element patterns (hereinafter referred to as “patterns”) of a semiconductor element that constitute one cell array, and nine patterns shown by hatching are those registered in the lowest hierarchy, and ten surrounding patterns. Pattern is part 1
It is registered in the upper hierarchy.

FIG. 3 is an explanatory diagram of a step (first step) for setting the first frame. 40 is a cell array frame,
41 is a 1st frame. The first frame 41 is set so as to be completed within one layer (here, the lowest layer) (in other words, not to extend over two or more layers). The first frame 41 designates nine patterns 20 to 28 belonging to the lowest hierarchy by enclosing them within the frame, but as shown in the figure, the patterns 20 to 28 and the pattern 3 are designated.
When the numbers 0 to 39 are interleaved with each other, some patterns (patterns 20, 21, 22, 2 in the figure)
(3, 25, 26, 27 and 28) inevitably partially protrudes outside the frame. That is, the illustrated pattern 2
0, 21, 22, 23, 25, 26, 27 and 28 are
The pattern crosses the first frame 41.

FIG. 4 is an explanatory diagram of a step of extracting a specific pattern (second step) and a step of setting a second frame (third step). The specific pattern is a pattern that crosses the first frame 41, and the patterns 20, 21, 22, 23, 25, 26, 27, and 28 correspond to them in the drawing. The second frame is set around each of these specific patterns. FIG. 4B is a diagram showing one of the specific patterns (typically the pattern 20) and the second frame 50 set around the specific pattern. Here, the pattern 20 is enlarged at a predetermined ratio and the enlarged pattern outline (broken line) after the enlargement is used as the second frame 50, but the invention is not limited to this. In short, the second frame 50 having an appropriate size may be set around the pattern 20. For example, the shape of the second frame 50 may be different from that of the pattern 20.

FIG. 5 is an explanatory view of the step (fourth step) of setting the third frame. 20, 21, 22, 2
3, 25, 26, 27 and 28 are patterns (specific patterns) that traverse the first frame 41, and these patterns are surrounded by the second pattern by the above steps.
Frames 50, 51, 52, 53, 55, 56, 57 and 5 of
8 is set. The third frame is set by a combination of the first frame 41 and these second frames. Figure 5
(B) is one of the specific patterns (typically pattern 2
It is a figure which shows the combination of the 2nd frame 50 and the 1st frame 41 set around 0). In this figure, the first
Only the outer side (outside of the frame) of the frame 41 of FIG.
The inside of 1 (inside the frame) is omitted. The second frame 50 is set around a specific pattern, that is, the pattern 20 that crosses the first frame 41. Cross. Figure 5
Reference signs A and B in (b) are the two intersections. Third
The unnecessary frames are deleted from the first frame 41 and the second frame 50, and the first frame 41 and the second frame 50 after the deletion are connected to each other. Specifically, the line segment 41 ′ that connects the two intersections A and B from the first frame 41 is deleted, and the line segment that enters the frame of the first frame 41 from the second frame 50. (Omitted in the figure) is erased, and the erased first frame 41 and second frame 50 are joined together.

In FIG. 5 (b), 60 is the third frame set in this way, and this third frame 60 shows one of the specific patterns (pattern 20), but the other. The same applies to the specific pattern of. Figure 6
FIG. 7 is an overall shape diagram of a third frame 60. When compared with FIG. 5A, the third frame 60 has a plurality of convex portions 61 to 70 protruding outside the frame of the first frame 41, and these convex portions are
It can be seen that the shape is freely formed along the outer shape of the specific pattern.

Therefore, according to this embodiment, regardless of the shapes of the patterns included in one layer, it is possible to set the third frame 60 of any shape capable of designating all of the patterns. It is possible to surely avoid the generation of a pattern that traverses the exposure pattern, to optimize the transfer size of the exposure pattern to the resist, and to obtain excellent exposure accuracy.

The cell array frame (corresponding to the fourth frame) 40 surrounding the first frame 41 is not particularly essential in the above description, but by using this cell array frame 40, useless graphics are obtained. The advantage is that no processing is required. That is, as is apparent from FIG. 5, the third frame 60 has a plurality of convex portions 61 to 70, and these convex portions are located between the first frame 41 and the cell array frame 40. Is provided by the second frame 50 in the area sandwiched between. Therefore, the setting process of the second frame 50 in the third step and the third frame 6 in the fourth step are performed.
If the setting processing of 0 and the like is limited to the above area, useless graphic processing, that is, graphic processing in the frame of the first frame 41 can be omitted, and the processing efficiency can be improved.

7 to 12 are views showing a second embodiment of the exposure data generating method according to the present invention, which is an example using a cell array frame (fourth frame). In FIG. 7, a large number of patterns including diagonal portions are element patterns of, for example, semiconductor elements that form one cell array, and each pattern shown by hatching (see FIGS. 7B and 7C) is in the lowest hierarchy. The registered patterns and the other patterns (FIGS. 7D and 7E) are registered in the next higher layer.

FIG. 8 is an explanatory diagram of a step (first step) of setting the cell array frame and the first frame. 80
Is a cell array frame (fourth frame), and 81 is a first frame.
The first frame 81 is set so as to be completed within one layer (here, the lowest layer) (in other words, not to extend over two or more layers), and the cell array frame 8
0 is set so as to surround the first frame 81 and be completed within the layer one level above.

The first frame 81 designates each pattern (hatching pattern) belonging to the lowest hierarchy by enclosing it within the frame, but in the example shown in the figure, the number of hatching patterns Or (here, pattern 82-
90) crosses the first frame 81. FIG. 9 is an explanatory diagram of a step (second step) of extracting a specific pattern. The specific pattern is a pattern that traverses the first frame 81, and in the figure, the patterns 82 to 90 correspond thereto. In this embodiment, the cell array frame 80 and the first frame 8
The extraction processing of the specific pattern is performed only within the region 91 sandwiched between the 1's. That is, 82a, 82b,
83a, 84a, 85a, 86a, 87a, 88a, 8
9a and 90a are the extracted specific patterns, and these are the patterns 82- that cross the first frame 81.
Of 90, it is a partial pattern located in the area 91.

FIG. 10 is an explanatory diagram of a step (third step) for setting the second frame. The second frame is set around each of the specific patterns, but in this embodiment, the second frame is limited to the area 91 sandwiched between the cell array frame 80 and the first frame 81. Set the frame. That is, reference numerals 92 to 101 denote second frames, respectively, and these are patterns 82 to 90 that cross the first frame 81.
It is set around the partial pattern located in the area 91. In addition, the shape of the second frame may be, for example, obtained by enlarging a partial pattern and matching the outline of the pattern after the enlargement.

FIG. 11 is an explanatory diagram of a step (fourth step) for setting the third frame, and FIG. 12 is a diagram in which the third frame is assigned to an actual layout. 102 is a third frame, and the third frame 102 is set by combining the first frame 81 and the second frames 92 to 101. Specifically, unnecessary line segments of the first frame 81 are erased, and the erased first frame 81 and the second frames 92 to 101 are connected and set. The unnecessary line segment of the first frame 81 is the first frame 81 for each of the second frames 92 to 101.
Is a line segment that connects between two intersections (see, for example, symbols a and b in FIG. 10) that intersect with.

Therefore, according to the present embodiment as well, it is possible to set the third frame 102 of any shape capable of designating all of the patterns regardless of the shapes of the patterns included in one layer. The same effect as the example can be obtained, and since graphic processing limited to the area 91 is performed, useless processing can be omitted and processing efficiency can be improved.

[0025]

According to the present invention, all the patterns belonging to one layer can be designated by one frame (third frame).
Therefore, it is possible to reliably avoid the generation of a pattern that crosses the frame, optimize the transfer size of the exposure pattern, and obtain good exposure accuracy.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a hierarchical pattern diagram of the first embodiment.

FIG. 3 is an explanatory diagram of a first step of the first embodiment.

FIG. 4 is an explanatory diagram of a second step and a third step of the first embodiment.

FIG. 5 is an explanatory diagram of a fourth step of the first embodiment.

FIG. 6 is an explanatory diagram of a third frame of the first embodiment.

FIG. 7 is a hierarchized pattern diagram of the second embodiment.

FIG. 8 is an explanatory diagram of a first step of the second embodiment.

FIG. 9 is an explanatory diagram of a second step of the second embodiment.

FIG. 10 is an explanatory diagram of a third step of the second embodiment.

FIG. 11 is an explanatory diagram of a fourth step of the second embodiment.

FIG. 12 is an allocation diagram of a third frame of the second embodiment.

FIG. 13 is a hierarchical structure diagram of a DRAM.

FIG. 14 is a diagram showing a state where a pattern that crosses a frame is generated.

FIG. 15 is a diagram illustrating a defect of a pattern that crosses a frame.

[Description of Reference Signs] First step Second step Third step Fourth step A, B: Intersection points 20, 21, 22, 23, 25, 26, 27, 28: Specific pattern 40: Cell array frame ( Fourth frame) 41: First frame 50, 51, 52, 53, 55, 56, 57, 58: Second frame 60: Third frame a, b: Intersection 80: Cell array frame (fourth frame) Frame) 82 to 90: Specific pattern 81: First frame 92 to 101: Second frame 102: Third frame

Claims (3)

[Claims] 1. A method of generating hierarchically structured exposure data, comprising: a first step of setting a first frame that is completed within one layer; and a step of setting the first frame that belongs to and belongs to the one layer. A second step of extracting a specific pattern to traverse, a third step of setting a second frame around the extracted specific pattern, and a third step of combining the first frame and the second frame. And a fourth step of setting the frame of the exposure data generation method. 2. The fourth step obtains two intersections of a first frame and a second frame, and a line segment connecting the two intersections and a second segment inside the first frame. The line segments of the frame are erased, and the line segments of the first frame and the second frame are joined to form the third line.
The exposure data generation method according to claim 1, wherein the frame is set. 3. A fourth frame that is completed within a layer one level above the one layer is set, and the second step is performed in a region between the fourth frame and the first frame. 2. The exposure data generating method according to claim 1, wherein the third step and the fourth step are executed.