JPH10172876A - Method for compressing eb data - Google Patents

Method for compressing eb data

Info

Publication number
JPH10172876A
JPH10172876A JP33336796A JP33336796A JPH10172876A JP H10172876 A JPH10172876 A JP H10172876A JP 33336796 A JP33336796 A JP 33336796A JP 33336796 A JP33336796 A JP 33336796A JP H10172876 A JPH10172876 A JP H10172876A
Authority
JP
Japan
Prior art keywords
block
pattern
data
compressed
patterns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33336796A
Other languages
Japanese (ja)
Inventor
Mitsuki Tsutsumida
光起 堤田
Toshio Suzuki
俊夫 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP33336796A priority Critical patent/JPH10172876A/en
Publication of JPH10172876A publication Critical patent/JPH10172876A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To ease constraints of design by performing a compressing method focusing attention on level structure (block) with which compression efficiency is higher. SOLUTION: A compressing method is composed of the following processes: 1) to specify a block to be compressed; 2) to detect the state of the black to be compressed placed on a chip and patterns entered into the block; 3) to take 'OR' of entered patterns in each position of the object to be compressed; and 4) to make 'SUB' of the entered patterns obtained at the process 3) from the block graphics. Graphics which are not overlapping outside entered patterns are automatically extracted. The above functions can be realized by a program for forming and processing EB data.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明はEBデータ圧縮方法
に関する。
The present invention relates to an EB data compression method.

【0002】[0002]

【従来の技術】LSIチップの作成では、論理設計→回
路設計→レイアウトパターン設計と設計を行ない、出来
上がったパターンをマスクパターンにして、シリコン基
盤上に転写し、実際のLSIにする。EBデータは、出
来上がったパターンをマスクパターンにするために、E
B描画装置を入力するためのデータである。(図1参
照) EBデータは、細密なLSIパターンをEB描画装置で
描画できる矩形の集合として表現するため、一般的な大
容量になり、かつその作成には大量の図形演算を行なう
必要があるため多大な計算機処理時間を必要とする。
2. Description of the Related Art In the production of an LSI chip, logic design → circuit design → layout pattern design and design are performed, and the completed pattern is used as a mask pattern and transferred onto a silicon substrate to form an actual LSI. The EB data is used to convert the completed pattern into a mask pattern.
This is data for inputting a B drawing device. (Refer to FIG. 1.) Since EB data represents a fine LSI pattern as a set of rectangles that can be drawn by an EB drawing apparatus, the EB data has a general large capacity, and requires a large amount of graphic operations to create it. Therefore, a large amount of computer processing time is required.

【0003】特にその傾向は大規模メモリ系のLSI
(DRAM)等で顕著であり、これを削減するため、同
じ形状のパターンを切り出し、1個の切り出しパターン
とその配置位置をEBデータとして出力することで、デ
ータ量と同時にその作成時間を短縮することが行なわれ
ている。これをデータ圧縮と呼ぶ。(図2参照) 従来からの手法については、以下の二つの方法がある。
[0003] In particular, the tendency is large-scale memory LSI.
(DRAM) and the like. In order to reduce this, a pattern having the same shape is cut out, and one cutout pattern and its arrangement position are output as EB data, thereby reducing the data amount and the creation time. Things are going on. This is called data compression. (Refer to FIG. 2) As the conventional method, there are the following two methods.

【0004】(1)データの階層構造に注目してデータ
を圧縮する方法、 レイアウト設計時に、複数箇所に配置した同じパターン
の固まり(以下、ブロック)を圧縮の単位に指定し、圧
縮する方法。
(1) A method of compressing data paying attention to the hierarchical structure of data, and a method of compressing data by designating a block (hereinafter referred to as a block) of the same pattern arranged at a plurality of locations in a layout design.

【0005】(2)個々の図形パターンに着目し、同じ
パターンが繰り返し使用されている場合、これを圧縮単
位にして圧縮する方法。
(2) A method in which attention is paid to individual graphic patterns, and when the same pattern is used repeatedly, this is used as a compression unit and compressed.

【0006】(1)と(2)の方法について比較する
と、(1)の方法では、レイアウト階層に着目してデー
タ圧縮するため、圧縮単位の指定が容易であること。大
面積のパターンを一括して圧縮できるため、圧縮の効率
が高いことが利点として上げられる。
Comparing the methods (1) and (2), in the method (1), since the data is compressed by focusing on the layout hierarchy, it is easy to specify the compression unit. As a large area pattern can be collectively compressed, high compression efficiency is an advantage.

【0007】一方欠点としては圧縮するブロックに接続
するパターンがある場合(電子回路であるため通常はあ
る。)はその部分のパターンは場所に拠って異なるた
め、圧縮できず(図3、参照)、圧縮する領域をブロッ
クの一部に制限し、その部分には外部のパターンが入ら
ないように設計段階で制限する設計制約必要になる。
On the other hand, as a drawback, when there is a pattern connected to the block to be compressed (usually because it is an electronic circuit), it cannot be compressed because the pattern of that part differs depending on the location (see FIG. 3). Therefore, it is necessary to limit the area to be compressed to a part of the block, and to restrict the area at the design stage so that an external pattern does not enter the block.

【0008】一方(2)の場合は、同じパターンを自動
認織するため設計段階での制約は少ないが、同じパター
ンを自動認識に多大の計算物量を必要とし、特にパター
ンが複雑になるに従ってその物量増える。そのため現実
的には大面積の圧縮は出来ない。また、他のパターンと
重なっている場合も自動認織は難しく現実的にはパター
ンが独立している場合しか扱えない。(図4参照)結果
圧縮率は(1)の方法に対して低くなる。
On the other hand, in the case of (2), since the same pattern is automatically recognized, there are few restrictions at the design stage, but the same pattern requires a large amount of calculation for automatic recognition. The quantity increases. Therefore, a large area cannot be compressed in practice. Also, automatic weaving is difficult when it overlaps with another pattern, and in reality, it can only be handled when the pattern is independent. (Refer to FIG. 4.) As a result, the compression ratio is lower than the method (1).

【0009】[0009]

【発明が解決しようとする課題】そこで本発明は、圧縮
効率の高い階層構造(ブロック)に着目した圧縮方法を
行ないながら、設計制約を緩和することを課題にする。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to relieve design constraints while performing a compression method focusing on a hierarchical structure (block) having high compression efficiency.

【0010】[0010]

【課題を解決するための手段】上記の目的を達成するた
めに、 (1)圧縮対象として、ブロックを指定する。(外部指
定) (2)圧縮対象のブロックをチップ上に配置した状態、
そのブロックに侵入しているパターンを検出する。
In order to achieve the above object, (1) a block is designated as a compression target. (External designation) (2) The state where the block to be compressed is arranged on the chip,
Detect the pattern invading the block.

【0011】(3)圧縮対象への各配置位置での侵入パ
ターンを“OR”取りする。
(3) The intrusion pattern at each position of the compression target is ORed.

【0012】(4)(3)で求めた侵入パターンをブロ
ックの図形から“SUB”する。
(4) The intrusion pattern obtained in (3) is "SUB" from the block figure.

【0013】→外部の侵入パターンと重ならない図形の
自動抽出 以上の機能を実現する。(図4参照) 圧縮ブロックの設計段階で侵入パターンの範囲等を考え
ずパターン設計できる。
→ Automatic extraction of figures that do not overlap with external intrusion patterns The above functions are realized. (See FIG. 4) At the design stage of the compression block, the pattern can be designed without considering the range of the intrusion pattern and the like.

【0014】[0014]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

(1)圧縮対象として、ブロックを指定する。(外部指
定) (2)圧縮対象のブロックをチップ上に配置した状態、
そのブロックに侵入しているパターンを検出し、圧縮対
象への各配置位置での侵入パターンを“OR”取りす
る。
(1) Designate a block as a compression target. (External designation) (2) The state where the block to be compressed is arranged on the chip,
The pattern invading the block is detected, and the intrusion pattern at each position of the compression target is ORed.

【0015】(3)(2)で求めた侵入パターンをブロ
ックの図形から“SUB”する。
(3) "SUB" is performed on the intrusion pattern obtained in (2) from the figure of the block.

【0016】→外部の侵入パターンと重ならない図形の
自動抽出 以上の機能をEBデータ作成処理のプログラムで実現す
る。
→ Automatic extraction of figures that do not overlap with external intrusion patterns The above functions are realized by a program for EB data creation processing.

【0017】[0017]

【発明の効果】本発明により、複雑な外部からの侵入パ
ターンも処理可能する事で、圧縮使用時のパターン設計
を容易にし、かつ高いパターンの圧縮率を実現する。
According to the present invention, it is possible to process a complicated intrusion pattern from the outside, thereby facilitating pattern design when using compression and realizing a high pattern compression ratio.

【図面の簡単な説明】[Brief description of the drawings]

【図1】EBデータ作成処理の説明図。FIG. 1 is an explanatory diagram of an EB data creation process.

【図2】圧縮処理の例の説明図。FIG. 2 is an explanatory diagram of an example of a compression process.

【図3】階層を考慮した圧縮の説明図。FIG. 3 is an explanatory diagram of compression in consideration of a hierarchy.

【図4】パターンを考慮した圧縮の説明図。FIG. 4 is an explanatory diagram of compression in consideration of a pattern.

【図5】本発明の圧縮方法の説明図。FIG. 5 is an explanatory diagram of a compression method according to the present invention.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】LSIチップのマスクパターンをEBで描
画するために用いるEBデータを、パターンレイアウト
設計時の階層構造に従って圧縮し、EBデータの作業時
間、及びEBデータ量を削減することを特徴とするEB
データ圧縮方法。
An EB data used for drawing a mask pattern of an LSI chip by EB is compressed in accordance with a hierarchical structure at the time of pattern layout design, thereby reducing a working time of the EB data and an EB data amount. EB to do
Data compression method.
JP33336796A 1996-12-13 1996-12-13 Method for compressing eb data Pending JPH10172876A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33336796A JPH10172876A (en) 1996-12-13 1996-12-13 Method for compressing eb data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33336796A JPH10172876A (en) 1996-12-13 1996-12-13 Method for compressing eb data

Publications (1)

Publication Number Publication Date
JPH10172876A true JPH10172876A (en) 1998-06-26

Family

ID=18265323

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33336796A Pending JPH10172876A (en) 1996-12-13 1996-12-13 Method for compressing eb data

Country Status (1)

Country Link
JP (1) JPH10172876A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6481002B2 (en) 2000-02-17 2002-11-12 Kabushiki Kaisha Toshiba System and method for compressing LSI mask writing data
JP2005521071A (en) * 2001-07-13 2005-07-14 アプライド マテリアルズ インコーポレイテッド Pattern generation method and apparatus using cached cells of hierarchical data

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6481002B2 (en) 2000-02-17 2002-11-12 Kabushiki Kaisha Toshiba System and method for compressing LSI mask writing data
JP2005521071A (en) * 2001-07-13 2005-07-14 アプライド マテリアルズ インコーポレイテッド Pattern generation method and apparatus using cached cells of hierarchical data

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