JPH0697058A - Method of forming data for electron beam lithography - Google Patents

Abstract

PURPOSE:To form data for lithography rapidly, while preventing missing and overlapping of graphic figures even though assigning processing target regions for a plurality of CPU's, performing parallel processing independently and registering the graphic form for each rectangular region. CONSTITUTION:Graphic figures F10 and F11 contained in a processing target region EA including a subfield 32 are taken in a CPU, and an overlap is removed and a graphic figure F22 is generated. Cutting lines L3 and L4 containing the boundary line of the processing target region EA is generated and the graphic figure F22 is cut off. A graphic figure below the cutting line L4 is deleted, and a graphic figure F37 is created between the cutting lines L3 and L4. A parting line is generated from the apex of the graphic figure F37 normal to the cutting line L4, thereby dividing it into graphic figures F38 to F40. Since part of the graphic figures F39 and F40 are on the external margin and inside the internal margin so that they are cut at the boundary line of the subfield 32 and the graphic figures F39a and F40a are registered in the subfield 32.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of creating drawing data for an electron beam drawing apparatus from graphic data of a mask pattern, and more specifically, dividing an integrated circuit pattern into a large number of processing target areas, and processing each processing target area. To a plurality of CPUs to independently process each processing target area in parallel.

With the recent increase in the size and density of LSIs, there is an increasing demand for shortening the processing time for creating drawing data for an electron beam drawing apparatus. In order to meet this demand, a method of dividing an LSI chip into a plurality of areas and processing each area independently and in parallel is being studied. And
Each area is a square area that can be drawn by electromagnetic deflection in an electron beam drawing apparatus, that is, a large number of subfields 3 obtained by dividing an LSI chip area in a grid pattern as shown in FIG.
It is most desirable to correspond to 0 (area surrounded by a solid line).

Further, in order to draw a large-scale and high-density LSI in a short time, it is better to use an electron beam drawing apparatus of a vector scan system which scans and exposes only a portion where graphic data exists. . However, in the vector scan type electron beam drawing apparatus, a minute figure having a bottom and a height that are both less than a predetermined length cannot be drawn because the electron beam cannot be irradiated, and the accuracy becomes extremely poor. Hinders Therefore, as shown in FIG. 13, a margin M (shown by a broken line) of a predetermined width shown by a broken line is set inside and outside each sub-field 30 with the boundary line as a reference so that a minute figure is generated. I try to prevent it. The outer margin of the subfield 30 is the inner margin of the subfield adjacent to the subfield.

That is, when a figure after graphic processing is registered in a subfield, cutting is performed at the boundary of the subfield without considering a margin, and only a figure completely included in the subfield is registered, so that a minute figure is generated. May occur. For example, when the figures F1 and F2 shown in FIG. 13 are cut at the boundary line of the subfield 30, the figures F11 and F21 are registered as shown in FIG. In this case, the figure F21
Becomes a minute figure.

On the other hand, the judgment at the time of registering the figure after the figure processing in the subfield is set based on the margin inside and outside the subfield. That is, when the graphic is completely contained in the subfield, or when the graphic is within the outer margin and also including the inner margin, the graphic is registered in the subfield. If even part of the figure is outside the margin including the outer margin and inside the margin including the inner margin, the inside figure cut by the boundary line of the subfield is registered in the subfield. .
If the graphic is within the outer margin and outside the inner margin corresponding to a predetermined pair of adjacent boundary lines of the subfield, the graphic is registered in the subfield.

Therefore, for example, figures F1 and F shown in FIG.
Of the two, the figure F2 is excluded from the registration target, and the figure F1
Is registered and is registered in the subfield 30 as shown in FIG. Therefore, the generation of minute figures is prevented.

Therefore, in order to create drawing data for the electron beam drawing apparatus of the vector scan system in a short time, it is indispensable to perform the parallel processing independently for each subfield. Further, in order to create drawing data for a vector scan type electron beam drawing apparatus, a figure is registered in a subfield having a margin in the subfield in order to perform figure processing such that a minute figure is not generated. A way to do is essential.

[0008]

2. Description of the Related Art Conventionally, a process of sequentially processing each figure data or each side forming each figure for creating drawing data for a vector scan type electron beam drawing apparatus, and then registering the figure data in a subfield In the above, the subfield to be registered in each figure was decided. Therefore, there is a problem that it takes a lot of time to create the drawing data and the work efficiency is reduced.

As a method of solving this problem and creating drawing data at high speed, it has been considered to use a computer having a plurality of CPUs. In this method, an LSI chip is divided into a large number of subfields that can be drawn by electromagnetic deflection of an electron beam drawing apparatus, each subfield is assigned to a plurality of CPUs, and each subfield is independently processed in parallel.

[0010]

However, in this case,
A defect may occur in the manufactured LSI due to the difference in the positional relationship of the graphics registered in each subfield by each CPU.

For example, consider a case where adjacent subfields 31 and 32 are assigned to different graphics processing CPUs to register graphics F10 and F11 as shown in FIG. First, as shown in FIG. 16A, the subfield 31 and the figure F10 included in the field 31 are loaded into one figure processing CPU. After various figure processes are performed on this figure F10, a dividing line is generated in the vertical direction from the vertex of the figure F10 to divide into the figures F20 and F21.

After that, the registration of the figures F20 and F21 is determined. Since a part of each figure F20 and F21 is outside the external margin and inside the internal margin, the figures F20 and F21 are bordered by the subfield 31. Be disconnected. Therefore, as shown in FIG. 16C, F20 is set in the subfield 31.
a and F21a are registered.

Another graphic processing CPU is shown in FIG.
As shown in FIG.
Figures F10 and F11 included in are captured. Figure F
After performing various graphic processings on 10, F11,
As shown in FIG. 17B, the overlapping of the figures F10 and F11 is removed to generate the figure F22. Next, FIG.
As shown in (c), a dividing line is generated in the vertical direction from each vertex of the figure F22, and the figure F22 is divided into figures F23 to F26.

After that, the registration of the figures F23 to F26 is determined. The graphic F23 is excluded from the registration target because it is outside the external margin, and the graphic F24 is excluded from the registration target because a part of the graphic F24 is outside the external margin and outside the internal margin. Each figure F25, F26
Is partly outside the outer margin and inside the inner margin, and is cut at the boundary of the subfield 32. Therefore, as shown in FIG. 17D, the figures F25a and F26a are registered in the subfield 32. The left side of the figure F25a is separated from the boundary line of the subfield 32.

Accordingly, as shown in FIG. 18, the drawing data includes the figure F21a of the subfield 31 and the subfield 3
The area between the second figure F25a is missing. In this state, the LSI circuit is electrically disconnected and the intended LSI circuit cannot be constructed.

Consider a case where adjacent subfields 33 and 34 are assigned to different graphics processing CPUs to register graphics F12 and F13 as shown in FIG. 1
First, as shown in FIG. 19A, the sub-field 33 and the figure F12 included in the field 33 are loaded into one figure processing CPU. After various figure processes are performed on this figure F12, a dividing line is generated in the vertical direction from the vertex of the figure F12 to divide into the figures F27 and F28.

After that, the registration of the figures F27 and F28 is determined. Since a part of each of the figures F27 and F28 is outside the outer margin and inside the inner margin, the figures F27 and F28 are bordered by the subfield 33. Be disconnected. Therefore, as shown in FIG. 19C, F27 is set in the subfield 33.
a and F28a are registered.

FIG. 20A shows another graphic processing CPU.
As shown in FIG.
The figures F12 and F13 included in are captured. Figure F
After various graphic processes are executed for 12 and F13,
As shown in FIG. 20B, the overlapping of the figures F12 and F13 is removed to generate the figure F29. Next, FIG.
As shown in (c), a dividing line is generated in the vertical direction from each vertex of the figure F29, and the figure F29 is divided into figures F30 to F33.

After this, the registration determination of the figures F30 to F33 is performed. The figure F30 is excluded from registration because it is outside the external margin, and the figure F31 is excluded from registration because part of it is outside the external margin and outside the internal margin. Each figure F32, F33
Is partly outside the outer margin and inside the inner margin, and is cut at the boundary of the subfield 34. Therefore, as shown in FIG. 20D, the figures F32a and F33a are registered in the subfield 34. The left side of the figure F32a projects from the boundary line of the subfield 32.

Therefore, as shown in FIG. 21, the drawing data includes the figure F28a of the subfield 33 and the subfield 3 of the figure.
The figure F32a of No. 4 overlaps. In this state, when writing is performed by an electron beam drawing apparatus of the vector scan system, double exposure occurs in the overlap portion, and an abnormally thick line width portion is formed. Therefore, the miniaturized LSI circuit may be electrically short-circuited, and the intended LSI circuit cannot be constructed.

As described above, in the method of allocating each processing target area to a plurality of CPUs and independently performing parallel processing to create drawing data, a missing portion or an overlapping portion may occur in a figure. Therefore, the correction process is required, which hinders high-speed processing of drawing data creation.

The present invention has been made in order to solve the above-mentioned problems, and assigns each processing target area to a plurality of CPUs and independently performs parallel processing to register and draw a figure in each rectangular area. Even if data is created, it is possible to speed up drawing data creation by preventing the loss of graphics that cause circuit disconnection and the overlap of graphics that causes circuit short circuits. It is intended to provide a drawing data creation method.

[0023]

To achieve the above object, a first invention divides an integrated circuit pattern into a large number of processing target areas based on a rectangular area which can be drawn by electromagnetic deflection of an electron beam drawing apparatus. The graphic data of each processing target area and the mask pattern included in the processing target area is assigned to a plurality of CPUs, the graphic processing is independently performed for each processing target area, and then the graphic is registered in each rectangular area. In a drawing data creation method for an electron beam drawing apparatus, a margin of a predetermined width is set inside and outside a rectangular area with a boundary line of each rectangular area as a reference, and an area surrounded by an external margin is set as a processing target area, and each processing is performed. After creating a cutting line pair that includes a pair of upper and lower boundary lines facing each other in the target area and deleting figures other than the figures existing between the cutting line pairs, the cutting line pairs exist between the cutting line pairs. Divide the figure by generating a dividing line perpendicular to the cutting line pair from each vertex of the figure, and when each divided figure is completely included in the rectangular area, or each divided figure is within the outer margin. Further, when the internal figure includes the internal margin and is within the internal margin, the divided figure is registered in the rectangular area. Further, even if a part of each divided figure is outside the outer margin including the outer margin and inside the inner figure including the inner margin, the inner figure obtained by cutting the divided figure at the boundary line of the rectangular area is Register in the rectangular area. Further, when each divided figure is inside the outer margin and outside the inner margin corresponding to a predetermined pair of adjacent boundary lines of the rectangular area, the divided figure is registered in the rectangular area.

According to a second aspect of the invention, the integrated circuit pattern is divided into a large number of processing target areas based on a rectangular area which can be drawn by electromagnetic deflection of an electron beam drawing apparatus, and each processing target area and the processing target area. Drawing data creation method for an electron beam drawing apparatus in which the figure data of the mask pattern included in the above is assigned to a plurality of CPUs, the figure processing is independently performed for each processing target area, and the figure is registered in each rectangular area. In the above, the area surrounded by the external margin by setting a margin of a predetermined width inside and outside the rectangular area with the boundary line of each rectangular area as a reference is the processing target area, and a pair of left and right boundary lines facing each other of the processing target area. After deleting the shapes other than the shapes existing between the cutting line pairs by generating the cutting line pairs each including, each vertex of the shapes existing between the cutting line pairs is perpendicular to the cutting line pair. A dividing line is generated to divide the figure, and each figure is completely contained in the rectangular area, or each figure is within the outer margin and within the inner margin. Sometimes, the divided figure is registered in the rectangular area, and even if a part of each divided figure is outside and including the external margin and inside and including the internal margin, the divided figure is registered in the rectangular area. When the internal figure cut by the boundary line is registered in the rectangular area, and each divided figure is within the outer margin and outside the inner margin corresponding to a predetermined adjacent pair of borders of the rectangular area. The divided figure is registered in the rectangular area.

[0025]

According to the present invention, the figures other than the figures existing between the cutting line pairs are deleted, and the figures existing between the cutting line pairs are divided only by the dividing lines generated perpendicularly to the cutting line pairs from their vertices. To be done. Therefore, the drawing-in area for registering a figure in each rectangular area is made common. Therefore, it is possible to prevent the generation of minute figures, missing figures or overlaps.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment embodying the present invention will now be described with reference to FIGS.
It will be described with reference to FIG. FIG. 1 shows an electrical schematic configuration of a drawing data creating apparatus for creating drawing data for a vector scan type electron beam drawing apparatus. Host CPU
1 is a system control unit 2, a processed graphic data input unit 3, L
An SI chip dividing unit 4, a graphic data transfer unit 5, a graphic data receiving unit 6, and a data output unit 7 are provided. The plurality of child CPUs 13A to 13C, etc., which perform graphic processing upon receiving graphic data from the host CPU 1, are the system control unit 1.
4, a graphic data receiving unit 15, a graphic processing unit 16, and a graphic data transfer unit 17 are provided.

When the control command 8 instructing the graphic conversion process is input, the system control unit 2 of the host CPU 1 activates a predetermined graphic processing program to input the processed graphic data input unit 3, the LSI chip dividing unit 4, and the graphic data. Transfer unit 5,
The graphic data receiving unit 6 and the data output unit 7 are controlled.

The graphic data input section 3 is a magnetic tape 9
The figure data of the mask pattern stored in is read.
The LSI chip dividing unit 4 divides the LSI chip into a large number of subfields 30 (see FIG. 3) as a rectangular area by using the working direct access device 10. Further, as shown in FIG. 4, the LSI chip dividing unit 4 sets a margin M (shown by a broken line) of a predetermined width shown by a broken line inside and outside the subfield 30 with the boundary line of each subfield 30 as a reference. , The area surrounded by the external margin is the processing target area EA.

The graphic data transfer unit 5 includes a plurality of child CPUs 13.
Of the A to 13C, the processing target area EA and the graphic data of the mask pattern included in the processing target area EA are transferred to the child CPU that is not operating. Graphic data receiving unit 6
Receives the graphic-processed data processed by the child CPU. The above operation is executed for all graphic data of the LSI chip.

During this period, the system control unit 14 of each of the child CPUs 13A to 13C controls the graphic data receiving unit 15, the graphic processing unit 16, and the graphic data transfer unit 17 based on a predetermined graphic processing program. The graphic data receiving unit 15 receives the data transferred from the host CPU 1 and outputs the received data to the graphic processing unit 16 in the operation waiting state.

The graphic processing unit 16 inputs the processing target area EA and the graphic data included in the processing target area EA, as shown in FIG.
The graphic processing shown in the flowchart of FIG. That is, first, in step 21, various graphic processing such as overlap removal processing, sizing processing, and scaling processing is performed on the input graphic data. For example, if the subfield 32 and the figures F12 and F13 are input data as shown in FIG. 8A, the overlapping of the figures F12 and F13 is removed and the figure F22 shown in FIG. 8B is generated. It

At step 22, a pair of cutting lines including a pair of upper and lower boundary lines of the processing target area EA are generated for the graphic for which various graphic processing has been finished, and the graphic is cut, and the graphic is present between the pair of cutting lines. Delete shapes other than shapes.
For example, in FIG. 8B, the cutting lines L3 and L4 including the upper and lower boundaries of the processing target area EA are generated to generate the figure F22.
If the figure above the cutting line L3 and below the cutting line L4 is deleted by cutting, the cutting line L3, as shown in FIG.
A figure F37 is generated between L4.

Next, at step 23, a dividing line perpendicular to the cutting line pair is generated from each vertex of the figure existing between the cutting line pair, and between the generated dividing line and the side of the first intersecting figure. When a trapezoidal figure is generated and all the figures are decomposed into trapezoidal figures, the trapezoidal figure is decomposed into triangles and rectangles. For example, when a dividing line is generated perpendicularly to the cutting line L4 from each vertex of the figure F37 in FIG. 8C, divided figures F38 to F40 are generated as shown in FIG. 8D.

Further, in step 24, it is judged whether or not each figure divided in step 23 is a figure to be registered in the subfield based on the registration criteria shown in FIG. 4, and the figure to be registered is selected. Register in the subfield and delete the figures that are not registered.

That is, as shown in FIG. 4A, each figure F
When the subfields 3 and F4 are completely contained in the subfield 30, the figures F3 and F4 are registered in the subfield 30. As shown in FIG. 4B, when even a part of the figure F5 is outside and including the external margin and inside the figure and including the internal margin.
Is cut into figures F5a and F5b at the boundary of the subfield 30. Then, only the figure F5a inside the subfield 30 becomes the registration target in the subfield 30,
The figure F5b is deleted.

As shown in FIG. 4C, when the figure F6 is inside the outer margin of the subfield 30 and also inside the outer margin including the inner margin, the figure F6 is registered in the subfield 30. Be the target. Furthermore, FIG.
As shown in (d), when the figures F7 and F8 are inside the outer margins on the upper and left sides of the subfield 30 and outside the inner margins, the figures F7 and F8 are to be registered in the subfield 30. Become.

In the final step 25, the figure registered in the subfield in step 24 is passed to the final figure processing for drawing data. Then, the graphic processing unit 16
Outputs the graphic-processed data processed as described above to the graphic data transfer unit 17. The graphic data transfer unit 17 sends back the graphic-processed data processed by the graphic processing unit 16 to the host CPU 1.

LS by the plurality of child CPUs 13A to 13C
When all the graphic data of the I chip are processed and the graphic-processed data is sent back to the host CPU 1, the data output unit 7 outputs the drawing data to the output list 11 or the magnetic tape 12.

On the basis of the drawing data recorded on the magnetic tape 12, an electron beam drawing apparatus of the vector scan system draws on a semiconductor wafer to manufacture an LSI circuit.

Next, the operation of the drawing data creating apparatus configured as described above will be described. Now, for example, as shown in FIG.
Consider a case in which the figures F10 and F11 are assigned by being assigned to A and 13B.

First, as shown in FIG. 7A, a processing target area EA including a subfield 31 and a graphic F10 included in the processing target area EA are loaded into the child CPU 13A. After various graphic processes are performed on the graphic F10, cutting lines L1 and L2 including upper and lower boundaries of the processing target area EA are generated as shown in FIG. 7B. The figure F10 is cut by the cutting lines L1 and L2, and the cutting line L1
The figure above the line and below the cutting line L2 is deleted, and a figure F34 is generated between the cutting lines L1 and L2. Next, FIG.
As shown in (c), a dividing line is generated perpendicularly to the cutting line L2 from the apex of the figure F34, and divided into the divided figures F35 and F36.

After that, the registration of the figures F35 and F36 is determined, and a part of each of the figures F35 and F36 is on the outer margin, that is, outside and inside the inner margin. It is cut with a line. Therefore, as shown in FIG.
35a and F36a are registered. The right side of the figure F36a is in contact with the boundary line of the subfield 31.

Further, as shown in FIG. 8A, the child CPU 13B receives the processing target area EA including the subfield 32 and the figures F10 and F11 included in the processing target area EA. After various figure processes are executed on the figures F10 and F11, as shown in FIG.
The figure F22 is generated by removing the overlap of 0 and F11. Next, as shown in FIG. 8C, cutting lines L3 and L4 including upper and lower boundaries of the processing target area EA are generated. The figure F22 is cut by the cutting lines L3 and L4, and the cutting line L
The figure above 3 and below the cutting line L4 is deleted, and a figure F37 is generated between the cutting lines L3 and L4. Thereafter, as shown in FIG. 8D, the cutting line L4 is cut from the top of the figure F37.
A dividing line is generated perpendicularly to and is divided into divided figures F38 to F40.

Then, the registration of the figures F38 to F40 is judged. The figure F38 is excluded from registration because it is outside the external margin. Part of each of the figures F39 and F40 is on the outer margin, that is, outside the inner margin and inside the inner margin, and is therefore cut at the boundary line of the subfield 32. Therefore, the figures F39a and F40a are registered in the subfield 32 as shown in FIG.
The left side of the figure F39a is in contact with the boundary line of the subfield 32.

Therefore, as shown in FIG. 9, the drawing data is such that the figures F35a and 36a of the subfield 31 and the figures F39a and F40a of the subfield 32 are in contact with each other without any overlap, thereby forming the intended LSI circuit. can do.

Further, consider a case where adjacent subfields 33 and 34 are assigned to the child CPUs 13A and 13B to register the figures F12 and F13 as shown in FIG. First, as shown in FIG. 10A, a processing target area EA including a subfield 33 and a graphic F12 included in the processing target area EA are taken into the child CPU 13A. After various graphic processes have been executed on this graphic F12, FIG.
As shown in 0 (b), cutting lines L5 and L6 including upper and lower boundaries of the processing target area EA are generated. Cutting lines L5, L
The figure F12 is cut by 6, and the figures above the cutting line L5 and below the cutting line L6 are deleted, and the cutting lines L5 and L6 are cut.
A figure F41 is generated in the meantime. Next, as shown in FIG. 10C, a dividing line is generated from the apex of the figure F41 perpendicularly to the cutting line L6 and divided into the divided figures F42 and F43.

After that, the registration of the figures F42 and F43 is determined, and a part of each figure F42 and F43 is on the outer margin, that is, outside and inside the inner margin. It is cut with a line. Therefore, as shown in FIG. 10D, F42a and F43a are registered in the subfield 33. The right side of the figure F43a is in contact with the boundary line of the subfield 33.

Further, the child CPU 13B has a processing target area EA including a subfield 34 as shown in FIG.
And figures F12 and F13 included in the processing target area EA
Is captured. After various figure processes are performed on the figures F12 and F13, the overlap of the figures F12 and F13 is removed and a figure F29 is generated as shown in FIG. 11B. Next, as shown in FIG. 11C, cutting lines L7 and L8 including upper and lower boundaries of the processing target area EA are generated. The figure F29 is cut by the cutting lines L7 and L8, the figures above the cutting line L7 and below the cutting line L8 are deleted, and the figure F44 is generated between the cutting lines L7 and L8. Thereafter, as shown in FIG. 11D, a dividing line is generated perpendicularly to the cutting line L8 from the vertex of the figure F44, and the dividing figure F45 is generated.
~ F47.

Then, the registration of the figures F45 to F47 is determined. The figure F45 is excluded from the registration target because it is outside the external margin. Part of each of the figures F46 and F47 is on the outer margin, that is, outside and inside the inner margin, and therefore is cut at the boundary line of the subfield 34. Therefore, as shown in FIG. 11E, the figures F46a and F47a are registered in the subfield 34. The left side of the figure F46a is in contact with the boundary line of the subfield 34.

Therefore, as shown in FIG. 12, the drawing data is such that the figures F42a and 43a of the subfield 33 and the figures F46a and F47a of the subfield 34 are in contact with each other without any overlap, and the intended LSI circuit is constructed. can do.

As described above, in this embodiment, a plurality of CPUs 1
When each processing target area is assigned to 3A to 13C and parallel processing is performed independently to create drawing data, a cutting line pair including a pair of upper and lower boundary lines facing each other is generated to generate a cutting line pair. The shapes other than the existing shapes are deleted. For this reason, it is possible to make the figure capture area common when registering a figure in each subfield. Therefore,
It is possible to prevent the loss of graphics that causes disconnection of LSI circuits and the occurrence of overlap that causes short circuits in LSI circuits.
It is possible to speed up drawing data creation.

In the above embodiment, a cutting line pair including a pair of upper and lower boundary lines of each processing target area EA is generated to delete figures other than the figures existing between the cutting line pairs. Instead of this, a cutting line pair including a pair of left and right boundary lines of each processing target area EA may be generated to delete figures other than the figures existing between the cutting line pairs.

In the above embodiment, three child CPUs 13A are used.
Although 13C to 13C are provided, two or four or more child CPUs may be provided, and a processing target area may be assigned to each CPU to allow independent parallel processing.

[0054]

As described in detail above, according to the present invention,
Even if the graphics data is created by registering graphics in each rectangular area by allocating each processing target area to multiple CPUs and performing independent parallel processing, the cause of the graphic missing or the circuit short circuit that causes the circuit disconnection It is possible to prevent the overlap of the figures to be generated and to speed up the drawing data creation.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing an electrical configuration of a drawing data creating apparatus according to an embodiment.

FIG. 2 is a flowchart showing processing of a graphic processing unit.

FIG. 3 is a diagram showing a state in which an LSI chip is divided into subfields.

FIG. 4 is a diagram showing a registration standard of graphics in a subfield.

FIG. 5 is a diagram showing an example of mask pattern data.

FIG. 6 is a diagram showing an example of mask pattern data.

FIG. 7 is a diagram illustrating a graphic registration process according to an embodiment.

FIG. 8 is a diagram illustrating a graphic registration process according to an embodiment.

9 is a diagram showing drawing data created from the mask pattern data of FIG.

FIG. 10 is a diagram illustrating a graphic registration process according to an embodiment.

FIG. 11 is a diagram illustrating a graphic registration process according to an embodiment.

12 is a diagram showing drawing data created from the mask pattern data of FIG.

FIG. 13 is a diagram showing a state in which internal and external margins are set in a subfield.

FIG. 14 is a diagram illustrating a problem of a conventional graphic processing method.

FIG. 15 is a diagram showing a registration result by a conventional graphic processing method.

FIG. 16 is a diagram illustrating a conventional graphic registration process.

FIG. 17 is a diagram illustrating a conventional graphic registration process.

FIG. 18 is a diagram showing drawing data created by a conventional graphic processing method.

FIG. 19 is a diagram illustrating a conventional graphic registration process.

FIG. 20 is a diagram illustrating a conventional graphic registration process.

FIG. 21 is a diagram showing drawing data created by a conventional graphic processing method.

[Explanation of symbols]

 1 host CPU 2 system control unit 3 processed graphic data input unit 4 LSI chip dividing unit 5 graphic data transfer unit 6 graphic data receiving unit 7 data output unit 7 13A to 13C child CPU 14 system control unit 15 graphic data receiving unit 16 graphic Processing unit 17 Graphic data transfer unit 30 to 34 Subfield EA Processing target area F1 to F46 Graphic L1 to L8 Cutting line M Margin

Claims (2)

[Claims] 1. An integrated circuit pattern is divided into a large number of processing target areas based on a rectangular area that can be written by electromagnetic deflection of an electron beam drawing apparatus, and each processing target area and mask patterns included in the processing target area are divided. Graphic data can be converted into multiple C
In the drawing data creation method for the electron beam drawing apparatus, which is configured such that the figures are registered in each rectangular area after being assigned to the PU and each figure area is independently processed, the boundary line of each rectangular area is used as a reference. By setting a margin of a predetermined width inside and outside the rectangular area, the area surrounded by the external margin is set as the processing target area, and a cutting line pair including a pair of upper and lower boundary lines of each processing target area is generated and cut. After deleting shapes other than the ones existing between line pairs, divide the figure by generating a dividing line perpendicular to the cutting line pairs from each vertex of the shapes existing between the cutting line pairs, and dividing each shape into a rectangle. When it is completely included in the area, or when each divided figure is inside the outer margin and also inside the inner margin, the divided figure is registered in the rectangular area, and Even if a part of the split figure is outside and including the external margin and inside and including the internal margin, the internal figure obtained by cutting the divided figure at the boundary of the rectangular area is set to the rectangular area. Further, the divided figures are registered in the rectangular area when each divided figure is within the outer margin and outside the inner margin corresponding to a predetermined pair of adjacent boundary lines of the rectangular area. A writing data creation method for an electron beam writing apparatus, characterized in that. 2. An integrated circuit pattern is divided into a large number of processing target areas based on a rectangular area that can be drawn by electromagnetic deflection of an electron beam drawing apparatus, and each processing target area and mask patterns included in the processing target area are divided. Graphic data can be converted into multiple C
In the drawing data creation method for the electron beam drawing apparatus, which is configured such that the figures are registered in each rectangular area after being assigned to the PU and each figure area is independently processed, the boundary line of each rectangular area is used as a reference. A margin of a predetermined width is set inside and outside the rectangular area, and the area surrounded by the external margin is set as a processing target area, and a cutting line pair including a pair of left and right boundary lines of each processing target area is generated and cut. After deleting shapes other than the ones existing between line pairs, divide the figure by generating a dividing line perpendicular to the cutting line pairs from each vertex of the shapes existing between the cutting line pairs, and dividing each shape into a rectangle. When it is completely included in the area, or when each divided figure is inside the outer margin and also inside the inner margin, the divided figure is registered in the rectangular area, and Even if a part of the split figure is outside and including the external margin and inside and including the internal margin, the internal figure obtained by cutting the divided figure at the boundary of the rectangular area is set to the rectangular area. Further, the divided figures are registered in the rectangular area when each divided figure is within the outer margin and outside the inner margin corresponding to a predetermined pair of adjacent boundary lines of the rectangular area. A writing data creation method for an electron beam writing apparatus, characterized in that.