JPH03283423A - Charged beam drawing method - Google Patents

Abstract

PURPOSE:To remarkably cut down the processing time for converting the design pattern data in stage layer structure to the picture drawing pattern data required for actual picture drawing processing by a method wherein the mutual overlap removal of figure pattern included in block regions and the figure processing as well as the figure division processing from the largest region capable of being deflected by a beam deflecting means to the limited unit picture drawing regions are integratedly performed. CONSTITUTION:The data on the conditions if the figure patterns included in the block constituting the design pattern data are overlapped with one another or not are checked and expanded by a host computer so as to be resultantly brought together into block data comprising figure patterns 60a-60h and the reference data on the other blocks 61, 62 furthermore the block data 61 including a figure 61a and the other block data 62 comprising figure patterns 62a, 62b are collected. Finally, the figure processing and the figure division processing such as mutual overlap removal and the white and black inversion etc., of the so far taken figure patterns included in respective blocks are performed.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention is directed to a charging method for drawing patterns of semiconductor integrated circuits such as LSIs on samples such as masks and semiconductor wafers at high speed and with high precision. The present invention relates to a beam lithography method, and particularly to a charged beam lithography method that enables high-speed generation of lithography pattern data acceptable to an apparatus.

(Prior Art) In recent years, LSI patterns have become increasingly finer and more complex, and electron beam lithography devices are widely used as devices for forming such patterns. When drawing a desired pattern using this device, LS such as CAD
Design pattern data created using the pattern design tool I cannot be supplied as drawing pattern data to the above-mentioned drawing apparatus in its original format. In other words, the data system defined by the design pattern data is generally created as a data system with a very high degree of freedom, so in order to make the data system acceptable to the electron beam lithography system, the following is required. must satisfy certain restrictions.

■ Defined as a figure system consisting only of basic figures (trapezoids, rectangles, etc.) that can be accepted by electron beam lithography equipment.

■ Must be defined in a data system that does not overlap each other, which would result in multiple exposures and reduce pattern formation accuracy.

■ Defined in a data system divided into predetermined unit lithography areas according to the lithography method of the electron beam lithography system.

Therefore, the multiple exposure area is removed using a method such as contouring processing from the above design pattern data, and then a unique unit drawing area (
By dividing the graphics into basic graphics groups such as rectangles, trapezoids, and triangles for each frame region and subfield region, a graphics data system acceptable to the electron beam lithography system is created. Then, drawing pattern data related to a desired LSI chip is generated based on data of such a graphic system, and the drawing pattern data is stored in a storage medium typified by a magnetic disk and used for drawing.

Then, in the drawing processing step, the above drawing pattern data is
Each drawing stripe area (an area where frame areas are collected according to a predetermined rule), which is a unit area that can be drawn by continuous movement of the table, is read out and temporally stored in the pattern memory section. The data stored in this pattern memory is decoded and a desired pattern is constructed from a collection of drawing unit figures (rectangles with limits on figure size and triangles with limits on shape and size) that can be formed by beam shaping means. The figure is divided as much as possible.

Based on the resulting graphical data, the beam position and beam shape are controlled, and the table on which the sample is placed is continuously moved in the X or Y direction to create a desired area within the drawing stripe area. Draw a pattern.

Next, the table is moved by the width of the drawing stripe area in a direction perpendicular to the direction of continuous movement, and the above process is repeated to perform the drawing process on the entire desired area. In addition, in a two-stage deflection method in which the main deflection means controls the sub-deflection position and the sub-deflection means draws a desired pattern in the sub-deflection area, the frame area is composed of a collection of unit drawing areas (sub-fields). A collection of these frame areas constitutes a writing stripe area, and the width of the writing stripe is defined by the beam deflection widths of the main deflection means and the sub-deflection means.

As mentioned above, when generating the drawing pattern data to be used in the drawing process, as a countermeasure for the miniaturization and high integration of LSI patterns, it is necessary to Compression of the drawing pattern data was achieved by composing the drawing pattern data with a group of graphic patterns and their repetition information. The reason for this is that in the data conversion process of memory devices, where pattern density is becoming finer and the degree of integration is increasing rapidly, computer resources will be severely strained unless data compression using the above-mentioned repeating structure is performed. This is because data conversion is no longer possible from the viewpoint of taking a long time and making it impractical.

Against this background, in actual data conversion processing,
In data conversion processing for a non-repetitive pattern area, the area is divided into areas in a matrix based on a predetermined subfield size, and for each subfield area, its drawing position and the area included in the subfield area are calculated. Generates drawing pattern data that defines a group of drawing figure patterns. And for pattern areas with repeats,
It is determined whether the area that becomes the repetition seed is larger than the above subfield size, and if it is smaller or equal to the above, drawing in which repetition information is added to the figure data indicating the drawn figure pattern included in the repetition seed pattern area. Use it as pattern data. If the area is larger than the subfield area, the repeated seed pattern area is divided into areas with a predetermined subfield size, and drawing pattern data of a system in which repetition information is added for each subfield area is generated.

Then, by combining the drawing pattern data generated through the above processing steps, drawing pattern data (frame data) relating to a frame area, which is one unit constituting the area of the LSI chip, is constructed. Furthermore, chip data is expressed as a collection of frame data, and when drawing, the drawing process is repeated for each drawing stripe area, which is a unit area that collects frame areas that can be drawn by one continuous movement of the table. The entire desired area was drawn.

However, this type of method has the following problems. That is, in the process of data conversion from design pattern data created in CAD to drawing pattern data, a lot of processing time is spent on removing overlaps between figures included in the block area and dividing subfields of figures. These factors were a major factor hindering the speeding up of data conversion time.

Due to this situation, the current data conversion process uses CAD
There is a limit to how quickly the desired drawing pattern data can be generated from the design pattern data created by
The progress in miniaturization and higher integration of LSIs has led to longer data conversion times, and as the writing throughput of the writing apparatus itself improves, the supply of writing pattern data cannot keep up. In other words, it is quite conceivable that the data conversion process will limit the drawing throughput, and there will always be a need to improve and expand the performance of computers.

These problems will reduce the operation rate of electron beam lithography equipment and cause a decline in LSI productivity.In the future, with the rapid progress of LSI, pattern miniaturization and increased integration will lead to electronic This poses a major problem in increasing the reliability of the LSI pattern written by the beam drawing device and the operating rate of the device.

(Problem to be Solved by the Invention) As described above, in the process of converting the drawing pattern data from the design pattern data etc. in the conventional drawing method using a combination of beam deflection means to control the beam position and beam shape, As the scale of LSI patterns increases, the time required for removing overlaps between figures, reversing black and white, and dividing the figures into areas, which impedes the speeding up of the data conversion time, has become longer. For this reason, the data conversion processing time (the time from when design pattern data is actually input until the drawing pattern data is output) becomes longer, which can lead to problems such as a decrease in drawing throughput. Conceivable.

Note that the above-mentioned problem is not limited to the electron beam drawing method, but also applies to the ion beam drawing method using an ion beam and the laser drawing method using a laser.

The present invention has been made in consideration of the above circumstances, and its purpose is to eliminate graphic arithmetic processing (removal of graphic overlaps and black and white inversion processing) and graphic division processing, which have a high proportion in the data conversion processing process. It is an object of the present invention to provide a charged beam lithography method that can increase the speed, shorten data conversion time, and improve lithography throughput.

[Structure of the Invention] (Means for Solving the Problems) The gist of the present invention is to control the beam shape and beam position from design pattern data expressing the graphic pattern of an LSI or from different drawing methods. When generating drawing pattern data for drawing a desired LSI pattern on a sample such as a mask or wafer, the overall data conversion time can be significantly reduced by speeding up the graphic calculation processing and graphic division processing between graphic patterns. The goal is to shorten the time.

That is, the present invention provides LSI chip design pattern data expressed as a set of block data consisting of figure pattern information to be drawn and reference information of other blocks;
or generating drawing pattern data expressing a desired pattern to be drawn on the sample by controlling the shape and drawing position of the charged beam from drawing pattern data of different drawing methods;
In a charged beam drawing method in which a desired pattern is drawn based on the drawing pattern data, a predetermined operation (such as mutual overlap removal processing or black-and-white When performing graphic arithmetic processing (inversion processing) and graphic division processing (dividing the graphic pattern into predetermined areas), a The block area is divided into three types of line segments, an X parallel line segment and a Y parallel line segment for each of the scanning areas to be divided, and the graphic calculation process is performed for each divided slit area. This method generates drawing pattern data.

(Operation) According to the present invention, L created by effectively utilizing the hierarchical structure
When generating drawing pattern data for drawing a desired pattern on a sample by controlling the beam shape and beam position from the SI design pattern data, the mutual overlap of graphic patterns included in each block area is determined. The time required for these processes can be reduced by integrating graphic calculation processing, typified by removal and black-and-white inversion processing, and graphic division processing into unit drawing areas limited from the maximum area that can be deflected by the beam deflection means. It is possible to reduce the time required, and it is possible to significantly speed up data conversion.

As described above, the method of the present invention makes it possible to significantly shorten the processing time required for data conversion from hierarchically structured design pattern data to drawing pattern data necessary for actual writing processing, and as a result, It is possible to increase the operating rate of the drawing device and to improve the productivity of LSI. In addition, the data conversion method of the charged beam lithography system described above is expected to be more effective in the future as patterns become smaller and more highly integrated, and there is a demand for shorter delivery times for lithography masks. .

(Example) Hereinafter, details of the present invention will be explained with reference to illustrated embodiments.

FIG. 1 is a schematic diagram showing the configuration of an electron beam lithography system used in a method according to an embodiment of the present invention.

In the figure, reference numeral 10 denotes a sample chamber, and a table 12 on which a sample 11 such as a glass mask or a semiconductor wafer is placed is accommodated in the sample chamber 10. The table 12 is driven by a table drive circuit 13 in the X direction (left and right directions on the paper) and the Y direction (front and back directions on the paper). And table 12
The moving position of is measured by a position circuit 14 using a laser length measuring needle or the like.

An electron beam optical system 20 is arranged above the sample chamber 10. This optical system 20 includes an electron gun 21, various lenses 2
2-26, blanking deflector 31. Beam dimension variable deflector 32. Main deflector 33 for beam scanning. Sub deflector 34 and beam shaping aperture 35.3 for beam scanning
It consists of 6 mag. Then, it is positioned in a predetermined unit drawing area (subfield) by the main deflector 33,
The sub-deflector 34 positions the figure drawing position within the sub-field, and the beam dimension variable deflector 32
The beam shape is controlled by the shaping apertures 35 and 36, and while the table 12 is continuously moved in one direction, the LSI chip pattern area is drawn in a drawing stripe area that is collected within the range that can be drawn by one continuous movement of the table. . In other words, a writing stripe area is written, which is a collection of frame areas obtained by dividing the LSI chip pattern area into strips according to the deflection width of the beam. Furthermore, table 12
is moved stepwise in a direction perpendicular to the direction of continuous movement, and the above process is repeated to sequentially draw each drawing stripe area.

On the other hand, the control computer 40 has a magnetic disk (storage medium) 4.
1 is connected, and the drawing pattern data of the LSI chip is stored in this disk 41. The drawing pattern data of the LSI chip read from the magnetic disk 41 is temporarily stored in a pattern memory (data buffer section) 42 for each drawing stripe area.

The drawing pattern data for each drawing stripe stored in the pattern memory 42, that is, the drawing stripe information composed of drawing positions, basic figure data, etc., is decoded by a pattern data decoder 43 and a drawing data decoder 44, which are data decoding units. It is sent to a blanking circuit 45 , a beamformer driver 46 , a main deflector driver 47 and a sub-deflector driver 48 .

That is, the pattern data decoder 43 inputs the drawing pattern data for each drawing stripe area, expands the compressed drawing figure data based on the pattern repetition information defined as the drawing stripe data, and
In the drawing process of the drawing stripe area, the drawing figure data defined in the drawing pattern data is transferred to the forming forming aperture 35 while determining and decoding for each subfield whether or not it is an area to be drawn and the area to be drawn next. The beam control data is created based on this data and sent to the blanking circuit 45.

Then, the desired beam dimension data is created,
Control data for this beamforming is sent to beamformer driver 46. Next, the beamformer driver 46
A predetermined deflection signal is applied to the beam size variable deflector 32 of the optical system 20, thereby controlling the size of the electron beam.

Further, the drawing data decoder 44 decodes and creates subfield positioning data based on the drawing stripe data, and sends it to the main deflector driver 47. Then, a predetermined signal is applied from the main deflector driver 47 to the main deflector 33 of the optical system 20, whereby the electron beam is deflected and scanned to a designated subfield position.

Further, the drawing data decoder 44 generates a control signal for scanning the sub-deflector, and this signal is sent to the sub-deflector driver 48. A predetermined sub-deflection signal is applied from the sub-deflector driver 48 to the sub-deflector 34, thereby performing drawing processing for each sub-field.

Next, an electron beam lithography method using the apparatus configured as described above will be explained. FIG. 2 shows the process of generating data for performing the drawing process. The LSI pattern is
Design and pattern creation (digitization processing) is performed using a CAD system, and the design pattern data is converted into a device-specific drawing pattern depending on the drawing method of the electron beam drawing device using a host computer with high processing power, including a large computer. converted.

Based on this drawing pattern data, the positioning and beam shape of the electron beam are controlled to perform a series of drawing processes.

Here, the design pattern data created by the CAD system is an independent data system for each LSI chip 51 to 55 constituting the drawing mask 50, as shown in FIG. 3, if the sample to be drawn is a mask, for example. As shown in FIG. 4, the design pattern data related to each LSI chip is a data system having a hierarchical structure in which graphic data is stored distributed among several processors.

Specifically, a block 60 representing the entire LSI chip has child blocks 61 and 62 arranged as shown in FIG. 4(a), and block reference information includes child blocks 61 and 62 as shown in FIG. The block arrangement information is composed of the array arrangement information of the block 61 and the array arrangement information of the child block 62 as shown in FIG. As shown in (f), the data system defines graphic patterns, and as a result, an LSI chip as shown in (g) of the same figure is expressed.

In order to convert LSI pattern data in this format into a graphic data system that can be accepted by an electron beam lithography system, a host computer checks whether the graphic patterns included in the blocks constituting the design pattern data overlap each other. and expansion processing (for example, Japanese Patent Application No. 62-3271
According to the method disclosed in No. 9), the result is a graphic pattern 60 a c - 60h as shown in FIG. 5(a) and reference information of blocks 61 and 62 as shown in FIG. As block data, block data 61 including a graphic pattern 61a and block data 62 composed of graphic patterns 62a and 62b are obtained.

Graphic operations and graphic division processing, such as removing mutual overlap between graphic patterns included in each block thus obtained and inverting black and white, are performed. This graphic calculation and graphic division processing will be explained below.

FIG. 6(a) shows a graphic pattern group included in the block area 80, which is composed of graphic patterns 81 to 85, and each graphic pattern group has overlapping patterns as shown by diagonal lines. have. Processing steps for removing overlaps between graphic pattern groups, reversing black and white, and dividing graphics into subfields will be sequentially explained.

First, as shown in FIG. 6(b), the graphic patterns 81 to
Y-axis parallel line segments 90a to 90i passing through each vertex of the block area 85 are defined, and then, as shown in FIG. Divide into slits. Then, for each slit area, the side vector of the figure as shown in FIG. 6(d) is defined using the upper left vertex of each figure pattern as the reference point, and if By incrementing the vector by +1 and -1 in the case of a leftward vector, the overlapping portions of the figures are removed as a result. Note that in detecting the overlapped portion in this case, the overlapped portion is determined from the vector that becomes +2 to the next vector that becomes +1.

Furthermore, in the above figure overlap removal process, the subfield dividing line segment 91b shown in FIG. It is possible to obtain a graphic pattern as shown in the figure () in which overlapping figures are removed and subfields are divided.

Regarding the black and white reversal process, as shown in Figure 6(e), the above vectors are interpreted from the bottom of the slit by changing the interpretation of the side vectors of the figure, and when the first vector is rightward, and when the final vector is leftward, 1 each
Define two closed shapes. In this case as well, by forcibly making the figure a closed figure (not divided in this example) at the subfield dividing line segment 91b, a figure pattern as shown in FIG. 6(g) is obtained.

By performing the above-mentioned processing on all the slit areas, it is possible to create a graphic system in which the figures do not overlap each other and are divided into sub-field areas as shown in FIG. 6(h). For the purpose of reducing the number of figures and the amount of data in the figure pattern group, each figure is merged with adjacent figures in the X direction to form the figure pattern group shown in FIG. 6(1). Further, FIG. 6(j) shows a graphic pattern group obtained by performing black-and-white inversion processing and subfield division processing.

In this way, the process of storing the above graphic pattern group on the magnetic disk in units of blocks is repeated, and the LS
Graphic operations and graphic division processing are performed on the graphic patterns included in all the blocks constituting the design pattern data of I.

The block-by-block graphic pattern group obtained through the above-mentioned processing steps has the hierarchical structure of the pattern restricted to a level so that there is no block reference other than block 60, which indicates the entire LSI chip. (in this example, the original data has a Lebel data structure), and as shown in Figure 7, the LS
The entire area of the I-chip is divided into temporary frame areas (71 to 76) determined by the main deflection width of the beam. In FIG. 7, the continuous movement direction of the table is the horizontal direction in the paper, and the table step movement direction is the vertical direction in the paper.

Next, the data conversion process performed for each frame process will be explained. The above provisionally divided frame area 71
76 (hereinafter referred to as a virtual frame area), the block area is composed of position data that defines the drawing position of the block area based on the relative position from the reference position of the virtual frame area, and array attribute information. The block drawing data consists of the block arrangement data to be drawn, and the block figure data as shown in FIG. Frame data consisting of the aggregate and the drawing position data of the block area is generated.

The frame data group obtained in this way is stored on a magnetic disk. Then, based on the drawing pattern data stored in the magnetic disk, for example,
By performing the drawing process using the method disclosed in No. 188, high-speed and highly accurate drawing can be realized.

Thus, according to the method of this embodiment, it is possible to rapidly convert drawing pattern data that is highly consistent with design pattern data created by a CAD system. According to the results of experiments conducted by the present inventors, it was possible to achieve approximately twice the speed.

Therefore, according to the method of this embodiment, it is possible to significantly reduce the processing time for data conversion from design pattern data having a hierarchical structure to drawing pattern data necessary for actual drawing processing, and as a result, the charged beam drawing device In addition to increasing the operating rate of the LSI, it is also possible to increase the productivity of the LSI.

Note that the present invention is not limited to the embodiments described above. For example, the means for storing the drawing pattern data is not limited to a magnetic disk, but other storage media such as a magnetic tape or a semiconductor memory can be used. Further, the configuration of the electron beam lithography apparatus is not limited to the same as that shown in FIG. 1, but can be modified as appropriate. Although the embodiments have been explained using an electron beam as an example, the application is not limited to electron beams, but can be applied to ion beams, laser beams, etc., and the drawing method may include a two-stage deflection method that combines main and sub-deflection. , a one-stage deflection method or a three-stage or more deflection method may be used. Furthermore, in addition to the shot method using a variable shaped beam, it is also applicable to a vector or rask method using an elliptical beam. Furthermore, the graphic system of the drawing pattern data stored in the storage medium may be not only basic figures such as rectangles and trapezoids but also drawing unit figures and polygonal figures, and the present invention is also applicable to data of such a graphic system.

Furthermore, input data to be converted is not limited to design pattern data having a hierarchical structure, and may be drawing pattern data that is supplied to devices with different drawing methods.

Specifically, in a rask scanning type drawing apparatus using a circular beam as shown in FIG. 9, the drawing pattern data itself usually allows overlap in the drawing figures, and the drawing figures are In the process of developing dots, the overlap of figures is removed and black and white is inverted. In this way, the above-described processing is effective for data that requires the above-described graphic calculation processing and graphic division processing for input data. In addition, various modifications can be made without departing from the gist of the present invention.

[Effects of the Invention] As detailed above, according to the present invention, a desired pattern can be created by controlling the beam shape and beam writing position from LSI design pattern data having a hierarchical structure or writing pattern data using different writing methods. To speed up the processing time required for figure calculation processing and figure division processing, such as mutual overlap removal of figures and black and white inversion processing, which occupy a considerable proportion of the conversion processing time when generating drawing pattern data for drawing processing. This makes it possible to significantly speed up data conversion.

[Brief explanation of the drawing]

Fig. 1 is a schematic diagram showing the configuration of an electron beam lithography system used in a method according to an embodiment of the present invention, Fig. 2 is a schematic diagram showing the process of generating drawing pattern data, and Fig. 3 is an LSI arranged on a drawing sample. FIG. 4 is a schematic diagram showing the data structure of the chip; FIG. 4 is a schematic diagram showing the data structure of design pattern data; FIG. 5 is a schematic diagram showing the block data system; FIG. 6 is a schematic diagram showing the graphic processing system. Figure 7 is a schematic diagram showing virtual division into frame areas, Figure 8 is a schematic diagram showing the structure of drawing pattern data, and Figure 9 is a schematic diagram showing a rask scanning writing method using a circular beam. be. DESCRIPTION OF SYMBOLS 10... Sample chamber, 11... Sample, 12... Table, 20... Electron optical system, 21... Electron gun, 22
~26...Lens, 31-34...Deflector, 35.36...Beam shaping aperture, 40...Control computer, 41...Magnetic disk (storage medium), 42...Pattern memory , 43... Pattern data decoder, 44... Drawing data decoder, 45... Blanking circuit, 46-48... Deflector driver, 51-55... LSI chip, 60... Block, 61.62...Child block area, 60a-60h...Graphic pattern, 71-76...Frame area, 80...Block area, 81-85...Graphic pattern, 902-90i...Y Axial line segments, 91a, 91b...subfield dividing line segments.

Claims (2)

[Claims] (1) From LSI chip design pattern data expressed as a set of block data consisting of figure pattern information to be drawn and reference information of other blocks, or drawing pattern data of different drawing methods, the shape of the charged beam and In a charged beam drawing method, the drawing pattern data is generated by controlling a drawing position to express a desired pattern to be drawn on a sample, and the desired pattern is written based on the drawing pattern data, wherein the design pattern data is configured. When performing a graphic calculation process in which a predetermined operation is performed on a graphic pattern in a block, and a graphic division process in which the graphic pattern is divided into predetermined areas, the vertices of a group of graphic patterns included in the block are dividing the block area by three types of line segments: a line segment parallel to the X direction or Y direction passing through the area, and an X direction dividing line segment and a Y direction dividing line segment for each area to be divided;
A charged beam drawing method, characterized in that the graphic calculation process is performed for each of the divided slit areas to generate the drawing pattern data. (2) The charged beam drawing method according to claim 1, wherein the graphic calculation process includes removing mutual overlap between graphic patterns in blocks constituting the design pattern data, or performing black and white inversion processing.