JPH01253059A - 並列信号処理方式 - Google Patents

並列信号処理方式

Info

Publication number
JPH01253059A
JPH01253059A JP63078120A JP7812088A JPH01253059A JP H01253059 A JPH01253059 A JP H01253059A JP 63078120 A JP63078120 A JP 63078120A JP 7812088 A JP7812088 A JP 7812088A JP H01253059 A JPH01253059 A JP H01253059A
Authority
JP
Japan
Prior art keywords
processor
bus
processors
memory
signal processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63078120A
Other languages
English (en)
Japanese (ja)
Inventor
Hirohisa Yamaguchi
博久 山口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KDDI Corp
Original Assignee
Kokusai Denshin Denwa KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kokusai Denshin Denwa KK filed Critical Kokusai Denshin Denwa KK
Priority to JP63078120A priority Critical patent/JPH01253059A/ja
Priority to EP89904226A priority patent/EP0369022B1/fr
Priority to DE68923684T priority patent/DE68923684T2/de
Priority to PCT/JP1989/000351 priority patent/WO1989009448A1/fr
Priority to US07/399,555 priority patent/US5084836A/en
Publication of JPH01253059A publication Critical patent/JPH01253059A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Image Processing (AREA)
JP63078120A 1988-04-01 1988-04-01 並列信号処理方式 Pending JPH01253059A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP63078120A JPH01253059A (ja) 1988-04-01 1988-04-01 並列信号処理方式
EP89904226A EP0369022B1 (fr) 1988-04-01 1989-04-01 Systeme de traitement de signaux en parallele
DE68923684T DE68923684T2 (de) 1988-04-01 1989-04-01 System fuer parallele signalverarbeitung.
PCT/JP1989/000351 WO1989009448A1 (fr) 1988-04-01 1989-04-01 Systeme de traitement de signaux en parallele
US07/399,555 US5084836A (en) 1988-04-01 1989-07-26 Parallel signal processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63078120A JPH01253059A (ja) 1988-04-01 1988-04-01 並列信号処理方式

Publications (1)

Publication Number Publication Date
JPH01253059A true JPH01253059A (ja) 1989-10-09

Family

ID=13653025

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63078120A Pending JPH01253059A (ja) 1988-04-01 1988-04-01 並列信号処理方式

Country Status (5)

Country Link
US (1) US5084836A (fr)
EP (1) EP0369022B1 (fr)
JP (1) JPH01253059A (fr)
DE (1) DE68923684T2 (fr)
WO (1) WO1989009448A1 (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5055999A (en) 1987-12-22 1991-10-08 Kendall Square Research Corporation Multiprocessor digital data processing system
IE63461B1 (en) * 1989-09-11 1995-04-19 Jeremy Owen Jones Improvements in and relating to stable memory circuits
DE59209766D1 (de) * 1992-08-19 1999-12-09 Siemens Nixdorf Inf Syst Multiprozessorsystem mit Cache-Speichern
EP0739517B1 (fr) * 1994-01-10 2000-08-16 The Dow Chemical Company Ordinateur superscalaire a architecture harvard massivement multiplexee
US5464435A (en) * 1994-02-03 1995-11-07 Medtronic, Inc. Parallel processors in implantable medical device
US5555424A (en) * 1994-10-06 1996-09-10 The Dow Chemical Company Extended Harvard architecture computer memory system with programmable variable address increment
US5949982A (en) * 1997-06-09 1999-09-07 International Business Machines Corporation Data processing system and method for implementing a switch protocol in a communication system
US20040254965A1 (en) * 2001-03-02 2004-12-16 Eric Giernalczyk Apparatus for variable word length computing in an array processor

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4204251A (en) * 1977-12-28 1980-05-20 Finn Brudevold Interconnection unit for multiple data processing systems
JPS5899868A (ja) * 1981-12-08 1983-06-14 Nec Corp 並列処理方式
JPS59157761A (ja) * 1983-02-25 1984-09-07 Hitachi Ltd 線形計画問題計算用並列デ−タ処理方式

Also Published As

Publication number Publication date
DE68923684T2 (de) 1996-01-25
EP0369022A1 (fr) 1990-05-23
DE68923684D1 (de) 1995-09-07
US5084836A (en) 1992-01-28
EP0369022A4 (en) 1992-05-13
WO1989009448A1 (fr) 1989-10-05
EP0369022B1 (fr) 1995-08-02

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