JPH01251740A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPH01251740A JPH01251740A JP7892888A JP7892888A JPH01251740A JP H01251740 A JPH01251740 A JP H01251740A JP 7892888 A JP7892888 A JP 7892888A JP 7892888 A JP7892888 A JP 7892888A JP H01251740 A JPH01251740 A JP H01251740A
- Authority
- JP
- Japan
- Prior art keywords
- film
- crystal
- aluminum
- electrode wiring
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 24
- 239000013078 crystal Substances 0.000 claims abstract description 19
- 238000000034 method Methods 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000001259 photo etching Methods 0.000 claims abstract description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- IVHJCRXBQPGLOV-UHFFFAOYSA-N azanylidynetungsten Chemical compound [W]#N IVHJCRXBQPGLOV-UHFFFAOYSA-N 0.000 claims 1
- WNUPENMBHHEARK-UHFFFAOYSA-N silicon tungsten Chemical compound [Si].[W] WNUPENMBHHEARK-UHFFFAOYSA-N 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 5
- 238000013508 migration Methods 0.000 abstract description 5
- 230000005012 migration Effects 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 238000004544 sputter deposition Methods 0.000 abstract description 3
- 230000007547 defect Effects 0.000 abstract description 2
- 239000011229 interlayer Substances 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000012298 atmosphere Substances 0.000 description 3
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910002804 graphite Inorganic materials 0.000 description 2
- 239000010439 graphite Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- -1 tungsten nitride Chemical class 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
Abstract
Description
【発明の詳細な説明】
〔従来の技術〕
半導体集積回路装置における従来のアルミニウム配線法
は、シリコン基板上に絶縁膜を形成し、該絶縁膜を介し
て、該絶縁膜に開けられたコンタクト穴を通して、アル
ミニウム膜を形成し、該アルミニウム膜をホト・エッチ
ングにより電極配線となすのが通例であった。[Detailed Description of the Invention] [Prior Art] In the conventional aluminum wiring method for semiconductor integrated circuit devices, an insulating film is formed on a silicon substrate, and contact holes made in the insulating film are connected through the insulating film. It was customary to form an aluminum film through the wafer, and then photo-etch the aluminum film to form the electrode wiring.
しかし、上記従来技術によると、アルミニウム電極配線
が多結晶体となり、エレクトロ・マイグレーションやス
トレス・マイグレーションニヨリ断蔵し易いと云う課題
があった。However, according to the above-mentioned conventional technology, there is a problem that the aluminum electrode wiring becomes a polycrystalline substance and is easily broken due to electromigration or stress migration.
本発明は、かかる従来技術の課題を解決し、単結晶アル
ミニウム膜による半導体集積回路装置の電極配線を可能
とする製造方法を提供する事な目的とする。An object of the present invention is to solve the problems of the prior art and provide a manufacturing method that enables electrode wiring of a semiconductor integrated circuit device using a single crystal aluminum film.
上記課題を解決するために、本発明は半導体集積回路装
置の製造方法に関し、シリコン等の半導体基板上に８１
０２膜等の絶縁膜を形成し、該絶縁膜上にアルミニツム
膜を形成し、該アルミニウム膜をグラフオエピタキシャ
ル法により単結晶膜化した後、該単結晶膜アルミニウム
膜をホト・エッチングにより電極配線となす手段をとる
事及び、前記絶縁膜に開けられたコンタクト穴を通して
アルミニウム電極配線を多層配線するに際し、少くとも
コンタクト穴部の半導体基板上にタングステン膜又はタ
ングステン・シリサイド膜又はタングステン・ナイトラ
イド膜を形成する手段をとり、前記グラフオエピタキシ
ャル法により単結晶アルミニウム膜形成と該単結晶アル
ミニウム膜のホトエツチングによる電極配線となす手段
をとる。In order to solve the above problems, the present invention relates to a method for manufacturing a semiconductor integrated circuit device.
After forming an insulating film such as 02 film, forming an aluminum film on the insulating film, and converting the aluminum film into a single crystal film by grapho-epitaxial method, electrode wiring is formed by photo-etching the single crystal aluminum film. When wiring aluminum electrode wiring in multiple layers through the contact hole formed in the insulating film, at least a tungsten film, a tungsten silicide film, or a tungsten nitride film is formed on the semiconductor substrate in the contact hole portion. A means is taken to form a single crystal aluminum film by the grapho-epitaxial method and a means is taken to form an electrode wiring by photo-etching the single crystal aluminum film.
シリコン等の半導体基板上に５ｉｎ２膜を形成し、該５
１０２膜にパターンニング処理を施してアルミニウム膜
を全面にスパッタ法等で形成後、線状グラファイト・ヒ
ーター又は線状ランプ光をアルミニウム瞑表面に走査さ
せるいわゆるグラフォエピタキ処理する事により、通常
の全面加熱の場合にはアルミニウム膜は多結晶体となる
のに対し、単結晶体とする作用がある。この様にして形
成された単結晶アルミニウム膜をホト・エッチングによ
り電極配線となすことにより単結晶アルミニウム膜から
成る電極配線を形成する革ができ、単結晶アルミニウム
膜から成る電極配線では多結晶アルミニウム膜に存在す
る結晶粒界がなくなる為ニ、エレクトロ・マイグレーシ
ョンやストレス・マイグレーションが多結晶粒界から発
生する為に、これらマイグレーションの無いアルミニウ
ム電極配線を得ることができる作用がある。更に、シリ
コン等の半導体基板上のコンタクト穴部にＷ、ＷＳｉ、
やＷＮを形成する事によりグラフオ・エピタキシャル時
の昇温によるアルミニウムとシリコン等の半導体基板と
の反応によるスパイク（ＳｌをＡｔが腐蝕する）形成や
イジーール（コンタクト部で８１で射出する）形成等の
不具合をなくする作用がある。A 5in2 film is formed on a semiconductor substrate such as silicon, and the 5in2 film is formed on a semiconductor substrate such as silicon.
After patterning the 102 film and forming an aluminum film on the entire surface by sputtering, etc., we perform a so-called graphoepitaxy process in which a linear graphite heater or linear lamp light is scanned over the aluminum surface to form an aluminum film on the entire surface. In the case of heating, the aluminum film becomes a polycrystalline body, whereas it has the effect of turning it into a single crystalline body. By photo-etching the single-crystal aluminum film formed in this way to form an electrode wiring, a layer for forming an electrode wiring made of a single-crystal aluminum film is obtained. Since the crystal grain boundaries that exist in the polycrystalline grain boundaries are eliminated, electro-migration and stress migration occur from the polycrystalline grain boundaries, so that an aluminum electrode wiring free of these migrations can be obtained. Furthermore, W, WSi,
By forming WN, it is possible to form spikes (At corrodes Sl) due to the reaction between aluminum and semiconductor substrates such as silicon due to temperature rise during grapho-epitaxial process, and easy formation (injection at 81 at the contact part). It has the effect of eliminating problems.
第１図は本発明の一実施例を示すＡｔ膜のグラフオエピ
タキシャル法をＭＯ３型トランジスタに適用した場合を
例に工程順に示した′ものである。FIG. 1 shows the process order of an example in which the grapho-epitaxial method of At film according to an embodiment of the present invention is applied to an MO3 type transistor.
すなわち、（α）Ｓｉ基板１０表面には下地配線層とソ
ース・ドレイン領域となる拡散層２とフィールド酸化膜
としてのＳｉｎ、膜３とゲート５１０２＠４及びＰｏ１
ｙＳｉゲート６のゲート電極によるＭＯＳ）ランジスタ
が形成され、その表面に層間絶縁膜としてのＣｖＤＳ１
０２膜５と、ソース、ゲート及びドレイン領域に開けら
れた該ＣｖＤＳｉＯ□膜５へのコンタクト穴部にはＷＳ
ｉ膜７等が形成され、更にその表面全面にスパッタ法等
でｋｔＭを形成後、線状光１０を走査方向１１の如く走
査させる事により、Ａｔ膜の動的加熱による単結晶化を
行ない、当初多結晶Ａｔ膜８又はアモルファス状態であ
ったＡｔ１１は単結晶Ａｔ膜となって行くことになる。That is, on the surface of the (α) Si substrate 10, there are a base wiring layer, a diffusion layer 2 serving as a source/drain region, a Si film 3 as a field oxide film, a gate 5102@4, and a Po1
A MOS transistor is formed by the gate electrode of the ySi gate 6, and CvDS1 as an interlayer insulating film is formed on its surface.
02 film 5 and contact holes to the CvDSiO□ film 5 opened in the source, gate and drain regions.
After the i-film 7 and the like are formed, and KtM is further formed on the entire surface by sputtering or the like, the linear light 10 is scanned in the scanning direction 11 to single-crystallize the At film by dynamic heating. The polycrystalline At film 8 or At11, which was initially in an amorphous state, becomes a single crystal At film.
次で、（ｂ）全面単結晶化されたＡｔ膜にホト・エッチ
ング処理により単結晶Ａｔから成るＡＡ電極配線１２が
形成されることとなる。Next, (b) AA electrode wiring 12 made of single-crystal At is formed on the entire surface of the single-crystal At film by photo-etching.
本例の場合はコンタクト穴部にＷＳｉ膜を形成した例を
示したがＷのみでも良く、ＷＮでも良い事は云うまでも
なく、又、Ａｔ多層配線の場合は下地Ａｊ電線のコンタ
クト部表面には必ずしもこれらＷやＷＳｉ、ＷＮ等を形
成しなくても良く、ＷやＷ Ｓ ｉ 、 Ｗ Ｎ等はコ
ンタクト穴部から突き出た構造で形成されていても良い
。In this example, a WSi film is formed on the contact hole, but it goes without saying that W alone or WN may also be used. Also, in the case of At multilayer wiring, a WSi film may be formed on the surface of the contact portion of the underlying Aj electric wire. It is not necessarily necessary to form these W, WSi, WN, etc., and W, WSi, WN, etc. may be formed in a structure protruding from the contact hole portion.
更に線状光１０は棒状のグラファイトヒーターをＳｉウ
ェーハ等の表面に近接させながら走査させても良く、又
、棒状のＡｒランプやハロゲンランプ光を棒状のレンズ
あるいはセルフォックス・レンズで３１ウエーハ等の表
面に棒状光になる様にし、Ｓｉウェーハ等を移動させ、
Ｓｉウエーノ＼表面に実質的に線状光１０が走査させる
事になれば良い。Furthermore, the linear light 10 may be scanned with a rod-shaped graphite heater brought close to the surface of the Si wafer, etc., or the light of a rod-shaped Ar lamp or halogen lamp may be scanned using a rod-shaped lens or Selfox lens. Move the Si wafer etc. so that it becomes a bar-shaped light on the surface,
It is sufficient if the linear light beam 10 is substantially scanned over the Si wafer surface.
又、Ａｔ膜のグラフオ・エピタキシャル処理は不活性雰
囲気か還元雰囲気あるいは真空中で行なうがＡｔ膜表面
に５１０２膜やＳｉ、Ｎ４膜をＯＶＤ法等で形成して、
グラフオ・エピタキシャル処理をするいわゆるキャップ
ド・アニール処理を飾しても良く、その場合はせいぜい
窒素雰囲気でグラフオ・エピタキシャル処理を施すこと
ができ、大気雰囲気中でもグラフオ・エピタキシャル処
理が可能ともなる。In addition, the grapho-epitaxial treatment of the At film is performed in an inert atmosphere, reducing atmosphere, or vacuum, but a 5102 film, Si, or N4 film is formed on the surface of the At film by the OVD method, etc.
A so-called capped annealing process that performs a grapho-epitaxial process may also be used. In that case, the grapho-epitaxial process can be performed in a nitrogen atmosphere at most, and the grapho-epitaxial process can also be performed in an air atmosphere.
本発明により半導体集積回路装置のＡｔ電極配線が単結
晶Ａ７で行なう事ができ、マイグレーションによるＡ、
４断線不良を防止する事ができる効果がある。According to the present invention, At electrode wiring of a semiconductor integrated circuit device can be performed using single crystal A7, and A,
4. It has the effect of preventing disconnection defects.
す半導体集哨回路におけるＡｊ配線の単結晶化処理を工
程順に示した図である。
１・・・・・・・・・Ｓ１基板
２・・・・・・・・・拡散層
３・・・・・・・・・５ｉ０２膜
４・・・・・・・・・ゲー） Ｓ ｉ ０２膜５・・・
・・・・・・０ＶＤＳｉＯ２膜６・・・・・・・・・Ｐ
Ｏ１ｙＳｉゲート７・・・・・・・・・ＷＳｉ膜
８・・・・・・・・・多結晶Ａｔ膜
９・・・・・・・・・単結晶Ａｔ膜
１０・・・・・・線状光
１１・・・・・・走査方向
１２・・・・・・Ａｔ電極配線
以上
出願人 セイコーエプソン株式会社
第１図（α）ｒ Ｃｂ＞は本発明の一実施例を示詑１図
（０−〕
／
第１図（ｂ）
代理人 弁理士最上務（他１名）FIG. 3 is a diagram illustrating, in order of process, the single crystallization process of the Aj wiring in the semiconductor concentrating circuit. 1...S1 Substrate 2...Diffusion layer 3...5i02 Film 4...Ge) S i 02 membrane 5...
...0VDSiO2 film 6...P
O1ySi gate 7...WSi film 8...Polycrystalline At film 9...Single crystal At film 10...Line Shape light 11...Scanning direction 12...At electrode wiring Applicant: Seiko Epson Corporation Figure 1 (α) r Cb> shows an embodiment of the present invention (Figure 1) 0-〕 / Figure 1 (b) Agent: Chief Patent Attorney (1 other person)
Claims (2)
絶縁膜が形成され、該絶縁膜上にアルミニウム（Ａｌ）
膜を形成し、該アルミニウム膜をグラフォエピタキシャ
ル法により単結晶化膜化した後、該単結晶アルミニウム
膜をホト・エッチングにより電極配線となす事を特徴と
する半導体集積回路装置の製造方法。(1) An insulating film such as a SiO_2 film is formed on a semiconductor substrate such as silicon, and aluminum (Al) is formed on the insulating film.
1. A method for manufacturing a semiconductor integrated circuit device, comprising forming a film, converting the aluminum film into a single crystallized film by graphoepitaxial method, and then forming electrode wiring by photo-etching the single crystal aluminum film.
絶縁膜が形成され、該絶縁膜に開けられたコンタクト穴
を通してアルミニウム電極配線を多層配線する場合に、
少くともコンタクト穴部の半導体基板上にはタングステ
ン（Ｗ）膜又はタングステン・シリサイド（ＷＳｉ）膜
又はタングステン・ナイトライド（ＷＮ）膜が形成され
て成る事を特徴とする請求項１記載の半導体集積回路装
置の製造方法。(2) An insulating film such as a SiO_2 film is formed on a semiconductor substrate such as silicon, and when wiring aluminum electrode wiring in multiple layers through contact holes made in the insulating film,
2. The semiconductor integrated device according to claim 1, wherein a tungsten (W) film, a tungsten silicide (WSi) film, or a tungsten nitride (WN) film is formed on the semiconductor substrate at least in the contact hole portion. A method of manufacturing a circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7892888A JPH01251740A (en) | 1988-03-31 | 1988-03-31 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7892888A JPH01251740A (en) | 1988-03-31 | 1988-03-31 | Manufacture of semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01251740A true JPH01251740A (en) | 1989-10-06 |
Family
ID=13675531
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7892888A Pending JPH01251740A (en) | 1988-03-31 | 1988-03-31 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01251740A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5208187A (en) * | 1990-07-06 | 1993-05-04 | Tsubochi Kazuo | Metal film forming method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6012424A (en) * | 1983-06-03 | 1985-01-22 | エルメス・プレシザ・アンテルナシオナル・ソシエテ・アノニム | Feeder for printer or typewriter |
-
1988
- 1988-03-31 JP JP7892888A patent/JPH01251740A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6012424A (en) * | 1983-06-03 | 1985-01-22 | エルメス・プレシザ・アンテルナシオナル・ソシエテ・アノニム | Feeder for printer or typewriter |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5208187A (en) * | 1990-07-06 | 1993-05-04 | Tsubochi Kazuo | Metal film forming method |
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