JPH01244650A - Manufacture of semiconductor integrated circuit - Google Patents
Manufacture of semiconductor integrated circuitInfo
- Publication number
- JPH01244650A JPH01244650A JP7227788A JP7227788A JPH01244650A JP H01244650 A JPH01244650 A JP H01244650A JP 7227788 A JP7227788 A JP 7227788A JP 7227788 A JP7227788 A JP 7227788A JP H01244650 A JPH01244650 A JP H01244650A
- Authority
- JP
- Japan
- Prior art keywords
- aluminum
- wiring
- aluminum wiring
- aluminum oxide
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 42
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 16
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims abstract description 16
- 239000011229 interlayer Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims description 4
- 239000002344 surface layer Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 abstract description 18
- 238000005530 etching Methods 0.000 abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 238000007743 anodising Methods 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 239000012466 permeate Substances 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 8
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 1
- 210000004709 eyebrow Anatomy 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路の製造方法に関し、特にアルミ
ニウム配線を使用する多層配線形成工程を含む半導体集
積回路の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly to a method for manufacturing a semiconductor integrated circuit including a step of forming multilayer wiring using aluminum wiring.
従来、半導体集積回路における多層配線は、まず公知の
アルミニウムスパッタ技術、ホトレジスト技術及びアル
ミニウムエツチング技術を用いて下層アルミニウム配線
を形成し、次にＣＶＤ技術を用いて眉間絶縁膜を形成し
、次に眉間絶縁膜を選択エッチしてスルーホールを形成
した後、再びアルミニウムスパッタ工程、ホトレジスト
工程、アルミニウムエツチング工程を経て上層のアルミ
ニウム配線を形成するという方法で形成されていた。Conventionally, in multilayer wiring in semiconductor integrated circuits, a lower layer aluminum wiring is first formed using known aluminum sputtering technology, photoresist technology, and aluminum etching technology, then a glabella insulating film is formed using CVD technology, and then a glabella insulating film is formed using CVD technology. The insulating film is selectively etched to form through holes, and then the upper layer of aluminum wiring is formed through an aluminum sputtering process, a photoresist process, and an aluminum etching process again.
上述した従来技術の多層配線方法では、層間絶縁膜にス
ルーホールを形成する場合、ホトレジストにピンホール
等の欠陥が存在すると、スルーホール以外の部分の層間
絶縁膜も同時にエツチングされてしまい、上層のアルミ
ニウムエツチング時に下層アルミニウム配線もエツチン
グされてしまうという欠点がある。更に上層のアルミニ
ウム配線のエツチングを施す場合、下層のアルミニウム
配線の保護膜としては下層のアルミ配線形成後の眉間絶
縁膜が利用される。従って、眉間絶縁膜自身にピンホー
ルが存在した場合も上層のアルミニウムのエツチング時
に下層のアルミニウム配線もエツチングされてしまうと
いう欠点がある。In the conventional multilayer wiring method described above, when forming through holes in the interlayer insulating film, if there are defects such as pinholes in the photoresist, the interlayer insulating film in areas other than the through holes will be etched at the same time, causing damage to the upper layer. There is a drawback that the lower layer aluminum wiring is also etched during aluminum etching. Furthermore, when etching the upper layer aluminum wiring, the glabellar insulating film after the lower layer aluminum wiring is formed is used as a protective film for the lower layer aluminum wiring. Therefore, even if a pinhole exists in the glabella insulating film itself, there is a drawback that the lower layer aluminum wiring is also etched when the upper layer aluminum is etched.
以上説明した様に従来技術では層間絶縁膜に欠陥が存在
する場合、上層のアルミエツチング時に下層のアルミニ
ウム配線の一部もエツチングされてしまい、所望の配線
パターンが形成されず歩留の低下をきたす。また、場合
によっては半導体集積回路の信頼性を低下させる一要因
ともなり得るという欠点がある。As explained above, in the conventional technology, if there is a defect in the interlayer insulating film, part of the lower layer aluminum wiring is also etched during the upper layer aluminum etching, and the desired wiring pattern is not formed, resulting in a decrease in yield. . Furthermore, it has the disadvantage that it may become a factor in reducing the reliability of semiconductor integrated circuits in some cases.
本発明は、素子領域が形成された半導体基板に眉間絶縁
膜とアルミニウム配線を繰返して形成する多層配線工程
を含む半導体集積回路の製造方法において、下層アルミ
ニウム配線形成後に該下層アルミニウム配線の表面層を
酸化アルミニウムに変換する工程を含んで構成される。The present invention provides a method for manufacturing a semiconductor integrated circuit that includes a multilayer wiring process in which a glabella insulating film and aluminum wiring are repeatedly formed on a semiconductor substrate on which an element region is formed. It consists of a step of converting it into aluminum oxide.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｄ）は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention.
まず、第１図（ａ＞に示すように、シリコン基板１の上
に酸化Ｍ２を設け、その上に第１のアルミニウム配線３
を形成する。First, as shown in FIG. 1 (a), oxide M2 is provided on a silicon substrate 1, and a first aluminum wiring 3
form.
次に、第１図（ｂ）に示すように、陽極酸化法等を用い
て第１のアルミニウム配線３の表面を酸化アルミニウム
膜４に変換する。この酸化アルミニウム膜は電気的絶縁
性を有する。Next, as shown in FIG. 1(b), the surface of the first aluminum wiring 3 is converted into an aluminum oxide film 4 using an anodic oxidation method or the like. This aluminum oxide film has electrical insulation properties.
次に、第１図（ｃ）に示すように、眉間絶縁膜５を堆積
する。眉間絶縁膜として、例えばＣＶｒ）法を用いて５
ｉ０２膜を形成する（以下これをＣＶＤ−３ｉ０２膜と
いう）。次に、ホトリソグラフィ技術を用いてスルーポ
ール（図示せず）をあける。この場合、酸化アルミニウ
ム膜４に達するピンホール７が眉間絶縁膜５に存在し、
ピンホール７をエツチング液が滲透したとしても酸化ア
ルミニウム膜４があり、酸化アルミニウムはＣＶＤ−３
ｉ０２よりエツチング速度が遅いから、第１のアルミニ
ムラ配線３に達する孔は形成されない０次に、アルミニ
ウム膜６を被着する。Next, as shown in FIG. 1(c), a glabellar insulating film 5 is deposited. As an insulating film between the eyebrows, for example, using the CVr) method,
Form an i02 film (hereinafter referred to as CVD-3i02 film). Next, a through pole (not shown) is opened using photolithography technology. In this case, a pinhole 7 that reaches the aluminum oxide film 4 exists in the glabella insulating film 5,
Even if the etching solution penetrates the pinhole 7, there is an aluminum oxide film 4, and the aluminum oxide is CVD-3.
Since the etching speed is slower than that of i02, a hole reaching the first uneven aluminum wiring 3 is not formed.The aluminum film 6 is then deposited in the 0th order.
次に、第１図（ｄ）に示すように、ホトリソグラフィ技
術により余分のアルミニウムを除去し、第２のアルミニ
ウム配線８を形成する。アルミニウムのエツチング時に
も酸化アルミニウム膜４は侵されずに残る。層間絶縁１
１１５中にピンホール７が存在しても、電気的絶縁性の
酸化アルミニウム膜があるから、第１のアルミニウム配
線３と第２のアルミニウム配線８とが短絡することはな
い。Next, as shown in FIG. 1(d), excess aluminum is removed by photolithography to form a second aluminum wiring 8. Even during aluminum etching, the aluminum oxide film 4 remains uncorroded. Interlayer insulation 1
Even if the pinhole 7 exists in the pinhole 115, the first aluminum wiring 3 and the second aluminum wiring 8 will not be short-circuited because of the electrically insulating aluminum oxide film.
以上説明したように、本発明は、下層アルミニウム配線
の表面を酸化アルミニウムで覆うようにしたので、その
後の工程におけるエツチングにおいても下層アルミニウ
ム配線に達する貫通孔が形成されず、従って上層アルミ
ニウム配線と下層アルミニウム配線とが短絡しないとい
う効果を有する。As explained above, in the present invention, since the surface of the lower layer aluminum wiring is covered with aluminum oxide, a through hole reaching the lower layer aluminum wiring is not formed even in the subsequent etching process, and therefore, the upper layer aluminum wiring and the lower layer This has the effect of preventing short-circuiting with aluminum wiring.
第１図（ａ）〜（ｄ）は本発明の一実施例を説明するた
めの工程順に示した半導体チップの断面図である。
１・・・シリコン基板、２・・・酸化膜、３・・・第１
のアルミニウム配線、４・・・酸化アルミニウム膜、５
・・・層間絶縁膜、６・・・アルミニウム膜、７・・・
ピンホール、８・・・第２のアルミニウム配線。FIGS. 1(a) to 1(d) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining one embodiment of the present invention. 1... Silicon substrate, 2... Oxide film, 3... First
aluminum wiring, 4...aluminum oxide film, 5
... Interlayer insulating film, 6... Aluminum film, 7...
Pinhole, 8...second aluminum wiring.
Claims (1)
ミニウム配線を繰返して形成する多層配線工程を含む半
導体集積回路の製造方法において、下層アルミニウム配
線形成後に該下層アルミニウム配線の表面層を酸化アル
ミニウムに変換する工程を含むことを特徴とする半導体
集積回路の製造方法。In a method for manufacturing a semiconductor integrated circuit that includes a multilayer wiring process in which an interlayer insulating film and aluminum wiring are repeatedly formed on a semiconductor substrate on which an element region is formed, the surface layer of the lower aluminum wiring is converted to aluminum oxide after forming the lower aluminum wiring. 1. A method for manufacturing a semiconductor integrated circuit, comprising the step of:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7227788A JPH01244650A (en) | 1988-03-25 | 1988-03-25 | Manufacture of semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7227788A JPH01244650A (en) | 1988-03-25 | 1988-03-25 | Manufacture of semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01244650A true JPH01244650A (en) | 1989-09-29 |
Family
ID=13484630
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7227788A Pending JPH01244650A (en) | 1988-03-25 | 1988-03-25 | Manufacture of semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01244650A (en) |
-
1988
- 1988-03-25 JP JP7227788A patent/JPH01244650A/en active Pending
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