JPS6177342A - Formation of multilayer wiring - Google Patents

Abstract

PURPOSE:To form multilayer wirings having no possibility of disconnection without causing the deterioration in characteristic of the title device by including the process of forming the first layer wiring, process of forming as insulation film of approximately the same thickness as that of the first layer wiring, and process of flattening the insulation film with regard to the first layer wiring. CONSTITUTION:The insulation film 13 of approximately the same thickness as that of the first layer wiring, e.g. an Si3N4 film is formed. Next, the insulation film 13 is selectively removed in a part 13' present above the first wiring layer 12, and a resist pattern 14 is formed in the part 13' resulting from removal of the film 13 at the part 13' above the wiring 12 in order to flatten the surface. Using the mask of this resist pattern 14, the film 13 at the part 13' above the wiring 12 is etched away with e.g. CF4 gas 18, resulting in flattening. After contact holes 16 are opened in the interlayer insulation film 15 above required parts of the wiring 12, the second layer wiring 17 is formed likewise as the first layer wiring 13. Repetion of the above-mentoined processes on the wiring 17 enables the formation of a multilayer wiring of three or more layers.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming multilayer wiring, and more particularly, to a method for forming multilayer wiring in semiconductor devices, particularly integrated circuits.

[Conventional technology]

2. Description of the Related Art As semiconductor devices, particularly integrated circuits, have electrode wirings, multilayer wiring formation methods have come to be used as the degree of integration increases.

The conventional method for forming multilayer wiring in this type of semiconductor device involves the following process 1! Take it and measure it. That is, on a semiconductor substrate, for example, on a silicon substrate on which a transistor has been formed,
First layer wiring! After that, the first layer I! is formed by, for example, a plasma CVD method. A Si, N4 film (, 9 (nitride film)) is formed as an interlayer insulating film on the entire surface of the substrate including the contact hole. Next, the Si and N4 films in the contact hole area are removed by etching. A second layer wiring is formed on this Sd, N4 interlayer insulation layer 1.

In the two-layer wiring structure formed by the conventional multilayer wiring formation method described above, an insulating film such as St or N4 film exists on the first layer wiring except for the through-hole area, and a second layer Wiring is provided.

The wiring structure thus formed had the following defects. In other words, at the point where the second layer wiring intersects the first layer wiring, there is a large step due to the #11 layer wiring, so when the above insulation is provided on top of it, the level difference that occurs in the insulating film The height difference is 5 tar, and the second layer wiring at the step is not thin, so it is easy to cause wire breakage. Attempts have been made to improve the wiring yield by flattening the stepped portions that occur in the insulating film.

For this purpose, a conventionally attempted method 'e#12 will be explained.

FIG. 2 (51) shows #11 on the entire surface of the semiconductor substrate 21.
Metal layer for layer wiring (not shown in Fig. 2(a))
An insulating film 22, for example, a 5isN4 film, is formed to have a thickness similar to
Check out A! It shows a cross section of the corresponding portion of the semiconductor device substrate 21 after being removed by dry etching using a gas 26 containing J4 as a main component, using π as a mask.

In this case, the dimensions of the portion 27 of the insulating film 22 removed by the above-mentioned etching do not change much in the illustrated through-opening bottom portion or the bottom portion, but the semiconductor substrate portion 28 at the bottom portion is etched by the etching gas 26. There is a risk of damage.

In the state where the above process is completed, that is, in the state shown in FIG. When the process is completed, the state shown in FIG. 2 (6) is reached.

In this way, only the metal 24' deposited on the etched away portion 27 of the insulating film 22 remains, and this metal 24' can form the first layer S. Since the film 22 and metal 24' remain, the optical surface becomes flat. After that, an interlayer insulating film 25 is formed to obtain a flat gold surface, and a second layer of φ is formed on this film without causing disconnection.
e can be formed.

However, according to this formation method, during the etching shown in FIG. For this reason, it is not suitable as a method for forming electrode parts because of the drawbacks that cause deterioration.At this time, when this etching is carried out by a chemical process or a tecking method that causes less damage, the etching is difficult to process with precision. This results in isotropic etching.

Therefore, after processing the surface of the semiconductor substrate 210, as shown in FIG.
If chemical etching is performed to obtain the state shown in FIG. After the engineering process is completed, when the first layer wiring metal 24' is deposited, a groove 27' is formed around the wiring metal 24'.
When ft is formed, it cannot be completely flattened and a step 29 remains, and #! If two-layer wiring IiI is applied, there is a risk of the above-mentioned disconnection.

[Problems that the invention attempts to solve]

The present invention solves the above-mentioned problems of the conventional multilayer wiring formation method for semiconductor devices, especially integrated circuits, and eliminates the possibility of deterioration of characteristics and the possibility of disconnection in the multilayer wiring. The purpose of this paper is to provide a method of formation.

Means for Solving Problem c] The multilayer interconnection forming method according to the present invention includes a process for forming a first layer interconnect on a semiconductor substrate and a process for manufacturing the substrate on which the first layer interconnect is formed. Insulation with the same thickness as the first layer wiring*
1--A step of forming, and a step of etching and removing a portion of the insulating film on the first layer wiring using a resist pattern as a mask to planarize the insulating film with respect to the first layer wiring.

The above-mentioned problems in the prior art can be solved by the multilayer wiring forming method of the present invention.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 (ω-0) is a cross-sectional view of a semiconductor substrate in the order of steps on which a multilayer interconnection forming method according to the present invention is performed.

In FIG. 1(G), in order to flatten the step caused by the first layer wiring 12 formed on the semiconductor substrate 11, an insulating film 13 having the same thickness as the first layer wiring 12, For example 54
Form an sN4 film. FIG. 1-) shows a state 1m in which the formation of the insulating film 13 described above has been completed.

Next, a portion 15' of the insulating film (EtHN4 film) 15 existing on the first layer wiring 12 is selectively removed to planarize the optical surface of the first layer wiring of the insulating film 15. A resist pattern 14 is formed on the portion 15 excluding the portion 15' on the resist pattern 12. The state after the above steps are shown in FIG. 1 (6).

In the above process, it is necessary to form the resist pattern 14 with high alignment accuracy with respect to the first layer wiring 12.
The alignment with the above-mentioned precision can be achieved by using, for example, a known reduction projection electro-optical device which is capable of alignment with a high precision of ±0.1 μm for pattern formation.

In the state shown in FIG. 1 (6), the insulating film 1 is then
Using a 14"ft mask of the resist pattern formed on the portion 15'' excluding the first layer wiring 12 of No. 3, the portion 15' of the insulating film 13 on the first layer wiring 12 is coated with, for example, CF4 gas 18. Interlayer insulating film 1 removed by etching
5 is formed to realize flattening of the six insulating surfaces. FIG. 1(o) is a diagram showing the state on the right after the above steps have been completed.

Thereafter, as shown in FIG. 1(d), M contact holes (through holes) 14 are formed in the interlayer insulating film 15 at required locations on the first layer wiring 12, and then the second layer wiring 17 is formed. Although it is formed in the same manner as the first layer wiring 12, the interlayer insulating film 15 is flattened and there is no stepped portion, so the second layer wiring 12 is formed.
7, there is a risk of wire breakage.

By repeatedly carrying out the above-described process of the present invention on the first layer wiring 12, it is possible to form further multilayer wiring of 95 or more layers.

Although one embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications can be made within the technical scope thereof.

For example, an insulating film used for planarization (#11 (,) to (d)
13) in ) is 842N, not limited to membranes,
It suffices if the insulating film has the same thickness as the first layer wiring 12,
It may be an inorganic film or an organic film. Further, for etching the insulating film 13 in the process of the present invention, either a chemical etching method or a VH physical etching method may be used.

〔Effect of the invention〕

Since the present invention is configured as described above, it is possible to form a multilayer wiring in a semiconductor device, especially an integrated circuit, without causing deterioration of the characteristics of the semiconductor device and without fear of disconnection. There are effects that can be formed.

[Brief Description of the Drawings] Figure 1i1 is a process-order cross-sectional view of a semiconductor substrate according to an embodiment of the present invention, and Figure 2B) * (6) + (a) is a process-order cross-sectional view of a semiconductor substrate according to the prior art. %1IK2 Figure (d) is a cross-sectional view of a semiconductor substrate obtained by a conventional technique different from the above.

Claims (1)

[Claims] a step of forming a first layer wiring on a semiconductor substrate;
A step of forming an insulating film having the same thickness as the first layer wiring on the substrate on which the layered wiring is formed, and etching a portion of the insulating film on the first layer wiring using a resist pattern as a mask. and removing the insulating film to planarize the insulating film relative to the first layer wiring.