JPH0536841A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it possible to apply wiring, whose inter-layer capacity is small, not only to a wiring in the uppermost layer but also to a wiring in an arbitrary layer without shorting or disconnection in a state that the flatness of an element is held by a method wherein in a state that the space on the periphery of the first layer wiring is held, a wiring is formed in an inter-layer insulating film. CONSTITUTION:A small hole 7 is formed only in the upper portion of a first layer wiring 4, which consists of an insulating film, using the resist 10 and a dry etching is performed through this hole 7. After the resist 10 is removed, a spin-on glass film 3 is applied from over an insulating film 2 and after the film 3 is subjected to sintering, contact holes between a first layer and a second layer are formed to form a second layer wiring 5. At this time, as the surface tension of the film 3 is high, the film 3 does not intrude into the hole 7 and it becomes possible that the hole 7 is filled with the film 3 in a state that a space 6 on the periphery of the wiring 4 is held. Thereby, the wiring 4 can be buried in an inter-layer insulating film in the state that the space 6 on the periphery of the wiring 4 is held and a wiring structure, wherein the interwiring capacity between the wirings 4 and 5 is small, becomes possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a wiring used in an integrated circuit of a field effect transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIG. 4 shows a wiring structure of a conventional semiconductor integrated circuit. In FIG. 4, the same numbers or symbols are used for parts equivalent to those in FIGS. FIG. 4 (a) shows a direct wiring 4 on the interlayer insulating film as wiring.
Is shown, the interlayer insulating film 1 is deposited thereon, and the second layer wiring 5 is formed thereon. Figure 4 (b)
Shows an air bridge wiring structure having a space between the first layer wiring 4 and the second layer wiring 5.

[0003]

However, FIG. 4 (a)
The conventional wiring structure shown in (1) has a problem that the inter-wiring capacitance becomes large because of the presence of the interlayer insulating film 1 between the wirings, which has a great influence particularly at high frequency operation. Further, since the line thickness of the wiring 4 is reflected in the upper layer insulating film, the flatness of the element cannot be maintained, and the problem of disconnection of the wiring 5 formed in the upper layer occurs. Fig. 4 (b) shows the structure of the air bridge wiring for the purpose of reducing the capacitance between wirings. However, it is not possible to flatten the element with this structure, so the wiring of the upper layer should be created. Therefore, it is impossible to fabricate a multilayer wiring structure using a wiring structure having a small inter-wiring capacitance as an arbitrary layer wiring. In addition, the weight of the wiring causes the wiring to bend in the middle, which may cause a short circuit or a break in the wiring. Therefore, a method of surrounding the wiring metal with a metal having a high Young's modulus and holding it so that the wiring does not bend is also being studied (Technical Report of the Institute of Electronics, Information and Communication Engineers ED90-151 Vol.90 No.381 p. 49).

However, in the case of the air bridge wiring, since the wiring thickness is usually as thick as 1 to 2 .mu.m, the workability of the wiring is deteriorated and it is difficult to make the wiring finer and have a multi-layer structure. In this method, a wiring in which a space around the wiring is formed is formed in the interlayer insulating film, and a spin-on-glass film is used to embed the space around the wiring in the interlayer film while holding the space. Another object of the present invention is to provide an excellent wiring of a semiconductor integrated circuit and a method of manufacturing the same by simultaneously achieving a reduction in inter-wiring capacitance, flattening of elements, and a stable wiring structure free from short circuits and disconnections. There is.

[0005]

In order to solve the above-mentioned problems, the present invention has at least two or more kinds of insulating films having different dry etching rates deposited on the wiring in the order of high etching rate as wiring of a semiconductor integrated circuit device. A spin-on-glass film was applied and sintered in a state in which a space having an insulating film layer and through which small holes were formed in the uppermost insulating film and only the insulating film around the wiring having a high dry etching rate was removed by dry etching was held. A wiring structure of a semiconductor integrated circuit is used, which has a structure and on which an upper layer wiring is formed.

Further, in order to solve the above-mentioned problems, the present invention solves the above-mentioned problems by forming a wiring 4 as a wiring of a semiconductor integrated circuit element, depositing an interlayer film 1 on the wiring 4, and forming a wiring on the interlayer film 1. A step of depositing an interlayer film 2 whose dry etching rate is much lower than that of the interlayer film 1, and a step of forming a large number of small holes along the shape of the wire 4 in the interlayer film 2 above the wire 4. , A step of removing the interlayer film 1 around the wiring 4 by dry etching through the small holes, a step of applying a spin-on-glass film 3 from above and sintering the same, and a step of coating the spin-on-glass film 3 on the spin-on-glass film 3 as a second layer wiring. A method for manufacturing a semiconductor integrated circuit wiring, which has a step of forming the wiring 5, is sequentially performed.

[0007]

With the above structure, the present invention makes it possible to remove the insulating film existing between the wirings and embed it in the interlayer film while leaving a space around the wirings. In this case, the inter-wiring capacitance C is expressed by Equation 1 when the capacitance of the spin-on-glass film is C ₁ and the capacitance of the space above the wiring is C ₂ .

1 / C = 1 / C ₁ + 1 / C ₂ Equation 1 As is clear from Equation 1, when C ₂ is much smaller than C ₁ , C is almost equal to C ₂ . In the present wiring structure, the space capacitance C ₂ is extremely small, so that the inter-wiring capacitance C can be suppressed to a very small value.

Further, with this wiring structure, the element is flattened by coating the spin-on-glass film on each layer, so that the wiring having a small inter-wiring capacitance can be used as the wiring of any layer. Further, in this wiring structure, since there is no space immediately below the wiring, there is no problem of wiring short circuit or disconnection due to bending of the wiring in the air bridge wiring.

According to the manufacturing method of the third aspect of the present invention, the wiring can be embedded in the interlayer insulating film while the space around the wiring is maintained, and at the same time the element can be planarized. This is because the spin-on-glass film is applied in order to close the small holes formed in the insulating film above the wiring used for dry etching. That is, the surface tension of the spin-on-glass film can prevent the coating film from penetrating into the small holes, and the small holes can be closed by sintering the spin-on-glass film. Further, since the spin-on-glass film is used to planarize the wiring at the same time, the wiring structure can be multi-layered at the same time, and a wiring structure with a small inter-wiring capacitance can be used for any layer wiring. Become.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a wiring structure manufactured by using the manufacturing method of the present invention. Reference numeral 1 is an interlayer insulating film, and a SiN film was used in this embodiment. Reference numeral 2 is an insulating film having a slower dry etching rate than 1;
_Two membranes were used. Reference numeral 4 represents the first layer wiring. Reference numeral 5 is a second layer wiring, which intersects with the first layer wiring 4 through the space 6 and the interlayer insulating film. 6 is a space formed above the wiring.
Reference numeral 3 denotes a spin-on-glass film applied and sintered to close the small holes while maintaining the space 6 above the first layer wiring 4. By repeating the above-described configuration of the present invention on the second-layer wiring, it is possible to form a similar wiring structure having a small inter-wiring capacitance in a multilayer structure.

Next, the manufacturing method will be described with reference to FIG.
Reveal FIG. 2 shows a method for manufacturing a semiconductor device of the present invention.
FIG. In the semiconductor device of the present invention shown in FIG.
The same reference is made to the parts equivalent to those in FIGS.
It shall be indicated with a number. FIG. 2 (a) shows an integrated circuit first
This is the process of forming the layer wirings 4 and 8, and the wiring is now
Time Au was used. The first layer wiring 4 contacts the second layer wiring
The first layer wiring 8 is the second layer wiring.
It is the wiring that makes contact with. Figure 2 (b) shows that
SiN is deposited to 1 μm as the edge film 1 and the insulating film
2 as SiO ₂Of 0.2 μm is deposited on the insulating film 2.
3 μm above the first layer wiring²Between the first and second layer wiring
This is the step of forming the contact hole 9 of FIG. Figure 2 (c)
Is a large number of small holes only above the first layer wiring 4 of the insulating film.
2 μm using resist 10 to make²Small hole 7
And make CF through the small holes 7._Four/ O₂For mixed gas
The insulating film 1 by dry etching
It shows the steps performed. At this time, dry etching
The shape of the small holes 7 hardly changes due to the high selection ratio
Yes. 2 (d) shows that after the resist 10 is removed, the
The spin-on-glass film 3 was applied from above the edge film 2 and sintered.
Later, a contact hole between the first layer and the second layer is formed,
A process of forming the two-layer wiring 5 is shown. At this time, spin on
Since the glass film 3 has high surface tension, it penetrates into the small holes 7.
I haven't. Therefore, the space 6 around the first layer wiring 4 is
It is possible to close the small hole 7 in the state of being held.

As described above, it becomes possible to embed the first layer wiring 4 in the interlayer insulating film while maintaining the space 6 around the wiring, and the space between the first layer wiring 4 and the second layer wiring 5 can be obtained. It is possible to create a wiring structure having a small inter-wiring capacitance as a stable wiring having no problem of short circuit or disconnection. Further, by repeating this process, it becomes possible to make the present wiring structure multi-layered as shown in FIG.

The wiring structure of the present invention shown in FIG. 1 is produced using the process shown in FIG. 2 and the inter-wiring capacitance is measured. The result is shown in FIG. The inter-wiring capacitance of the air bridge wiring structure is about 2/3 that of ordinary wiring. Further, when the structure of the present invention is used (the air gap is the same as that of the air bridge wiring), the inter-wiring capacitance has almost the same value as that of the air bridge wiring structure. From this, it is possible to significantly reduce the inter-wiring capacitance that affects the delay time of the high frequency FET operation by making this wiring structure multi-layered.

[0015]

As described above, the present invention brings the following effects. 1) By using the structure in which the wiring is embedded in the interlayer film while maintaining the space around the wiring, the capacitance between the wirings is significantly reduced. 2) By embedding a wiring structure having a small inter-wiring capacitance in the interlayer insulating film by using a spin-on-glass film, flattening of the device is realized, and a wiring having a small inter-wiring capacity is formed by only the conventional uppermost layer 1 layer ( In addition to air bridge wiring, it is possible to form a multilayer wiring structure. 3) By using the wiring structure of the present invention, a wiring having a small inter-wiring capacitance can be stably formed without causing a problem of short circuit or disconnection.

[Brief description of drawings]

1 is a structural sectional view of the present invention.

FIG. 2 is a process sectional view showing a manufacturing method according to an embodiment of the present invention.

FIG. 3 is a characteristic diagram showing a comparison between inter-wiring capacitance created using the present invention and a conventional example.

FIG. 4 is a structural cross-sectional view showing a conventional wiring method.

[Explanation of symbols]

1 Insulating Film 2 Insulating Film 3 Etching Rate Slower Than Insulating Film 1 Spin-on-Glass Film 4 First Layer Wiring 5 Second Layer Wiring 6 Space Around Wiring 7 Small Hole Formed in Insulating Film 2 Contact Second Layer Wiring First layer wiring 9 Contact hole formed in insulating film 2 for forming contact between first layer wiring and second layer wiring 10 Resist

Claims (3)

[Claims] 1. A wiring for a semiconductor integrated circuit device, comprising an insulating film layer formed by depositing at least two or more kinds of insulating films having different dry etching rates on the wiring in descending order of etching rate, and forming the uppermost insulating film. While maintaining the space where only the insulating film around the wiring with a high dry etching rate was removed by dry etching through the small holes,
A semiconductor device having a structure in which a spin-on-glass film is applied and sintered, and an upper layer wiring is formed thereon. 2. The wiring structure according to claim 1, at least 2.
A semiconductor device, which is used for wiring in any layer of at least one layer. 3. A step of forming a wiring on a semiconductor substrate as a wiring of a semiconductor integrated circuit element, a step of depositing a first insulating film on the wiring, and a dry etching on the first insulating film. Depositing a second insulating film having an etching rate smaller than that of the first insulating film; forming a large number of small holes along the wiring shape in the second insulating film above the wiring; Removing the first insulating film around the wiring by dry etching through the small holes;
Applying a spin-on-glass film on the second insulating film,
A method of manufacturing a semiconductor device, comprising: a step of sintering and a step of forming an upper layer wiring thereon.