JPH01243589A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce an occupation area of a resistance element by employing a high impurity concentration buried layer as the resistance element and forming most part of the high impurity concentration buried layer within a projection region of a MOSFET. CONSTITUTION:A P type semiconductor region 5-1 is formed in an N type semiconductor region 4 by impurity diffusion, constituting a well region of a longitudinal power MOSFET 50. An N<+> type semiconductor region 7 constitut ing a source region. An N<+> type semiconductor region 6 formed on the surface fraction of an N<+> type semiconductor region 3 forms a drain contact region of a longitudinal power MOSFET 50. P<+> type semiconductor regions 9-1, 9-2 formed in the N type semiconductor region 4 constitute a drain region and a source region of a P MOS transistor 18 of a CMOS circuit, respectively. Drain resistance formed in a projection region of the longitudinal power MOSFET 50 is produced owing to the N<+> semiconductor region 3 and the N type semiconductor region 4, whereby an occupation area of electrostatic break down protective element in the semiconductor device can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and more particularly to a semiconductor device that occupies a small area and has an electrostatic protection function.

(Prior Art) Conventionally, an input section of an integrated circuit device has been provided with a circuit for protecting a gate insulating film of an internal circuit from an excessive input voltage such as external noise or surge.

FIG. 8 is a schematic chip layout diagram of a general integrated circuit 40 having an electrostatic protection circuit 43 in the manual stage.

In the figure, an input signal input from the input terminal 13a is inputted to the input buffer 7 circuit 45 via the electrostatic protection circuit 43. This human input signal is processed in the internal logic circuit 46 and then output from the output terminal 42 via the output buffer circuit 47.

FIG. 9 is a block diagram showing this electrostatic protection circuit 43 and a human power buffer 7 circuit 45 which is the closest to the input terminal 13a among the internal circuits.

Typically, electrostatic protection circuit 43 is divided into two parts. 1
One is a delay circuit section 55 that slows down the sharp rise of the input voltage waveform, and the other is a clamp circuit section 54 that defines the maximum value of the input terminal and clamps voltages exceeding this value.

The delay circuit section 55 consists of a series resistor and a capacitor, but since the capacitor is composed of the wiring capacitor including the clamp circuit section and the gate capacitor of the next stage, in reality only the series resistor is added. . The clamp circuit section 54 utilizes the reverse breakdown voltage of a diode and the breakdown voltage of a MOS diode diode-connected within a MOS transistor.

FIG. 10 is an equivalent circuit diagram specifically showing the contents of FIG. 9. Figures (a) and (b) show an electrostatic protection circuit 4 using a protective resistor 48, a diode 49, and a capacitor fit100.
This is an equivalent circuit when 3 is configured, and (e) and (
d) is an equivalent circuit when the electrostatic protection circuit 43 is configured using a protective resistor 48, a MOSFET 50 or 51, and a capacitor 100.

FIG. 11 shows the electrostatic protection circuit 43 shown in FIG.
FIG. 12 is a cross-sectional view of a semiconductor substrate on which is formed, and FIG. 12 is a top view thereof. In FIG. 11, an N-type single crystal substrate 6
The P-type diffusion layer 48 formed on the surface of the P-type diffusion layer 48 corresponds to the protective resistor 48 shown in FIG.
P-channel MOSFET 51 configured by 2-1
is the P-channel MOSFET 51 in FIG. 10(d).
corresponds to

In addition, NIJl formed on the surface of the P well region 5-2
Drain region 8-1 and source region 8 consisting of a diffusion layer
-2 constitutes an NMO8) transistor together with the gate electrode 12-2, which corresponds to the NMO3) transistor 17 in FIG. 10(d).

Furthermore, the PMO8) transistor 18, which is composed of a drain region 9-1, a source region 9-2, and a gate electrode 12-2, each of which is a P-type diffusion layer, is constructed of a P-type transistor 18 as shown in FIG. 10(d).
MO, S) corresponds to the transistor 18.

The NMOS transistor 17 and the PMO transistor 18 are connected to each other by a conductive layer 13e whose drain regions 8-1, 9-1 serve as output terminals, and constitute an input buffer circuit 45.

Furthermore, the P-type diffusion layers 61 provided at both ends of the MOSFET 51 can
This is a guard ring to prevent any influence from reaching anything other than the MOSFET 51, and is connected to the conductive layer 13r through a connection hole formed by selectively removing the silicon oxide film 1O and the insulating film 11. Note that this conductive layer 13'' is connected (not shown) to the lowest potential within the semiconductor device.

Furthermore, the source region 22 of the MOSFET 51 and the PM
O8) The source region 9-2 of the transistor 18 is connected to the highest potential in the CMOS circuit through the conductive layers 13b and 13f, and the source region 8-2 of the NMOS transistor 17 is connected to the highest potential in the CMOS circuit through the conductive layer 13d. Connected to the lowest potential in the CMOS circuit.

(Issue 2i to be solved by the invention) Usually, a resistive element is formed together with a semiconductor element in a semiconductor device, but in the conventional technology, the resistive element is formed on the same plane as the semiconductor element, and the integrated This was a major hindrance to improving performance.

In addition, as mentioned above, the protective resistor in the electrostatic protection circuit provided in the manual stage of the semiconductor device has a certain size in order to ensure sufficient current capacity to bypass overvoltage when it is applied to the input terminal. This trend was especially noticeable.

Furthermore, in the prior art, in order to prevent an adverse effect from being exerted on anything other than the MOSFET that constitutes the clamp circuit when an overvoltage is applied to the input terminal, the MOSFET
Guard rings or the like must be provided at both ends of the T, which also poses a major hindrance to improving the degree of integration of semiconductor devices.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a semiconductor device with an improved degree of integration by reducing the area occupied by a resistive element.

(Means for Solving the Problems) In order to achieve the above-mentioned object, the present invention provides semiconductor elements within a plurality of single crystal islands that are formed insulated from a semiconductor substrate and have regions exposed on the surface of the semiconductor substrate. forming a high impurity concentration buried layer for a resistance element along the inside of the interface with the substrate of the single crystal island, and exposing the high impurity concentration buried layer on the surface of the single crystal island. It is characterized by having contact parts at both ends.

Furthermore, the present invention is characterized in that the semiconductor element formed within the single crystal island is a MOSFET, and one of the contact portions is connected to an external input terminal and the other is connected to the drain region of the MOSFET.

Furthermore, the present invention provides a MOSFET formed within a single crystal island.
It is characterized in that it is a vertical MOSFET, and the conductivity type of its drain region is the same as that of the buried layer with high impurity concentration.

(Function) According to the above configuration, the buried layer with high impurity concentration can be used as a resistance element, and most of the buried layer with high impurity concentration can be formed within the projection area of the MOSFET. Therefore, the area occupied by the resistance element within the semiconductor device can be reduced.

Furthermore, the MOSFET is made into a vertical MOSFET, and the conductivity type of its drain region and the conductivity type of the buried layer with high impurity concentration are made the same, so that the drain resistance of the vertical MOSFET can also be used as a resistance element. So,
If the vertical MOSFET is used as a power MOSFET for clamping in an electrostatic protection circuit, the breakdown voltage can be improved without increasing the area of the semiconductor device.

Furthermore, since the single crystal island on which the MOSFET is formed is surrounded by a buried layer with high impurity concentration, the MOSFET
Even when used as a power MOSFET for clamping in an electrostatic protection circuit, there is no need to provide a guard ring or the like, and the area occupied by the electrostatic protection circuit within the semiconductor device can be further reduced.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a plan view of the first embodiment of the present invention, and FIG. 1 is a sectional view taken along the line AA in FIG. FIG. 3 is an equivalent circuit diagram of this embodiment.

In this example, dielectric isolation
In this embodiment, an N-channel vertical MOSFET on a substrate (hereinafter abbreviated as DI) is used as a voltage clamp circuit of an electrostatic protection element, and its drain resistance is used as a protection resistance.

In FIGS. 1 to 3, the same reference numerals as in FIGS. 10 to 12 represent the same or equivalent parts.

The method for manufacturing the DI substrate used in this example will be described below with reference to FIGS. 14(a) to 14(d).

First, on one side of the N-type single crystal silicon 4 shown in FIG. 4(a), a separation groove 80 is formed by anisotropic etching as shown in FIG. A silicon dioxide film 2 for dielectric isolation is deposited thereon.

Next, on this silicon dioxide film 2, a silicon polycrystalline layer 1 serving as a support is formed. Next, the single crystal side is shown in the same figure (
Polish to the position indicated by α-α in c).

As a result of the above process, as shown in FIG. 2(d), D
An I substrate is obtained.

In this embodiment, as shown in FIG. 1, a P-type semiconductor region 5-1 is formed within this N-type semiconductor region 4 by diffusion of impurities, and this Put2 semiconductor region 5-1
constitutes a well region of the vertical power MOSFET 50. An N++ semiconductor region 7 is formed within the P-type semiconductor region 5-1, and this constitutes the source region of the vertical power MOSFET 50.

The end of the N++ source region 7 on the gate electrode side is defined by a gate electrode 12-1, which will be described later, and extends under the gate electrode 12-1.

On the other hand, the peripheral portion of the N++ source region 7 other than the gate electrode side is defined by a mask made of, for example, a resist film.

On the surface of the N-type semiconductor region 4, a gate electrode 12-1 of a vertical power MO5FET 50 made of polycrystalline silicon or the like is formed.
The gate electrodes 12-2 of the NMOS transistor 17 and the PMOS transistor 18 are each formed through a silicon oxide film.

Furthermore, the gate electrode 12-1 is provided not only on the channel region but also on the N-type drain region 4. N++ semiconductor region 6 formed on the surface portion of N++ semiconductor region 3
It constitutes the drain contact region of the single-input vertical power MOSFET 50.

A conductive layer 13b made of, for example, an aluminum alloy layer is connected to the surfaces of the N++ source region 7 and the P-type well region 5-1 through a contact hole 14b formed by selectively removing the silicon oxide film 10 and the insulating film 11. has been done. Similarly,
In the N+ type drain contact region 6, a contact hole 1 is formed by selectively removing the silicon oxide film 10 and the insulating film 11 from the conductive layer 13a and the conductive layer 13c, which serve as input terminals, respectively.
4a and 14c.

N++ semiconductor regions 8-1 and 8-2 formed in the P-type semiconductor region 5-2 are each NMOS of a CMO3 circuit)
It constitutes the source region and drain region of the transistor 17. This N++ semiconductor region 8-1, 8-2 is defined by a gate 12-2 and a silicon oxide film lO.

P+ type semiconductor region 9- formed in N type semiconductor region 4
1.9-2 constitute the drain region and source region of the PMOS transistor 18 of the CMO3 circuit, respectively. , the P type semiconductor regions 9-1, 9-2 are also connected to the N+
+Similar to semiconductor region 8-1°8-2, gate electrode 12-
2 and the silicon oxide film 10.

N+ which constitutes the source region of transistor 17 (NMOS)
+ The semiconductor region 8-1 is connected to the conductive layer 13d through a connection hole formed by selectively removing the insulating film 11. Furthermore, this conductive layer 13d is connected to the lowest potential within the CMO8 circuit.

N++ which is the drain region of the NMOS transistor 17
The semiconductor region 8-2 is connected to the conductive layer 13e through a contact hole formed by selectively removing the insulating film 11, and
It is also connected to the drain region 9-1 of the OS transistor 18, and further connected to an internal logic circuit (not shown) as an output of the input buffer circuit.

On the other hand, the P+ type semiconductor region 9-2, which becomes the source region of the PMOS 18, is connected to the conductive layer 13f through the connection hole. Furthermore, this conductive layer 13f is connected to the highest potential within the CMO3 circuit.

The input terminal 13a constitutes a bonding pad made of, for example, an aluminum alloy layer, and is connected to the N++ semiconductor region 6.

Note that the P-type well 5-2 of the CMO8 circuit portion is connected to the lowest potential, and the N-type substrate 4 is connected to the highest potential (not shown).

Next, the operation of this embodiment will be explained using FIG. Third
In the figure, the drain resistance of the vertical power MOSFET 50 is shown divided into three parts 56a, 56b, and 57. The drain resistors 56a, 56b are each connected to a first drain resistor 56a, 56b.
The resistance from the connection hole 14a to just below the gate 12-1 and from the bottom of the gate 12-1 to the connection hole 14c in the figure is mainly due to the N++ conductor region 3, and the drain resistance 57 is mainly the resistance of the gate 12-1. N-type semiconductor region 4 directly below
represents the resistance due to

The input voltage value applied to the input terminal 13a is vertical power MOS
If the withstand voltage of the FET 50 is lower than that of the FET 50, the input signal is directly transmitted to the manual buffer 45 and transmitted to the internal logic circuit via the output terminal 13e.

On the other hand, when the input terminal becomes equal to or higher than the breakdown voltage of the vertical power MOSFET 50, the vertical power MOSFET 50 breaks down and becomes conductive. Therefore, Dairyoku Buffer 4
The voltage input to 5 connects the input terminal to resistors 56a and 57.
The gate of the input buffer 45 is protected from overvoltage.

In this way, according to this embodiment, the vertical power MOSFET
Drain resistors 56a, 5 formed within the projection area of 50
6b, 57 can be used as a protective resistor.

In other words, most of the protection resistors, which were conventionally formed on the same plane as the power MOSFET, have been replaced with the power MOSFET.
can be formed within the projection area. Therefore, the area occupied by the electrostatic protection element within the semiconductor device can be reduced.

FIG. 4 is a sectional view of a second embodiment of the present invention, and FIG. 5 is an equivalent circuit diagram thereof.

In Fig. 4, parts indicated by the same symbols as in Fig. 1 are the same as those in Fig. 1.
or its equivalent. Similarly, in FIG. 5, parts designated by the same reference numerals as those in FIG. 3 indicate the same or equivalent parts.

This example is D! The high concentration buried layer 20 of the substrate is formed into a single crystal region 4.
The high concentration buried layer 20 is formed to have a conductivity type opposite to that of the resistor, and is used as a protective resistor.
This is an example of forming a T.

In FIGS. 4 and 5, a P+ type semiconductor region 20 formed inside the silicon oxide film 2 constitutes a protective resistor 48 shown in FIG. The P+ type semiconductor region 32 formed in the surface portion of the N type semiconductor region 4 is the P+ type semiconductor region 20.
This becomes a contact area between the input terminal 13a and the input terminal 13a. The P+ type semiconductor region 21 formed on the surface of the N type semiconductor region 4 is 1
．． P-channel power MOSFE as voltage clamp circuit
It constitutes the drain region of T51.

Similarly, the P+ type semiconductor region 22 formed on the surface of the N-type semiconductor region 4 constitutes the source region of the P-channel power MOSFET 51.

Although not shown in FIG. 4, a terminal for supplying potential to the N-type semiconductor region 4 corresponding to the well of the P-channel MOSFET 51, which uses the P+-type semiconductor regions 21 and 22 as the drain region and the source region, respectively, is a terminal. , gate 12
-1 and the source terminal 13b are connected to the highest potential.

Next, the operation of this embodiment will be explained using FIGS. 4 and 5.

In FIG. 4, a conductive layer 13a serving as an input terminal is connected to a P+ type semiconductor region 20 forming a protective resistor 48 in a contact region 32. In FIG.

On the other hand, the conductive layer 13c connected to the contact region 32 on the opposite side is connected to the drain conductive layer 13g and also to the gate terminal 12-2 of the input buffer circuit 45.

In this embodiment having such a configuration, the input terminal 1
When the voltage applied to 3a becomes equal to or higher than the power supply voltage, the junction between the P 2 semiconductor region 20 and the N type semiconductor region 4 is biased in the forward direction, so that a current flows from the P 2 semiconductor region 20 to the power supply. Therefore, no overvoltage is applied to the internal circuit.

On the other hand, when the negative voltage applied to the input terminal 13a exceeds the breakdown voltage of the P-channel power MOSFET 51, the P-channel power MOSFET 51 breaks down and the power supply voltage is applied to the internal circuit.

FIG. 6 is a sectional view of the third embodiment, and FIG. 7 is a circuit diagram thereof. In Figure 6, Figure 1 or 4
Parts indicated by the same reference numerals as those in the figures indicate the same or equivalent parts. Similarly, in FIG. 7, parts designated by the same reference numerals as those in FIG. 3 or 5 indicate the same or equivalent parts.

In this embodiment, an N type high concentration buried layer 3 of a DI substrate is used as a protective resistor 48, a region of the opposite conductivity type is formed in the semiconductor region 4 on this buried layer 3, and a MOS serving as a protective element is formed in this region.
This is an example of forming an FET.

6 and 7, the P-type semiconductor region 5-1 formed on the surface of the N-type semiconductor region 4 is an N-channel MOS
This constitutes the P-well region of FET41. The N+ type semiconductor region 23 formed on the surface of the P type semiconductor region 5-1 constitutes the drain region of the N channel MOSFET 41 which serves as a voltage clamping element.

Similarly, the N-type semiconductor region 24 is an N-channel MOSFE.
It constitutes a source region of T41, and P+ type semiconductor region 25 constitutes a well power supply terminal of N-channel MOSFET41.

Therefore, the drain region 2 of the N-channel MOSFET 41
The conductive layer 13j connected to the N+ semiconductor region 3
The conductive layer 13C is connected to the input buffer side terminal of the resistor 48 (FIG. 7). The conductive layer 13i connected to the source region 24 is connected to the gate 1
2-1 and the conductive layer 13h connected to the well power supply terminal 25, it is connected to the lowest potential.

In this embodiment, when the input voltage value applied to the input terminal 13a is lower than the withstand voltage of the N-channel MOSFET 41, the input signal is directly transmitted to the human power buffer 745, and the output terminal 1
It is transmitted to the internal logic circuit via 3e.

On the other hand, when the input terminal becomes equal to or higher than the breakdown voltage of the N-channel MOSFET, the MOSFET 41 breaks down and becomes conductive. Therefore, the lowest potential of the semiconductor device is applied to the gate of the human power buffer 745.

FIG. 13 shows an embodiment in which an electrostatic protection circuit similar to the embodiment shown in FIG. 1 is formed on a PN junction isolation substrate, and the same reference numerals as in FIG. represents.

In this embodiment, in a P-type nested crystal silicon substrate 70, elements are separated by a P-type semiconductor region 73 for element isolation.
A type high impurity concentration region 71-1.74 is formed,
This N! The surface of the N-type epitaxial layer 72 formed inside the f2 high impurity concentration regions 71-1 and 740 has vertical! u
MO8FE750 is formed.

In this embodiment, the protective resistor 46 constituted by the N-type high impurity concentration layer 3 formed along the inside of the dielectric isolation insulating film 2 in the embodiment shown in FIG. It is formed by impurity concentration regions 71-1 and 74.

Furthermore, if the N-type high impurity concentration layer 71-2 is formed under the CMOS circuit composed of the NMO8) transistor 17 and the PMOS transistor 18 to lower the resistance of the N well of the CMO3 circuit, latch-up prevention can be achieved. You can also expect

The operation of this embodiment will be clear from the explanation of the operation of the embodiment shown in FIG.

Also in this embodiment, since the semiconductor region constituting the protection resistor is formed within the projection area of the vertical MOSFET 50 constituting the clamp circuit, the area occupied by the electrostatic protection circuit within the integrated circuit can be reduced. .

(Effects of the Invention) According to the present invention, the resistance element can be formed within the projection area of the MOSFET, and the area occupied by the resistance element in the semiconductor device can be reduced, so that the integration of the semiconductor device can be improved. It is possible to improve the degree of

Furthermore, since the MOSFET is made into a vertical MOSFET and the conductivity type of its drain region is made the same as that of the buried layer with high impurity concentration, the vertical MOSFET can be used as a power MOSFET for clamping in an electrostatic protection circuit. If used, the drain resistor can also be used as a resistance element, and the breakdown voltage of the electrostatic protection circuit can be improved without increasing the area. Moreover, M
Since the single crystal island where the OSFET is formed is surrounded by the buried layer with high impurity concentration, there is no need to provide a guard ring, and the area occupied by the electrostatic protection circuit within the semiconductor device can be further reduced.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a first embodiment of the invention. FIG. 2 is a plan view of the first embodiment. FIG. 3 is an equivalent circuit diagram of the first embodiment. FIG. 4 is a sectional view of a second embodiment of the invention. FIG. 5 is an equivalent circuit diagram of the second embodiment. FIG. 6 is a sectional view of a third embodiment of the invention. FIG. 7 is an equivalent circuit diagram of the third embodiment. FIG. 8 is a schematic diagram showing the on-chip layout of an integrated circuit having an electrostatic protection circuit. FIG. 9 is a block diagram of the electrostatic protection circuit. FIG. 10 is an equivalent circuit diagram of a conventional semiconductor device. FIG. 11 is a sectional view of the prior art. FIG. 12 is a plan view of the prior art. FIG. 13 is a sectional view of a fourth embodiment of the present invention. Figure TS14 is a cross-sectional view showing a method of manufacturing a dielectric insulation isolation substrate. DESCRIPTION OF SYMBOLS 1... Polycrystalline silicon support, 2... Silicon oxide film, 3... N-type high concentration buried layer, 4... N-type single crystal silicon region, 5... P-type well region, 6...P type contact region, 7...N type source region, 8-1°8-
2... N type semiconductor region, 9-1.9-2... P type semiconductor region, 10... silicon oxide film, 11... insulating film, 12-1.12-2... gate , 13a... Input terminal, 13b-J... Conductive layer, 41... N-channel MOSFET, 43... Electrostatic protection circuit, 45...
7 input buffer circuits, 50...vertical power MOSFETs
50. 51...P channel MOSFET

Claims (5)

[Claims] (1) A substrate, a single crystal island formed insulated from the substrate and having a region exposed on the surface of the substrate, and a resistive element formed along the inside of an interface between the single crystal island and the substrate. a high impurity concentration buried layer; contact portions formed at both ends of the high impurity concentration buried layer exposed to the surface of the single crystal island; and a semiconductor element formed within the single crystal island. A semiconductor device characterized by: (2) The semiconductor device according to claim 1, wherein the substrate is a dielectric isolation substrate. (3) The semiconductor device according to claim 1, wherein the substrate is a PN junction isolation substrate. (4) The semiconductor element is a MOSFET, and one of the contact portions is connected to an external input terminal, and the other is connected to a drain region of the MOSFET. The semiconductor device according to any one of Item 3. (5) A patent claim characterized in that the MOSFET is a vertical MOSFET, and the conductivity type of the semiconductor region constituting the drain region of the vertical MOSFET and the conductivity type of the high impurity concentration buried layer are the same. 4. The semiconductor device according to item 4.