JP2006093488A

JP2006093488A - Power mosfet

Info

Publication number: JP2006093488A
Application number: JP2004278647A
Authority: JP
Inventors: Shigeyuki Kawabata; 重行川畑
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 2004-09-27
Filing date: 2004-09-27
Publication date: 2006-04-06
Anticipated expiration: 2024-09-27
Also published as: JP4626245B2

Abstract

<P>PROBLEM TO BE SOLVED: To provide a power MOSFET which is reduced in an ON-state resistance per unit area without a reduction of its element breakdown voltage. <P>SOLUTION: The power MOSFET is equipped with: two or more first MOSFET elements which serve as the unit elements and are arranged on a semiconductor single crystal island formed on a support board as separated and insulated with a dielectric insulating layer; and a second MOSFET element which is arranged in a region surrounding the periphery of an area where the first MOSFET elements are arranged. The second MOSFET element is shaped so as to have an opening in a certain area in a planar form, and the first MOSFET elements and the second MOSFET element have the gates in common. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、絶縁ゲート型電力半導体装置に関し、特に複数個の単位素子のＭＯＳＦＥＴ素子に隣接して配置したＭＯＳＦＥＴ素子を備えた複合パワーＭＯＳＦＥＴに関する。 The present invention relates to an insulated gate power semiconductor device, and more particularly, to a composite power MOSFET including a MOSFET element arranged adjacent to a plurality of unit element MOSFET elements.

絶縁ゲート型電力半導体素子であるパワーＭＯＳＦＥＴに動作上から低いオン抵抗が要求される場合には、ドレイン層となる半導体基板の低抵抗率化や、電界緩和層となるドレイン層を薄くすることが有効であることが一般的に知られている。反面、これらの方法はドレイン接合耐圧が低下することは物理現象から明白であるので、ドレイン接合耐圧を維持しながら、低いオン抵抗のパワーＭＯＳＦＥＴを得る為には、ＭＯＳＦＥＴのチャネル長を長くする、つまり単位素子のＭＯＳＦＥＴ素子の配置数を増やすことが一般的に行われている。このように複数の単位ＭＯＳＦＥＴ素子を配置したパワーＭＯＳＦＥＴの例が特許文献１や特許文献２に記載されている。 When a power MOSFET that is an insulated gate type power semiconductor element requires a low on-resistance from the operation, it is possible to reduce the resistivity of the semiconductor substrate serving as the drain layer or to thin the drain layer serving as the electric field relaxation layer. It is generally known to be effective. On the other hand, since it is obvious from a physical phenomenon that the drain junction breakdown voltage decreases in these methods, in order to obtain a low on-resistance power MOSFET while maintaining the drain junction breakdown voltage, the channel length of the MOSFET is increased. That is, increasing the number of MOSFET elements as unit elements is generally performed. Examples of power MOSFETs in which a plurality of unit MOSFET elements are arranged in this way are described in Patent Document 1 and Patent Document 2.

図２を用いて、単位素子のＭＯＳＦＥＴ素子を三角形状に配置し、単位素子のＭＯＳＦＥＴ素子の配置数でオン抵抗を調整する場合を説明する。図２では、単位素子のＭＯＳＦＥＴ８は三角形状に配置してあり、所望のオン抵抗を得るには単位面積当りのオン抵抗から換算した数の単位素子を配置すればよい。図２（ｂ）は図２（ａ）のＡ−Ｂでの断面模式図を示す。図２で符号１はポリシリコンゲート層、２は単位素子のＭＯＳＦＥＴのチャネル層、３は単位素子のＭＯＳＦＥＴのソース層、４はチャネル層と同じ導電型の不純物層、５はソース電極、６は単結晶島を分離する誘電体絶縁層、７はドレイン電極、８は単位素子のＭＯＳＦＥＴ、９はゲート電極、１０はドレイン層と同じ導電型の不純物層、１１は基板から図示していない誘電体で絶縁分離された半導体の単結晶島、１２は半導体の単結晶島と単結晶島を分離する誘電体絶縁層間に形成した埋込み層を示す。 The case where the MOSFET elements of the unit elements are arranged in a triangular shape and the on-resistance is adjusted by the number of the MOSFET elements of the unit elements will be described with reference to FIG. In FIG. 2, the MOSFETs 8 of the unit elements are arranged in a triangle shape, and the number of unit elements converted from the on resistance per unit area may be arranged to obtain a desired on resistance. FIG. 2B is a schematic cross-sectional view taken along line AB of FIG. In FIG. 2, reference numeral 1 denotes a polysilicon gate layer, 2 denotes a channel layer of the MOSFET of the unit element, 3 denotes a source layer of the MOSFET of the unit element, 4 denotes an impurity layer having the same conductivity type as the channel layer, 5 denotes a source electrode, and 6 denotes Dielectric insulating layer that separates single crystal islands, 7 is a drain electrode, 8 is a MOSFET of a unit element, 9 is a gate electrode, 10 is an impurity layer of the same conductivity type as the drain layer, and 11 is a dielectric not shown from the substrate A single crystal island 12 of the semiconductor that is insulated and separated by 12 is a buried layer formed between dielectric insulating layers that separate the single crystal island and the single crystal island of the semiconductor.

特開２０００−５８８２０号公報（図５、図１８）JP 2000-58820 A (FIGS. 5 and 18) 特開平５−３３５５８３号公報（図１、図３）JP-A-5-335583 (FIGS. 1 and 3)

前記従来技術では、素子耐圧を維持しながらパワーＭＯＳＦＥＴのオン抵抗を小さくする為には、単位素子となるＭＯＳＦＥＴの配置数量を増やせば可能である。しかし半導体集積回路のＭＯＳＦＥＴの面積が大きくなると共にゲート容量も増加し、ゲート駆動電流が増加することになり結果的には集積回路の消費電力が増加する問題がある。 In the prior art, in order to reduce the on-resistance of the power MOSFET while maintaining the element withstand voltage, it is possible to increase the number of MOSFETs serving as unit elements. However, there is a problem that the power consumption of the integrated circuit increases as a result of an increase in the area of the MOSFET of the semiconductor integrated circuit and an increase in the gate capacitance and an increase in the gate drive current.

本発明の目的は、素子耐圧の低下なく単位面積あたりのＭＯＳＦＥＴオン抵抗を小さくしたパワーＭＯＳＦＥＴの提供である。 An object of the present invention is to provide a power MOSFET in which the MOSFET on-resistance per unit area is reduced without lowering the device breakdown voltage.

本発明の複合パワーＭＯＳＦＥＴは、１個以上の単位素子となるＭＯＳＦＥＴを配置し、単位素子ＭＯＳＦＥＴを配置した領域の外周部を囲うように形成したＭＯＳＦＥＴとを備え、この外周を囲うように形成したＭＯＳＦＥＴのソースは電極を介して単位素子のＭＯＳＦＥＴのソースと接続した。 The composite power MOSFET of the present invention includes one or more MOSFETs serving as unit elements, and a MOSFET formed so as to surround an outer periphery of a region where the unit element MOSFET is disposed, and is formed so as to surround this outer periphery. The source of the MOSFET was connected to the source of the MOSFET of the unit element via an electrode.

本発明の半導体装置によれば、複数個の単位素子となるＭＯＳＦＥＴを配置した構造において、素子耐圧の低下や駆動電流の増加を発生させずに単位面積のオン抵抗を小さくする事ができる。 According to the semiconductor device of the present invention, in a structure in which a plurality of MOSFETs serving as unit elements are arranged, the on-resistance of a unit area can be reduced without causing a decrease in device breakdown voltage or an increase in drive current.

以下、本発明の詳細について図面を用いながら説明する。 Hereinafter, the details of the present invention will be described with reference to the drawings.

図１は本実施例の複合型パワーＭＯＳＦＥＴの構造模式図である。図１（ａ）は、平面模式図を、図１（ｂ）は図１（ａ）のＡ−Ｂでの断面模式図を示す。図１で符号１はポリシリコンゲート層、２はチャネル層、３はソース層、４はチャネル層と同じ導電型の不純物層、５はソース電極、６は誘電体絶縁層、７はドレイン電極、８は内部に配置した単位素子ＭＯＳＦＥＴ、９はゲート電極、１０はドレイン層と同じ導電型の不純物層、１１は基板、１２は埋込み層、１３は単位素子を取り囲むように形成した外周のＭＯＳＦＥＴを示す。なお、図１ではゲート酸化膜、絶縁膜、及び表面保護膜は省略してある。 FIG. 1 is a schematic view of the structure of a composite power MOSFET according to this embodiment. 1A is a schematic plan view, and FIG. 1B is a schematic cross-sectional view taken along line AB of FIG. 1A. In FIG. 1, reference numeral 1 is a polysilicon gate layer, 2 is a channel layer, 3 is a source layer, 4 is an impurity layer of the same conductivity type as the channel layer, 5 is a source electrode, 6 is a dielectric insulating layer, 7 is a drain electrode, 8 is a unit element MOSFET disposed inside, 9 is a gate electrode, 10 is an impurity layer of the same conductivity type as the drain layer, 11 is a substrate, 12 is a buried layer, and 13 is a peripheral MOSFET formed so as to surround the unit element. Show. In FIG. 1, the gate oxide film, the insulating film, and the surface protective film are omitted.

本実施例のパワーＭＯＳＦＥＴは、シリコン半導体基板である支持体基板２１内に、ＳｉＯ₂ などの誘電体絶縁層６で絶縁分離して形成したシリコン単結晶の単結晶島の基板１１を形成し、この単結晶島の基板１１内に形成した単位素子ＭＯＳＦＥＴ８と、これらの単位素子ＭＯＳＦＥＴ８を取り囲むように形成した外周のＭＯＳＦＥＴ１３とを備え、平面構造上のポリシリコンゲート層１が共通になっている。 In the power MOSFET of this embodiment, a substrate 11 of a single crystal island of silicon single crystal formed by insulating and separating with a dielectric insulating layer 6 such as SiO ₂ is formed in a support substrate 21 which is a silicon semiconductor substrate, A unit element MOSFET 8 formed in the substrate 11 of the single crystal island and an outer peripheral MOSFET 13 formed so as to surround the unit element MOSFET 8 are provided, and the polysilicon gate layer 1 on the planar structure is shared.

本実施例のＭＯＳＦＥＴにゲート電圧を印加すると、電流はソース層３からチャネル層２表面の反転層を介してシリコン単結晶の基板１１に流れ出し、シリコン単結晶の基板１１を介してドレイン層１０に達する。中央部分に配置した単位素子ＭＯＳＦＥＴ８のソース電流は構造上、電流経路が図１（ｂ）の下面方向のみである為に、電流は下面方向への成分が多くを占める。 When a gate voltage is applied to the MOSFET of this embodiment, a current flows from the source layer 3 to the silicon single crystal substrate 11 via the inversion layer on the surface of the channel layer 2 and flows to the drain layer 10 via the silicon single crystal substrate 11. Reach. Since the source current of the unit element MOSFET 8 arranged in the central portion is structurally the current path is only in the lower surface direction of FIG. 1B, the current occupies most components in the lower surface direction.

一方、外周のＭＯＳＦＥＴ１３のソース電流は、図１（ｂ）の下面方向に流れる成分と横面方向に流れる成分とに分かれる。そのため、外周のＭＯＳＦＥＴ１３の平面パターンは形状を長くすること、つまり複数の単位素子ＭＯＳＦＥＴ８が配置された領域の外周部を取り囲むような平面形状にすることで電流密度を上げることが可能となり、よってパワーＭＯＳＦＥＴのオン抵抗を小さくできる。 On the other hand, the source current of the outer peripheral MOSFET 13 is divided into a component flowing in the lower surface direction and a component flowing in the horizontal surface direction in FIG. Therefore, it is possible to increase the current density by increasing the shape of the planar pattern of the MOSFET 13 on the outer periphery, that is, by forming a planar shape surrounding the outer periphery of the region where the plurality of unit element MOSFETs 8 are arranged. The on-resistance of the MOSFET can be reduced.

本実施例では内部に形成した単位素子ＭＯＳＦＥＴ８に比べて、外周のＭＯＳＦＥＴ１３の単位チャネル幅の電流密度を２倍程度に大きくできる。そのために、本実施例のパワーＭＯＳＦＥＴは同じ素子面積に単位素子ＭＯＳＦＥＴ８のみで構成したパワーＭＯＳＦＥＴのオン抵抗の４０〜５０％のオン抵抗にできる。なお、本実施例では単位素子ＭＯＳＦＥＴ８の平面形状が円形であるが、平面形状は、三角形、４辺形、凸多角形、長円等の形状であってもよく、また例えば、正８角形と正方形のように、異なる形状の組合せであっても構わない。また、外周のＭＯＳＦＥＴ１３は本実施例では「Ｃ」形状であるが、「コ」字状であってもよい。 In the present embodiment, the current density of the unit channel width of the outer peripheral MOSFET 13 can be increased to about twice that of the unit element MOSFET 8 formed inside. Therefore, the power MOSFET of the present embodiment can have an on-resistance of 40 to 50% of the on-resistance of the power MOSFET configured with only the unit element MOSFET 8 in the same element area. In this embodiment, the planar shape of the unit element MOSFET 8 is circular. However, the planar shape may be a triangle, a quadrilateral, a convex polygon, an ellipse, or the like. A combination of different shapes such as a square may be used. The outer peripheral MOSFET 13 has a “C” shape in this embodiment, but may have a “U” shape.

本実施例のパワーＭＯＳＦＥＴは、単位素子ＭＯＳＦＥＴ８を配置した領域の外周部にさらに取り囲むように外周のＭＯＳＦＥＴ１３を配置した複合型ＭＯＳＦＥＴにしたので、電流密度を大きくでき、加えて所望のオン抵抗を得るために、単位素子のＭＯＳＦＥＴ数のみを増やす手段より小さな素子面積で済むため、集積回路に好適である。 Since the power MOSFET of the present embodiment is a composite MOSFET in which the outer peripheral MOSFET 13 is disposed so as to further surround the outer peripheral portion of the region in which the unit element MOSFET 8 is disposed, the current density can be increased and a desired on-resistance can be obtained. Therefore, the element area is smaller than the means for increasing only the number of MOSFETs of the unit element, which is suitable for an integrated circuit.

図３は本実施例の複合型パワーＭＯＳＦＥＴの構造模式図である。図３（ａ）は平面模式図を、図３（ｂ）は図３（ａ）のＡ−Ｂでの断面模式図を示す。図３で符号１４は単体素子を完全に取り囲むように形成した外周のＭＯＳＦＥＴ、１５は外周のＭＯＳＦＥＴの外側に形成したチャネルのポリシリコンゲート層、１６は単位素子ＭＯＳＦＥＴ８と外周のＭＯＳＦＥＴの内側に形成したチャネルのポリシリコンゲート層、１７は単位素子ＭＯＳＦＥＴ８と外周のＭＯＳＦＥＴのゲート層を接続する配線層を示す。本実施例は、実施例１では一体になっていたポリシリコンゲート層１を、ポリシリコンゲート層１５とポリシリコンゲート層１６とに分割した他は、実施例１と同様である。 FIG. 3 is a structural schematic diagram of the composite power MOSFET of this embodiment. 3A is a schematic plan view, and FIG. 3B is a schematic cross-sectional view taken along line AB of FIG. 3A. In FIG. 3, reference numeral 14 denotes an outer peripheral MOSFET formed so as to completely surround a single element, 15 a channel polysilicon gate layer formed outside the outer MOSFET, and 16 a unit element MOSFET 8 formed inside the outer MOSFET. A polysilicon gate layer 17 for the channel, and a wiring layer 17 for connecting the unit element MOSFET 8 and the gate layer of the peripheral MOSFET. This embodiment is the same as the first embodiment except that the polysilicon gate layer 1 integrated in the first embodiment is divided into a polysilicon gate layer 15 and a polysilicon gate layer 16.

本実施例によれば、外周のＭＯＳＦＥＴ１４はリング状に形成してあるので、ターミネーション構造に切れ目が無い。そのため、オフ時のドレイン接合に印加される電界が均一化できるので、平面形状における局部的な電界集中を防止できる。また、外周のＭＯＳＦＥＴ１４の電流が一様に流れるようになるので、外周に形成するＭＯＳＦＥＴの局部的な電流集中を回避できる。 According to the present embodiment, the outer peripheral MOSFET 14 is formed in a ring shape, so that there is no break in the termination structure. Therefore, the electric field applied to the drain junction at the time of off can be made uniform, and local electric field concentration in the planar shape can be prevented. Further, since the current of the MOSFET 14 on the outer periphery flows uniformly, local current concentration of the MOSFET formed on the outer periphery can be avoided.

図４は本実施例の複合型パワーＭＯＳＦＥＴの構造模式図である。図４（ａ）は、平面模式図を、図４（ｂ）は図４（ａ）のＡ−Ｂでの断面模式図を示す。本実施例では外周のＭＯＳＦＥＴのソース層１８を単位素子ＭＯＳＦＥＴ８側、つまり内側に形成した点を除いて、その他は実施例２と同様である。 FIG. 4 is a structural schematic diagram of the composite power MOSFET of this embodiment. 4A is a schematic plan view, and FIG. 4B is a schematic cross-sectional view taken along line AB of FIG. 4A. The present embodiment is the same as the second embodiment except that the outer MOSFET source layer 18 is formed on the unit element MOSFET 8 side, that is, the inner side.

本実施例によれば、リング状に形成した外周のＭＯＳＦＥＴ１４のチャネル層２は内側にソース層１８を形成することにより、つまりチャネル層２の外側にチャネル層と同じ導電型の不純物層２２を形成することにより、素子オフ状態時に外周のＭＯＳＦＥＴ１４のドレイン接合付近に発生するリーク電流が、不純物層２２を介してソース電極５に達する為、チャネル層２はトランジスタのベース層としての働きが低減されて、ＭＯＳＦＥＴのトランジスタ動作成分の電流が低下し、安全動作領域が向上する。 According to the present embodiment, the channel layer 2 of the outer peripheral MOSFET 14 formed in a ring shape is formed with the source layer 18 inside, that is, the impurity layer 22 having the same conductivity type as the channel layer is formed outside the channel layer 2. As a result, a leak current generated near the drain junction of the outer MOSFET 14 in the element-off state reaches the source electrode 5 through the impurity layer 22, so that the channel layer 2 functions as a base layer of the transistor. The current of the transistor operation component of the MOSFET is reduced, and the safe operation region is improved.

図５は本実施例の複合型パワーＭＯＳＦＥＴの構造模式図である。図５（ａ）は、平面模式図を、図５（ｂ）は図５（ａ）のＡ−Ｂ間での断面模式図を示す。本実施例では外周のＭＯＳＦＥＴ１４の外側に形成したゲート電極２０と、内部の単位素子ＭＯＳＦＥＴ８と外周のＭＯＳＦＥＴ１４の内側に形成したＭＯＳＦＥＴのゲート電極１９を個別に取り出した点を除いて、その他は実施例２と同様である。 FIG. 5 is a structural schematic diagram of the composite power MOSFET of the present embodiment. 5A is a schematic plan view, and FIG. 5B is a schematic cross-sectional view taken along the line A-B in FIG. 5A. In this embodiment, except that the gate electrode 20 formed outside the outer MOSFET 14 and the internal unit element MOSFET 8 and the gate electrode 19 of the MOSFET formed inside the outer MOSFET 14 are individually taken out, the other embodiments. Same as 2.

本実施例の半導体装置によれば、外周のＭＯＳＦＥＴ１４に形成するゲート電極２０を内側に形成したＭＯＳＦＥＴのゲート電極１９より、オン時には遅くゲート電圧を印加し、オフ時には速くゲート電圧を降下することにより電流が集中することを回避して外周のＭＯＳＦＥＴ１４の破壊耐量を改善できる。 According to the semiconductor device of the present embodiment, the gate voltage is applied later than the gate electrode 19 of the MOSFET in which the gate electrode 20 formed on the outer peripheral MOSFET 14 is formed on the inner side, and the gate voltage is quickly lowered when turned off. It is possible to improve the breakdown tolerance of the MOSFET 14 on the outer periphery by avoiding current concentration.

図６は本実施例の複合型パワーＭＯＳＦＥＴの構造模式図である。図６（ａ）は、平面模式図を、図６（ｂ）は図６（ａ）のＡ−Ｂ間での断面模式図を示す。本実施例では外周のＭＯＳＦＥＴ１４の外側に形成したポリシリコンゲート層１５と、ソース電極５とを共通接続した点を除き、その他は実施例３と同様である。 FIG. 6 is a structural schematic diagram of the composite power MOSFET of this embodiment. 6A is a schematic plan view, and FIG. 6B is a schematic cross-sectional view taken along a line AB in FIG. 6A. This embodiment is the same as the third embodiment except that the polysilicon gate layer 15 formed outside the outer peripheral MOSFET 14 and the source electrode 5 are connected in common.

本実施例の半導体装置によれば、外周のＭＯＳＦＥＴ１４の外側に形成したポリシリコンゲート層１５とソース電極５とを共通接続することにより、ポリシリコンゲート層１５の外周側は、素子がオフ状態時には電界緩和に寄与する。 According to the semiconductor device of this embodiment, the polysilicon gate layer 15 formed outside the outer peripheral MOSFET 14 and the source electrode 5 are connected in common, so that the outer peripheral side of the polysilicon gate layer 15 is in the off state. Contributes to electric field relaxation.

実施例１の複合型パワーＭＯＳＦＥＴの構造模式図であり、（ａ）は平面模式図、（ｂ）はＡ−Ｂでの断面模式図である。It is a structure schematic diagram of composite type power MOSFET of Example 1, (a) is a plane schematic diagram, (b) is a cross-sectional schematic diagram in AB. 従来技術の基本素子を幾何学的に配置した場合の半導体装置の模式図であり、（ａ）は平面模式図、（ｂ）はＡ−Ｂでの断面模式図である。It is the schematic diagram of the semiconductor device at the time of arranging the basic element of a prior art geometrically, (a) is a plane schematic diagram, (b) is a cross-sectional schematic diagram in AB. 実施例２の複合型パワーＭＯＳＦＥＴの構造模式図であり、（ａ）は平面模式図、（ｂ）はＡ−Ｂでの断面模式図である。It is a structure schematic diagram of composite type power MOSFET of Example 2, (a) is a plane schematic diagram, (b) is a cross-sectional schematic diagram in AB. 実施例３の複合型パワーＭＯＳＦＥＴの構造模式図であり、（ａ）は平面模式図、（ｂ）はＡ−Ｂでの断面模式図である。It is a structure schematic diagram of composite type power MOSFET of Example 3, (a) is a plane schematic diagram, (b) is a cross-sectional schematic diagram in AB. 実施例４の複合型パワーＭＯＳＦＥＴの構造模式図であり、（ａ）は平面模式図、（ｂ）はＡ−Ｂでの断面模式図である。It is a structure schematic diagram of composite type power MOSFET of Example 4, (a) is a plane schematic diagram, (b) is a cross-sectional schematic diagram in AB. 実施例５の複合型パワーＭＯＳＦＥＴの構造模式図であり、（ａ）は平面模式図、（ｂ）はＡ−Ｂでの断面模式図である。It is a structure schematic diagram of composite type power MOSFET of Example 5, (a) is a plane schematic diagram, (b) is a cross-sectional schematic diagram in AB.

Explanation of symbols

１、１５、１６…ポリシリコンゲート層、２…チャネル層、３、１８…ソース層、４、２２…チャネル層と同じ導電型の不純物層、５…ソース電極、６…誘電体絶縁層、７…ドレイン電極、８…単位素子ＭＯＳＦＥＴ、９、１９、２０…ゲート電極、１０…ドレイン層と同じ導電型の不純物層、１１…基板、１２…埋込み層、１３、１４…外周のＭＯＳＦＥＴ、１７…配線層、２１…支持体基板、２３…外周ＭＯＳＦＥＴの外側に形成したポリシリコンのコンタクト。
DESCRIPTION OF SYMBOLS 1, 15, 16 ... Polysilicon gate layer, 2 ... Channel layer, 3, 18 ... Source layer, 4, 22 ... Impurity layer of the same conductivity type as a channel layer, 5 ... Source electrode, 6 ... Dielectric insulating layer, 7 ... Drain electrode, 8 ... Unit element MOSFET, 9, 19, 20 ... Gate electrode, 10 ... Impurity layer of the same conductivity type as the drain layer, 11 ... Substrate, 12 ... Built-in layer, 13, 14 ... MOSFET on the outer periphery, 17 ... Wiring layer, 21... Support substrate, 23... Polysilicon contact formed outside the outer peripheral MOSFET.

Claims

In a power MOSFET in which a plurality of unit elements are arranged on a semiconductor substrate,
A single crystal island of a semiconductor single crystal formed by isolating and separating the power MOSFET on a support substrate with a dielectric insulating layer;
A first MOSFET element that is a plurality of the unit elements disposed on the single crystal island;
A second MOSFET element disposed in a portion surrounding the outer periphery of the region where the first MOSFET element is disposed;
A power MOSFET, wherein the planar shape of the second MOSFET element is a partly open shape, and the gate of the first MOSFET element and the gate of the second MOSFET element are made common.

The power MOSFET according to claim 1,
A power MOSFET, wherein a channel layer of the second MOSFET element has a ring shape, and a gate of the first MOSFET element and a gate of the second MOSFET element are connected by an electrode wiring layer.

The power MOSFET according to claim 1 or 2,
A power MOSFET wherein the source layer of the second MOSFET element is formed on the side where the first MOSFET element is disposed.

The power MOSFET according to claim 2, wherein
A power MOSFET, wherein a gate electrode of the first MOSFET element and a gate electrode of the second MOSFET element are separated, and different gate voltages can be applied to the respective electrodes.

The power MOSFET according to claim 3, wherein
A power MOSFET wherein a polysilicon layer outside the second MOSFET element is connected to a source electrode voltage.