JPS58115858A - Mis type semiconductor device - Google Patents

Abstract

PURPOSE:To enable to isolate electrically between elements, and to enable to constitute an integrated circuit containing the MIS type semiconductor element by a method wherein a dielectric region is formed in the inside wall of a concave part provided in a substrate, and the MIS type semiconductor element is provided on the region thereof. CONSTITUTION:Patterning is performed according to thermal oxidation and photo etching to remove an SiO2 film 13 corresponding to the central part between source regions 15, and anisotropic etching is performed to Si according to the KOH etching liquid using the pattern thereof as the mask to provide a V- shaped groove having depth to reach an N type region 12. Then the surface of the substrate is thermally oxidized to form an SiO2 film 13'', and after the SiO2 film 13 on the surface of the substrate at the parts corresponding to a drain region 11 and a source region 15 are removed and openings for lead out of electrodes are formed, aluminum, etc., is evaporated to provide the drain electrode 16, the source electrode 17, and the gate electrode 18. At this time, the gate electrode 18 is arranged in the gate region 14 in the V-shaped groove interposing the SiO2 film 13'' between them.

Description

[Detailed description of the invention] (1) Origin @O technology field The present invention relates to an MX8flk semiconductor device.

(2) Prior art and problems In an M-engineered 8-board semiconductor device, a drain or source region is arranged so as to surround a channel region in order to increase speed. There is a medium conductor device having a structure in which the drain region is arranged separately from the source region, the channel region is exposed and a # suitable for the drain or source region is provided, and the gate electrode is arranged in the line trench. MI Nichinada semiconductor devices with this structure are commonly known as V-shaped grooves.
The well-known problems of the -Mos'1 field effect transistor will be explained by referring to one of the conventional examples, the 'V-MO8 electric field infant transistor.

Figure 1 is a cross-sectional view of a V-MO+3 field effect transistor.In Figure 1, 1 is n-type silicon (FII).
Substrate/drain region, 2 is n-type 81 region, 3 is p-type channel region, number is needle-shaped north region, 5 is silicon dioxide (
'iio*) Insulating film, 6 indicates a source electrode, 1 indicates a gate electrode, and 8 indicates a drain electrode.

The structure of this element will be briefly explained.

The substrate 1 becomes the drain region of the V-MO8 field effect transistor, and the gate electrode 7 is the n-type 8 in the center of the source region.
A V-shaped groove suitable for one dipping area is provided, and a drain electrode 8 is disposed in the channel region 3 in the groove with an insulating film 5f interposed therebetween.
is provided on the entire back surface of the substrate l.

When V-MO8 field effect transistor elements having such a structure are integrated, the drain electrodes of all V-MOB@field effect transistor elements are shared, which hinders the operation of the element and also causes damage to the substrate 1. is also in the operating region, so the fl that cannot be electrically reduced between lA
There is ljli.

Also, like a bipolar integrated circuit, an n
Although it is possible to form a decagonal S1 drain/layer and construct a v-MOS field effect transistor.

Since the isolation between each element is performed by a p-n11 reverse bias, breakdown occurs in the V-MO13 field effect transistor, which operates at a high voltage.

It has the disadvantage that it cannot perform inter-honko-bun. Additionally, 41 complicated steps are required to take out the entire thickness of the drain electrode and to isolate the elements.

(3) Object of the Invention An object of the present invention is to provide an integrated circuit including an MIB type semiconductor element having a gate electrode arranged in the groove described above and having a nine-layer structure.

(4) Structure of the Invention The present invention provides a substrate with a recess, a dielectric layer on the entire inner wall of the substrate recess, a semiconductor layer on the dielectric layer in the recess, and a drain ta and a source in the semiconductor layer. a channel region, a source or drain region, the drain or source region is arranged to surround the channel region, and the source or drain region is arranged separated from the drain or source region via the channel region. A trench is provided in which the channel region is exposed and reaches the drain or source region, and a gate electrode is disposed in the line trench.

providing a recess in the substrate and forming a dielectric region on the inner wall of the recess;
By providing an MIS type semiconductor element on the electric body region within the recess, the element formed within the recess can be electrically separated from nine other elements formed on the same substrate. can. Furthermore, it becomes easier to expose the top surface of the dray/four poles.

(0) Embodiments of the Invention - Hereinafter, as an embodiment of the present invention, a description will be given of the manufacturing process of a V-MO8 field effect transistor. FIGS. 2(a) to (r) are v-
This is a cross-sectional view of an MO8' wax field effect transistor.

Potassium hydroxide (KO
H) Process: SL is anisotropically etched using a etching solution to form four parts, and dielectric materials such as magnesia spinel, n-type S1, and n-sugi I:11 are primarily grown in the recesses by vapor phase growth. dielectric layer 10, n + 10-shaped rain region 11
1. After forming the n shadow area 12.

The surface of the substrate 9 is polished using a chemical mechanical polishing method until it becomes flat (Fig. 42 (a)).
. Next, the surface of the base lfL is thermally oxidized to form silicon dioxide (81
0t) [13 is to be formed (FIG. 2(b)), and photo-etching is performed to form the gate fly regionj)810. The film 13 is patterned and subjected to the step S10. Using the film 13 as a mask, boron (B) 4 is diffused or ion-implanted into the n shadow region 12 to form a p-type gate region 14 (FIG. 2(C)). Furthermore, in order to form a source region, phosphorus (phosphorus), etc., which has been patterned by thermal oxidation and photoetching is used as a mask, and is diffused into the p-type gate region 14.
An n-type source region 15 is formed (FIG. 2(d)). Subsequently, thermal oxidation and photoetching are carried out to remove the S i O and oxidation layer 3 in the center of the source region 15, and the S10! Using the film 13 as a mask, s1'2 anisotropic etching is performed using a KOH etching solution to form a V-shaped groove with a depth that reaches the n-type region (
Figure 2(e)).

Next, the substrate surface is thermally oxidized to form a 81Q film (gate oxide film).
13' (Fig. 2(f)), the drain/
After removing the portions of the Sin film 13 corresponding to the region 11 and the source region 15 and forming a margin for exposing the electrode region, aluminum (mutt) or the like is deposited to form the drain electrode 16.
A source electrode ``1'' and a gate electrode 18 are provided. At this time, the gate electrode 18 is placed in the gate region 1 in the V-shaped groove through the film 13' (FIG. 2(t)).
).

According to one embodiment of the present invention, the V-MO8 field effect transistor device is insulated by the magnesia spinel or dielectric layer 10 formed in the recess, so that a plurality of V-MO8 field effect transistor devices can be mounted on the same substrate. A structure t that can constitute a field effect transistor element and in which the drain region 11 is separated from the substrate 9
-It can be achieved. Also.

A hybrid integrated circuit with a V-MO8 field effect transistor device and a conventional M2S field effect transistor device or a bipolar transistor device is also possible.

(6) Effects of the Invention According to the present invention, the tooth region of the drain region is arranged so as to face the channel region, and the source or drain region is arranged separated from the drain or source region via the channel region, (1) An M having a structure in which a groove is provided in which the channel region is exposed and reaches the drain or source region, and a gate electrode is disposed in the groove.
This makes it possible to perform tlLfi-like separation between elements of a micro-sm semiconductor element, and to configure the MI8m conductor element circuit.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a conventional V-MO8 field effect transistor, and FIGS. 2(a) to (f) are cross-sectional views of a V-MO8 field effect transistor showing a manufacturing factory according to an embodiment of the present invention. . l: 4-plate/drain region, 3.14 channel region,
4,15 source area, 5.13.13', 13's
10. membrane, 6. l'7:/-, *electrode, '/, 1B
Gate electrode, 8, 16 Drain electrode, 10 - Electrical layer, 11 Drain region 7 Figure name 2 Figure (S(d) Cf) Figure 2

Claims (1)

[Claims] Gold film on the concave part of the board, trout electric body + mt on the entire surface of the inner wax of the concave part of the board
- providing a semiconductor layer on the dielectric layer in the cough recess, and providing the semiconductor layer with three regions, a drain or north region, a channel region, and a source or drain region, the drain or source region extending beyond the channel region; The source or drain region is arranged so as to surround the drain or source region, and the source or drain region is arranged to be separated from the drain or source region via the channel region, and a trench is provided in which the channel region extends and the drain reaches the source region. An MI8 semiconductor device characterized in that a gate electrode is arranged in a line groove.